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George Moussalem
ed5789ba7c arm64: dts: qcom: ipq5018: Add crypto nodes 
IPQ5018 uses Qualcomm QCE crypto engine v5.1 which is already supported.
So let's add the dts nodes for its DMA v1.7.4 and QCE itself.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250721-ipq5018-crypto-v3-1-b9cd9b0ef147@outlook.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 16:44:43 -05:00
George Moussalem
bf258fdaa2 arm64: dts: qcom: ipq5018: add PRNG node 
PRNG inside of IPQ5018 is already supported, so let's add the node for it.

Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250721-ipq5018-prng-v1-1-474310e0575d@outlook.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 16:44:37 -05:00
Raviteja Laggyshetty
bebacd802b arm64: dts: qcom: qcs8300: Add EPSS l3 interconnect provider node and CPUCP OPP tables to scale DDR/L3 
Add Epoch Subsystem (EPSS) L3 interconnect provider node and OPP tables
required to scale DDR and L3 per freq-domain on QCS8300 platform.
As QCS8300 and SA8775P SoCs have same EPSS hardware, added SA8775P
compatible as fallback for QCS8300 EPSS device node.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Co-developed-by: Imran Shaik <quic_imrashai@quicinc.com>
Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250722055039.135140-2-raviteja.laggyshetty@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 16:43:43 -05:00
Qiang Yu
df758a868d arm64: dts: qcom: x1e80100-qcp: enable pcie3 x8 slot for X1E80100-QCP 
Add perst, wake and clkreq sideband signals and required regulators in
PCIe3 controller and PHY device tree node. Describe the voltage rails of
the x8 PCI slots for PCIe3 port.

Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Signed-off-by: Wenbin Yao <quic_wenbyao@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250722091151.1423332-4-quic_wenbyao@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 16:43:07 -05:00
Qiang Yu
6facfaff0f arm64: dts: qcom: x1e80100: add bus topology for PCIe domain 3 
Add pcie3_port node to represent the PCIe bridge of PCIe3 so that PCI slot
voltage rails can be described under this node in the board's dts.

Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Signed-off-by: Wenbin Yao <quic_wenbyao@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250722091151.1423332-3-quic_wenbyao@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 16:43:07 -05:00
Krzysztof Kozlowski
f93e588213 dt-bindings: arm: qcom: Drop redundant free-form SoC list 
The schema and Devicetree specification defines how list of top-level
compatibles should be created, thus first paragraph explaining this is
completely redundant.

The list of SoCs is redundant as well, because the schema lists them.
On the other hand, Linux kernel should not be place to store marketing
names of some company products, so such list is irrelevant here.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250724132436.77160-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 16:17:12 -05:00
Krzysztof Kozlowski
8def31f8c1 arm64: dts: qcom: sm8650: Sort nodes by unit address 
Qualcomm DTS uses sorting of MMIO nodes by the unit address, so move
few nodes in SM8650 DTSI to fix that.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250727193652.4029-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 13:22:44 -05:00
Val Packett
1a67f85c69 dt-bindings: arm: qcom: Add Dell Latitude 7455 
Document the X1E80100-based Dell Latitude 7455 laptop.

Signed-off-by: Val Packett <val@packett.cool>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250525095341.12462-3-val@packett.cool
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 13:22:44 -05:00
George Moussalem
8d2a8e8dc4 arm64: dts: qcom: ipq5018: Add SPI nand support 
Add QPIC SPI NAND support for IPQ5018 SoC.

Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250501-ipq5018-spi-qpic-snand-v1-2-31e01fbb606f@outlook.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 13:22:44 -05:00
Bartosz Golaszewski
25197809e7 arm64: dts: qcom: sdm845-samsung-starqltechn: fix GPIO lookup flags for i2c SDA and SCL 
The I2C GPIO bus driver enforces the SDA and SCL pins as open-drain
outputs but the lookup flags in the DTS don't reflect that triggering
warnings from GPIO core. Add the appropriate flags.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Link: https://lore.kernel.org/r/20250811-qcom-gpio-lookup-open-drain-v1-3-b5496f80e047@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 13:22:44 -05:00
Bartosz Golaszewski
f07f492773 arm64: dts: qcom: qrb4210-rb2: fix GPIO lookup flags for i2c SDA and SCL 
The I2C GPIO bus driver enforces the SDA and SCL pins as open-drain
outputs but the lookup flags in the DTS don't reflect that triggering
warnings from GPIO core. Add the appropriate flags.

Reported-by: Alexey Klimov <alexey.klimov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Link: https://lore.kernel.org/r/20250811-qcom-gpio-lookup-open-drain-v1-2-b5496f80e047@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 13:22:44 -05:00
Bartosz Golaszewski
b2659ddbc2 arm64: dts: qcom: qrb2210-rb1: fix GPIO lookup flags for i2c SDA and SCL 
The I2C GPIO bus driver enforces the SDA and SCL pins as open-drain
outputs but the lookup flags in the DTS don't reflect that triggering
warnings from GPIO core. Add the appropriate flags.

Tested-by: Alexey Klimov <alexey.klimov@linaro.org>
Reported-by: Alexey Klimov <alexey.klimov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Link: https://lore.kernel.org/r/20250811-qcom-gpio-lookup-open-drain-v1-1-b5496f80e047@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 13:22:44 -05:00
Luca Weiss
35e0b432d5 arm64: dts: qcom: pmk8550: Correct gpio node name 
The reg for the GPIOs is 0xb800 and not 0x8800, so fix this copy-paste
mistake.

Fixes: e9c0a4e484 ("arm64: dts: qcom: Add PMK8550 pmic dtsi")
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250625-pmk8550-gpio-name-v1-1-58402849f365@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 13:22:44 -05:00
Yu Zhang(Yuriy)
b5634bf979 arm64: dts: qcom: qcs615-ride: Enable WiFi/BT nodes 
Enable WiFi/BT on qcs615-ride by adding a node for the PMU module of the
WCN6855 and assigning its LDO power outputs to the existing WiFi/BT
module.

Signed-off-by: Yu Zhang (Yuriy) <yu.zhang@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250727-615-v7-2-2adb6233bbb9@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 13:22:44 -05:00
Yu Zhang(Yuriy)
e13555a3e1 arm64: dts: qcom: qcs615: add a PCIe port for WLAN 
Add an original PCIe port for WLAN. This port will be referenced and
supplemented by specific WLAN devices.

Signed-off-by: Yu Zhang (Yuriy) <yu.zhang@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250727-615-v7-1-2adb6233bbb9@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 13:22:44 -05:00
Krishna chaitanya chundru
414be2b5a7 arm64: dts: qcom: qcs615-ride: Enable PCIe interface 
Add platform configurations in devicetree for PCIe, board related
gpios, PMIC regulators, etc.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250725112346.614316-3-ziyue.zhang@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 13:22:44 -05:00
Krishna chaitanya chundru
718cc7542a arm64: dts: qcom: qcs615: enable pcie 
Add configurations in devicetree for PCIe0, including registers, clocks,
interrupts and phy setting sequence.

Add PCIe lane equalization preset properties for 8 GT/s.

Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250725112346.614316-2-ziyue.zhang@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 13:22:44 -05:00
George Moussalem
f5f2b835e3 arm64: dts: qcom: ipq5018: Add GE PHY to internal mdio bus 
The IPQ5018 SoC contains an internal GE PHY, always at phy address 7.
As such, let's add the GE PHY node to the SoC dtsi.

The LDO controller found in the SoC must be enabled to provide constant
low voltages to the PHY. The mdio-ipq4019 driver already has support
for this, so adding the appropriate TCSR register offset.

In addition, the GE PHY outputs both the RX and TX clocks to the GCC
which gate controls them and routes them back to the PHY itself.
So let's create two DT fixed clocks and register them in the GCC node.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Link: https://lore.kernel.org/r/20250630-ipq5018-ge-phy-v6-3-01be06378c15@outlook.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 13:22:44 -05:00
George Moussalem
1e2261a669 arm64: dts: qcom: ipq5018: Add MDIO buses 
IPQ5018 contains two mdio buses of which one bus is used to control the
SoC's internal GE PHY, while the other bus is connected to external PHYs
or switches.

There's already support for IPQ5018 in the mdio-ipq4019 driver, so let's
simply add the mdio nodes for them.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Link: https://lore.kernel.org/r/20250630-ipq5018-ge-phy-v6-2-01be06378c15@outlook.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 13:22:43 -05:00
Luo Jie
e5612530e3 arm64: dts: qcom: Update IPQ5424 xo_board to use fixed factor clock 
xo_board is fixed to 24 MHZ, which is routed from WiFi output clock
48 MHZ (also being the reference clock of CMN PLL) divided 2 by
analog block routing channel.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
Link: https://lore.kernel.org/r/20250610-qcom_ipq5424_cmnpll-v3-4-ceada8165645@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 13:22:43 -05:00
Luo Jie
682c9d0e78 arm64: dts: qcom: ipq5424: Add CMN PLL node 
Add CMN PLL node for enabling output clocks to the networking
hardware blocks on IPQ5424 devices.

The reference clock of CMN PLL is routed from XO to the CMN PLL
through the internal WiFi block.
.XO (48 MHZ or 96 MHZ or 192 MHZ)-->WiFi (multiplier/divider)-->
48 MHZ to CMN PLL.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
Link: https://lore.kernel.org/r/20250610-qcom_ipq5424_cmnpll-v3-3-ceada8165645@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 13:22:43 -05:00
Luca Weiss
5ce2aa520d arm64: dts: qcom: sm7225-fairphone-fp4: Enable USB audio offload support 
Enable USB audio offloading which allows to play audio via a USB-C
headset with lower power consumption and enabling some other features.

This can be used like the following:

  $ amixer -c0 cset name='USB_RX Audio Mixer MultiMedia1' On
  $ aplay --device=plughw:0,0 test.wav

Compared to regular playback to the USB sound card no xhci-hcd
interrupts appear during playback, instead the ADSP will be handling the
USB transfers.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250501-fp4-usb-audio-offload-v2-5-30f4596281cd@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 13:22:43 -05:00
Luca Weiss
bbc5a9b5d9 arm64: dts: qcom: sm6350: Add q6usbdai node 
Add a node for q6usb which handles USB audio offloading, allowing to
play audio via a USB-C headset with lower power consumption and enabling
some other features.

We also need to set num-hc-interrupters for the dwc3 for the q6usb to be
able to use its sideband interrupter.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250501-fp4-usb-audio-offload-v2-4-30f4596281cd@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 13:22:43 -05:00
Viken Dadhaniya
6a5e9b9738 arm64: dts: qcom: qcs615: add missing dt property in QUP SEs 
Add the missing required-opps and operating-points-v2 properties to
several I2C, SPI, and UART nodes in the QUP SEs.

Fixes: f6746dc9e3 ("arm64: dts: qcom: qcs615: Add QUPv3 configuration")
Cc: stable@vger.kernel.org
Signed-off-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250630064338.2487409-1-viken.dadhaniya@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 13:22:43 -05:00
Jens Glathe
ebf6fc452a arm64: dts: qcom: x1e80100-lenovo-yoga-slim7x: add Bluetooth support 
To enable Bluetooth pwrseq appears to be required for the WCN7850.
Add the nodes from QCP, add the TODO hint for vreg_wcn_0p95 and
vreg_wcn_1p9
Add uart14 for the BT interface.

Tested-by: Anthony Ruhier <aruhier@mailbox.org>
Signed-off-by: Jens Glathe <jens.glathe@oldschoolsolutions.biz>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250624-slim7x-bt-v3-1-7ada18058419@oldschoolsolutions.biz
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 13:22:43 -05:00
Akhil P Oommen
1aa0b4e364 arm64: dts: qcom: x1p42100: Add GPU support 
X1P42100 SoC has a new GPU called Adreno X1-45 which is a smaller
version of Adreno X1-85 GPU. Describe this new GPU and also add
the secure gpu firmware path that should used for X1P42100 CRD.

Tested-by: Jens Glathe <jens.glathe@oldschoolsolutions.biz>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Tested-by: Aleksandrs Vinarskis <alex.vinarskis@gmail.com> # x1-26-100
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250623-x1p-adreno-v4-4-d2575c839cbb@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 13:22:43 -05:00
Konrad Dybcio
71ef5e99e9 arm64: dts: qcom: sm8250: Drop venus-enc/decoder node 
Commit 687bfbba5a ("media: venus: Add support for static video
encoder/decoder declarations") invalidates these empty nodes.

Get rid of them.

Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250614-topic-encdec-v1-4-f974c3e9cb43@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 13:22:43 -05:00
Konrad Dybcio
dce1122f07 arm64: dts: qcom: sdm845: Drop venus-enc/decoder node 
Commit 687bfbba5a ("media: venus: Add support for static video
encoder/decoder declarations") invalidates these empty nodes.

Get rid of them.

Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250614-topic-encdec-v1-3-f974c3e9cb43@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 13:22:43 -05:00
Konrad Dybcio
1f67c23f98 arm64: dts: qcom: sc7180: Drop venus-enc/decoder node 
Commit 687bfbba5a ("media: venus: Add support for static video
encoder/decoder declarations") invalidates these empty nodes.

Get rid of them.

Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250614-topic-encdec-v1-2-f974c3e9cb43@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 13:22:43 -05:00
Konrad Dybcio
8ff47ada5e arm64: dts: qcom: msm8916: Drop venus-enc/decoder node 
Commit 687bfbba5a ("media: venus: Add support for static video
encoder/decoder declarations") invalidates these empty nodes.

Get rid of them.

Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250614-topic-encdec-v1-1-f974c3e9cb43@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 13:22:43 -05:00
Dmitry Baryshkov
9af4e53512 arm64: dts: qcom: rename qcs615.dtsi to sm6150.dtsi 
The established practice is to have the base DTSI file named after the
base SoC name (see examples of qrb5165-rb5.dts vs sm8250.dtsi,
qrb2210-rb1.dts vs qcm2290.dtsi, qrb4210-rb2.dts vs sm4250.dtsi vs
sm6115.dtsi). Rename the SoC dtsi file accordingly and add "qcom,sm6150"
as a fallback compat string.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250604-qcs615-sm6150-v1-2-2f01fd46c365@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 13:22:43 -05:00
Dmitry Baryshkov
3e0252ea5d dt-bindings: arm: qcom: add qcom,sm6150 fallback compatible to QCS615 
QCS615 SoC is based on the earlier mobile chip SM6150. Add corresponding
compatible string to follow established practice for IoT chips.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250604-qcs615-sm6150-v1-1-2f01fd46c365@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 13:22:43 -05:00
Dmitry Baryshkov
0403e42f2f arm64: dts: qcom: sa8775p: rename bus clock to follow the bindings 
DT bindings for the DPU SA8775P declare the first clock to be "nrt_bus",
not just "bus". Fix the DT file accordingly.

Fixes: 2f39d2d46c ("arm64: dts: qcom: sa8775p: add display dt nodes for MDSS0 and DPU")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250602-sa8775p-fix-dts-v1-1-f9f6271b33a3@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 13:22:42 -05:00
Dmitry Baryshkov
c02716951e arm64: dts: qcom: sdm850-lenovo-yoga-c630: add routing for second USB connector 
On Lenovo Yoga C630 second (left) Type-C port is not connected to the
SoC directly. Instead it has a USB hub, which also powers on the onboard
USB camera. Describe these signal lines properly.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250608-c630-ports-v1-1-e4951db96efa@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 13:22:42 -05:00
Dmitry Baryshkov
e2a01c3b10 arm64: dts: qcom: sar2130p: use defines for DSI PHY clocks 
Use defined IDs to reference DSI PHY clocks instead of using raw
numbers.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250618-sar2130p-fix-mdss-v1-3-78c2fb9e9fba@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 13:22:42 -05:00
Dmitry Baryshkov
b1f622224b arm64: dts: qcom: sar2130p: correct VBIF region size for MDSS 
Correct the VBIF region size for the display device on the SAR1230P
platform.

Fixes: 541d0b2f4d ("arm64: dts: qcom: sar2130p: add display nodes")
Reported-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Closes: https://lore.kernel.org/all/c14dfd37-7d12-40c3-8281-fd0a7410813e@oss.qualcomm.com/
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250618-sar2130p-fix-mdss-v1-2-78c2fb9e9fba@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 13:22:42 -05:00
Dmitry Baryshkov
5bde57b9cd arm64: dts: qcom: sar2130p: use TAG_ALWAYS for MDSS's mdp0-mem path 
Switch the main memory interconnect of the MDSS device to use
QCOM_ICC_TAG_ALWAYS instead of _ACTIVE_ONLY.

Fixes: 541d0b2f4d ("arm64: dts: qcom: sar2130p: add display nodes")
Suggested-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250618-sar2130p-fix-mdss-v1-1-78c2fb9e9fba@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 13:22:42 -05:00
Dmitry Baryshkov
e08d75e483 arm64: dts: qcom: sdm845: rename DisplayPort labels 
Rename DP labels to have mdss_ prefix, so that corresponding device
nodes are grouped together.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250621-sdm845-dp-rename-v1-1-6f7f13443b43@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 13:22:42 -05:00
Sricharan Ramabadhran
450a80623e arm64: dts: qcom: ipq5018: Add tsens node 
IPQ5018 has tsens V1.0 IP with 5 sensors, though 4 are in use.
There is no RPM, so tsens has to be manually enabled. Adding the tsens
and nvmem nodes and adding 4 thermal sensors (zones). The critical trip
temperature is set to 120'C with an action to reboot.

In addition, adding a cooling device to the CPU thermal zone which uses
CPU frequency scaling.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
[bjorn: Added tsens-v1 fallback compatible, per binding]
Link: https://lore.kernel.org/r/20250612-ipq5018-tsens-v13-2-a210f3683240@outlook.com
 2025-08-11 13:22:42 -05:00
Neil Armstrong
77e1f16b93 arm64: dts: qcom: sm8650: Flatten the USB nodes 
Transition the USB controllers found in the SM8650 SoC to the newly
introduced, flattened representation of the Qualcomm USB block.

The reg and interrupts properties from the usb child node are merged
with their counterpart in the outer node, remaining properties and child
nodes are simply moved.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250811-topic-sm8x50-usb-flatten-v2-2-0bbb3ac292e4@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 10:04:35 -05:00
Neil Armstrong
33450878ad arm64: dts: qcom: sm8550: Flatten the USB nodes 
Transition the USB controllers found in the SM8550 SoC to the newly
introduced, flattened representation of the Qualcomm USB block.

The reg and interrupts properties from the usb child node are merged
with their counterpart in the outer node, remaining properties and child
nodes are simply moved.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250811-topic-sm8x50-usb-flatten-v2-1-0bbb3ac292e4@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 10:04:35 -05:00
Wasim Nazir
99ea5a0d6b arm64: dts: qcom: Add lemans evaluation kit (EVK) initial board support 
Lemans EVK is an IoT board without safety monitoring feature of
Safety Island(SAIL) subsystem.

Lemans EVK is single board supporting these peripherals:
  - Storage: 2 × 128 GB UFS, micro-SD card, EEPROMs for MACs,
    eMMC on mezzanine card
  - Audio/Video, Camera & Display ports
  - Connectivity: RJ45 2.5GbE, WLAN/Bluetooth, CAN/CAN-FD
  - Sensors: IMU
  - PCIe ports
  - USB & UART ports

On top of lemans EVK board additional mezzanine boards can be stacked
in future.

Implement basic features like uart/ufs to enable 'boot to shell'.

Co-developed-by: Rakesh Kota <quic_kotarake@quicinc.com>
Signed-off-by: Rakesh Kota <quic_kotarake@quicinc.com>
Co-developed-by: Sayali Lokhande <quic_sayalil@quicinc.com>
Signed-off-by: Sayali Lokhande <quic_sayalil@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Wasim Nazir <wasim.nazir@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250803110113.401927-9-wasim.nazir@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-10 21:01:20 -05:00
Wasim Nazir
e9d84a1f8b dt-bindings: arm: qcom: lemans: Add bindings for Lemans Evaluation Kit (EVK) 
Introduce new bindings for the Lemans EVK, an IoT board without safety
features.

Signed-off-by: Wasim Nazir <wasim.nazir@oss.qualcomm.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250803110113.401927-8-wasim.nazir@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-10 21:01:16 -05:00
Wasim Nazir
b4feac9e03 arm64: dts: qcom: lemans: Fix dts inclusion for IoT boards and update memory map 
IoT boards currently inherit the automotive memory map, which is not
suitable for their configuration. This leads to incorrect memory layout
and inclusion of unnecessary carveouts.

Use lemans.dtsi as the base for IoT boards to apply the correct memory
map. Include additional DTSI files as needed to complete the board
configuration.

Update 'model' string to represent these boards as 'lemans'.

Signed-off-by: Wasim Nazir <wasim.nazir@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250803110113.401927-7-wasim.nazir@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-10 21:01:16 -05:00
Wasim Nazir
d39e1d737b arm64: dts: qcom: lemans: Rename sa8775p-pmics.dtsi to lemans-pmics.dtsi 
The existing PMIC DTSI file is named sa8775p-pmics.dtsi, which does not
align with the updated naming convention for Lemans platform components.
This inconsistency can lead to confusion and misalignment with other
platform-specific files.

Rename the file to lemans-pmics.dtsi to reflect the platform naming
convention and improve clarity.

Signed-off-by: Wasim Nazir <wasim.nazir@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250803110113.401927-6-wasim.nazir@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-10 21:01:15 -05:00
Wasim Nazir
76326da895 arm64: dts: qcom: lemans: Refactor ride/ride-r3 boards based on daughter cards 
Ride/Ride-r3 boards used with lemans and derivatives:
  - Are composed of multiple daughter cards (SoC-card, display, camera,
    ethernet, pcie, sensor, front & backplane, WLAN & BT).
  - Across lemans & its derivatives, SoM is changing.
  - Across Ride & Ride-r3 board, ethernet card is changing.

Excluding the differences all other cards i.e SoC-card, display,
camera, PCIe, sensor, front & backplane are same across Ride/Ride-r3
boards used with lemans and derivatives.

Describe all the common cards in lemans-ride-common so that it can be
reused for all the variants of ride & ride-r3 platforms in lemans and
derivatives.

Nacked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Wasim Nazir <wasim.nazir@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250803110113.401927-5-wasim.nazir@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-10 21:01:15 -05:00
Wasim Nazir
4c0c97b95a arm64: dts: qcom: lemans: Separate out ethernet card for ride & ride-r3 
Ride & Ride-r3 in lemans/lemans-auto uses different ethernet cards
with different phy capabilities. Separate out the ethernet card
information from main board so that it can be reused for all the
variants of ride & ride-r3 platforms in lemans/lemans-auto.

Lemans/lemans-auto Ride uses 1G phy while Lemans/lemans-auto Ride-r3
uses 2.5G phy.

Introduce ethernet cards with 1G & 2.5G phy capabilities respectively:
  *-88ea1512.dtsi is for 2x 1G - SGMII (Marvell 88EA1512-B2) phy
  *-aqr115c.dtsi is for 2x 2.5G - HSGMII (Marvell AQR115c) phy

Nacked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Wasim Nazir <wasim.nazir@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250803110113.401927-4-wasim.nazir@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-10 21:01:15 -05:00
Wasim Nazir
24dc241bdd arm64: dts: qcom: lemans: Update memory-map for IoT platforms 
The "automotive" memory map is the special case for the Lemans
configuration described by this dtsi, move it aside and use the IoT
memory map as the baseline.

Introduce "lemans-auto" as a derivative of "lemans" that retains the
old automotive memory map to support legacy use cases.

As part of the IoT memory map updates:
  - Introduce new carveouts for gunyah_md and pil_dtb. Adjust the size and
    base address of the PIL carveout to accommodate these changes.
  - Increase the size of the video/camera PIL carveout without affecting
    existing functionality.
  - Reduce the size of the trusted apps carveout to meet IoT-specific
    requirements.
  - Remove audio_mdf_mem, tz_ffi_mem, and their corresponding SCM references,
    as they are not required for IoT platforms.

Co-developed-by: Pratyush Brahma <quic_pbrahma@quicinc.com>
Signed-off-by: Pratyush Brahma <quic_pbrahma@quicinc.com>
Co-developed-by: Prakash Gupta <quic_guptap@quicinc.com>
Signed-off-by: Prakash Gupta <quic_guptap@quicinc.com>
Nacked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Wasim Nazir <wasim.nazir@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250803110113.401927-3-wasim.nazir@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-10 21:01:15 -05:00
Wasim Nazir
c7724332e0 arm64: dts: qcom: Rename sa8775p SoC to "lemans" 
SA8775P, QCS9100 and QCS9075 are all variants of the same die,
collectively referred to as lemans. Most notably, the last of them
has the SAIL (Safety Island) fused off, but remains identical
otherwise.

In an effort to streamline the codebase, rename the SoC DTSI, moving
away from less meaningful numerical model identifiers.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Nacked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Wasim Nazir <wasim.nazir@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250803110113.401927-2-wasim.nazir@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-10 21:01:15 -05:00
Dmitry Baryshkov
633ffe2317 arm64: dts: qcom: sm8550: stop using SoC-specific genpd indices 
The SM8550 has switched to RPMHPD_* indices for RPMh power domains,
however commit e271b59e39 ("arm64: dts: qcom: sm8550: Add camera clock
controller") brought some more old-style indices. Convert all of them to
use common RPMh PD indices.

Fixes: e271b59e39 ("arm64: dts: qcom: sm8550: Add camera clock controller")
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250718-fix-rpmhpd-abi-v2-4-0059edb9ddb3@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-10 21:01:15 -05:00