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arm64: dts: qcom: x1p42100: Add GPU support
X1P42100 SoC has a new GPU called Adreno X1-45 which is a smaller version of Adreno X1-85 GPU. Describe this new GPU and also add the secure gpu firmware path that should used for X1P42100 CRD. Tested-by: Jens Glathe <jens.glathe@oldschoolsolutions.biz> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Tested-by: Aleksandrs Vinarskis <alex.vinarskis@gmail.com> # x1-26-100 Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250623-x1p-adreno-v4-4-d2575c839cbb@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
committed by
Bjorn Andersson
parent
71ef5e99e9
commit
1aa0b4e364
@@ -8251,6 +8251,13 @@ sbsa_watchdog: watchdog@1c840000 {
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
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};
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qfprom: efuse@221c8000 {
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compatible = "qcom,x1e80100-qfprom", "qcom,qfprom";
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reg = <0 0x221c8000 0 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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pmu@24091000 {
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compatible = "qcom,x1e80100-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
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reg = <0 0x24091000 0 0x1000>;
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@@ -15,3 +15,7 @@ / {
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model = "Qualcomm Technologies, Inc. X1P42100 CRD";
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compatible = "qcom,x1p42100-crd", "qcom,x1p42100";
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};
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&gpu_zap_shader {
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firmware-name = "qcom/x1p42100/gen71500_zap.mbn";
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};
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@@ -17,6 +17,7 @@
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/delete-node/ &cpu_pd9;
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/delete-node/ &cpu_pd10;
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/delete-node/ &cpu_pd11;
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/delete-node/ &gpu_opp_table;
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/delete-node/ &pcie3_phy;
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/delete-node/ &thermal_zones;
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@@ -24,9 +25,117 @@ &gcc {
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compatible = "qcom,x1p42100-gcc", "qcom,x1e80100-gcc";
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};
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/* The GPU is physically different and will be brought up later */
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&gmu {
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compatible = "qcom,adreno-gmu-x145.0", "qcom,adreno-gmu";
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};
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&gpu {
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/delete-property/ compatible;
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compatible = "qcom,adreno-43030c00", "qcom,adreno";
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nvmem-cells = <&gpu_speed_bin>;
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nvmem-cell-names = "speed_bin";
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gpu_opp_table: opp-table {
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compatible = "operating-points-v2-adreno", "operating-points-v2";
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opp-1400000000 {
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opp-hz = /bits/ 64 <1400000000>;
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opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>;
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opp-peak-kBps = <16500000>;
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qcom,opp-acd-level = <0xa8295ffd>;
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opp-supported-hw = <0x3>;
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};
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opp-1250000000 {
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opp-hz = /bits/ 64 <1250000000>;
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opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>;
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opp-peak-kBps = <16500000>;
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qcom,opp-acd-level = <0x882a5ffd>;
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opp-supported-hw = <0x7>;
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};
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opp-1107000000 {
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opp-hz = /bits/ 64 <1107000000>;
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opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
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opp-peak-kBps = <16500000>;
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qcom,opp-acd-level = <0x882a5ffd>;
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opp-supported-hw = <0xf>;
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};
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opp-1014000000 {
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opp-hz = /bits/ 64 <1014000000>;
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opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
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opp-peak-kBps = <14398438>;
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qcom,opp-acd-level = <0xa82a5ffd>;
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opp-supported-hw = <0xf>;
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};
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opp-940000000 {
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opp-hz = /bits/ 64 <940000000>;
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opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
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opp-peak-kBps = <14398438>;
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qcom,opp-acd-level = <0xa82a5ffd>;
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opp-supported-hw = <0xf>;
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};
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opp-825000000 {
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opp-hz = /bits/ 64 <825000000>;
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opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
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opp-peak-kBps = <12449219>;
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qcom,opp-acd-level = <0x882b5ffd>;
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opp-supported-hw = <0xf>;
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};
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opp-720000000 {
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opp-hz = /bits/ 64 <720000000>;
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opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
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opp-peak-kBps = <10687500>;
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qcom,opp-acd-level = <0xa82c5ffd>;
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opp-supported-hw = <0xf>;
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};
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opp-666000000-0 {
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opp-hz = /bits/ 64 <666000000>;
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opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
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opp-peak-kBps = <8171875>;
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qcom,opp-acd-level = <0xa82d5ffd>;
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opp-supported-hw = <0xf>;
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};
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/* Only applicable for SKUs which has 666Mhz as Fmax */
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opp-666000000-1 {
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opp-hz = /bits/ 64 <666000000>;
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opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
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opp-peak-kBps = <16500000>;
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qcom,opp-acd-level = <0xa82d5ffd>;
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opp-supported-hw = <0x10>;
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};
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opp-550000000 {
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opp-hz = /bits/ 64 <550000000>;
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opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
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opp-peak-kBps = <6074219>;
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qcom,opp-acd-level = <0x882e5ffd>;
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opp-supported-hw = <0x1f>;
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};
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opp-380000000 {
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opp-hz = /bits/ 64 <380000000>;
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opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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opp-peak-kBps = <3000000>;
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qcom,opp-acd-level = <0xc82f5ffd>;
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opp-supported-hw = <0x1f>;
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};
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opp-280000000 {
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opp-hz = /bits/ 64 <280000000>;
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opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
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opp-peak-kBps = <2136719>;
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qcom,opp-acd-level = <0xc82f5ffd>;
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opp-supported-hw = <0x1f>;
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};
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};
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};
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&gpucc {
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@@ -42,6 +151,13 @@ &pcie6a_phy {
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compatible = "qcom,x1p42100-qmp-gen4x4-pcie-phy";
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};
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&qfprom {
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gpu_speed_bin: gpu-speed-bin@119 {
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reg = <0x119 0x2>;
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bits = <7 9>;
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};
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};
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&soc {
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/* The PCIe3 PHY on X1P42100 uses a different IP block */
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pcie3_phy: phy@1bd4000 {
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