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arm64: dts: qcom: x1e80100: add bus topology for PCIe domain 3

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Add pcie3_port node to represent the PCIe bridge of PCIe3 so that PCI slot
voltage rails can be described under this node in the board's dts.

Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Signed-off-by: Wenbin Yao <quic_wenbyao@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250722091151.1423332-3-quic_wenbyao@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Qiang Yu
2025-07-22 17:11:50 +08:00
committed by Bjorn Andersson
parent f93e588213
commit 6facfaff0f
1 changed files with 11 additions and 0 deletions
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11
arch/arm64/boot/dts/qcom/x1e80100.dtsi
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@@ -3306,6 +3306,17 @@ opp-128000000 {
opp-peak-kBps = <15753000 1>;
};
};
pcie3_port: pcie@0 {
device_type = "pci";
compatible = "pciclass,0604";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
};
pcie3_phy: phy@1be0000 {