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arm64: dts: qcom: x1e80100-qcp: enable pcie3 x8 slot for X1E80100-QCP

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Add perst, wake and clkreq sideband signals and required regulators in
PCIe3 controller and PHY device tree node. Describe the voltage rails of
the x8 PCI slots for PCIe3 port.

Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Signed-off-by: Wenbin Yao <quic_wenbyao@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250722091151.1423332-4-quic_wenbyao@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Qiang Yu
2025-07-22 17:11:51 +08:00
committed by Bjorn Andersson
parent 6facfaff0f
commit df758a868d
1 changed files with 118 additions and 0 deletions
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118
arch/arm64/boot/dts/qcom/x1e80100-qcp.dts
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@@ -318,6 +318,48 @@ vreg_wcn_3p3: regulator-wcn-3p3 {
regulator-boot-on;
};
vreg_pcie_12v: regulator-pcie-12v {
compatible = "regulator-fixed";
regulator-name = "VREG_PCIE_12V";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
gpio = <&pm8550ve_8_gpios 8 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-0 = <&pcie_x8_12v>;
pinctrl-names = "default";
};
vreg_pcie_3v3_aux: regulator-pcie-3v3-aux {
compatible = "regulator-fixed";
regulator-name = "VREG_PCIE_3P3_AUX";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pmc8380_3_gpios 8 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-0 = <&pm_sde7_aux_3p3_en>;
pinctrl-names = "default";
};
vreg_pcie_3v3: regulator-pcie-3v3 {
compatible = "regulator-fixed";
regulator-name = "VREG_PCIE_3P3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pmc8380_3_gpios 6 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-0 = <&pm_sde7_main_3p3_en>;
pinctrl-names = "default";
};
usb-1-ss0-sbu-mux {
compatible = "onnn,fsusb42", "gpio-sbu-mux";
@@ -908,6 +950,59 @@ &mdss_dp3_phy {
status = "okay";
};
&pm8550ve_8_gpios {
pcie_x8_12v: pcie-12v-default-state {
pins = "gpio8";
function = "normal";
output-enable;
output-high;
bias-pull-down;
power-source = <0>;
};
};
&pmc8380_3_gpios {
pm_sde7_aux_3p3_en: pcie-aux-3p3-default-state {
pins = "gpio8";
function = "normal";
output-enable;
output-high;
bias-pull-down;
power-source = <0>;
};
pm_sde7_main_3p3_en: pcie-main-3p3-default-state {
pins = "gpio6";
function = "normal";
output-enable;
output-high;
bias-pull-down;
power-source = <0>;
};
};
&pcie3 {
pinctrl-names = "default";
pinctrl-0 = <&pcie3_default>;
perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
status = "okay";
};
&pcie3_phy {
vdda-phy-supply = <&vreg_l3c_0p8>;
vdda-pll-supply = <&vreg_l3e_1p2>;
status = "okay";
};
&pcie3_port {
vpcie12v-supply = <&vreg_pcie_12v>;
vpcie3v3-supply = <&vreg_pcie_3v3>;
vpcie3v3aux-supply = <&vreg_pcie_3v3_aux>;
};
&pcie4 {
perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
@@ -1119,6 +1214,29 @@ nvme_reg_en: nvme-reg-en-state {
bias-disable;
};
pcie3_default: pcie3-default-state {
clkreq-n-pins {
pins = "gpio144";
function = "pcie3_clk";
drive-strength = <2>;
bias-pull-up;
};
perst-n-pins {
pins = "gpio143";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
wake-n-pins {
pins = "gpio145";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
pcie4_default: pcie4-default-state {
clkreq-n-pins {
pins = "gpio147";