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Krishna Kurapati
d72cb0551d arm64: dts: qcom: sc7280: Flatten usb controller nodes 
Flatten usb controller nodes and update to using latest bindings
and flattened driver approach.

Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Tested-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> # FP5
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250728035812.2762957-1-krishna.kurapati@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 21:32:06 -05:00
Konrad Dybcio
642af3f3d5 arm64: dts: qcom: sc7280-chrome-common: Remove duplicate node 
sc7280.dtsi already includes the very same definition (bar 'memory@'
vs 'video@', which doesn't matter). Remove the duplicate to fix a lot
of dtbs W=1 warning instances (unique_unit_address_if_enabled).

Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Acked-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20250728-topic-chrome_dt_fixup-v1-1-1fc38a95d5ea@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 21:31:58 -05:00
Loic Poulain
1d363a6cf8 arm64: dts: qcom: qcm2290: Enable HS eMMC timing modes 
The host controller supports HS200/HS400 and HS400 enhanced strobe mode.
On RB1, this improves Linux eMMC read speed, from ~170MB/s to 300MB/s.

Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250728093426.1413379-1-loic.poulain@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 21:31:51 -05:00
Ling Xu
d15cb624a6 arm64: dts: qcom: sm6150: Add ADSP and CDSP fastrpc nodes 
Add ADSP and CDSP fastrpc nodes for SM6150 platform.

Signed-off-by: Ling Xu <quic_lxu5@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250729031259.4190916-1-quic_lxu5@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 21:29:34 -05:00
Neil Armstrong
c2e07613b8 arm64: dts: qcom: sm8650: Add ACD levels for GPU 
Update GPU node to include acd level values.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250729-topic-sm8650-upstream-gpu-acd-level-v1-1-258090038a41@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 21:27:19 -05:00
Sumit Garg
dc231840dc arm64: dts: qcom: qcm2290: Add TCSR download mode address 
Allow configuration of download mode via qcom_scm driver via specifying
download mode register address in the TCSR space. It is especially useful
for a clean watchdog reset without entry into download mode.

The problem remained un-noticed until now since error reporting for
missing download mode configuration feature was explicitly suppressed.

Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250730132230.247727-1-sumit.garg@kernel.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 21:26:44 -05:00
David Heidelberg
f72f3aac4a arm64: dts: qcom: sdm845-oneplus: Deduplicate shared entries 
Use the definition for qcom,msm-id and put them into the common dtsi.

Signed-off-by: David Heidelberg <david@ixit.cz>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250801-sdm845-msmid-v2-2-9f44d125ee44@ixit.cz
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 21:26:33 -05:00
David Heidelberg
285fee8c65 arm64: dts: qcom: sdm845*: Use definition for msm-id 
For all boards it's QCOM_ID_SDM845 except Dragonboard, where it's
QCOM_ID_SDA845.

Except for OnePlus 6 / 6T, which is handled in following commit.

Signed-off-by: David Heidelberg <david@ixit.cz>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250801-sdm845-msmid-v2-1-9f44d125ee44@ixit.cz
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 21:26:33 -05:00
Richard Acayan
8839b8e6e8 arm64: dts: qcom: sdm670-google-sargo: enable charger 
The Pixel 3a has a rechargeable 3000 mAh battery. Describe it and enable
its charging controller in PM660.

Signed-off-by: Richard Acayan <mailingradian@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250630224158.249726-2-mailingradian@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 21:23:06 -05:00
Aleksandrs Vinarskis
93109afda0 arm64: dts: qcom: x1e78100-lenovo-thinkpad-t14s: Enable HBR3 on external DPs 
When no link frequencies are set, msm/dp driver defaults to HBR2 speed.
Explicitly list supported frequencies including HBR3/8.1Gbps for all
external DisplayPort(s).

Signed-off-by: Aleksandrs Vinarskis <alex.vinarskis@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250630205514.14022-3-alex.vinarskis@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 21:22:51 -05:00
Aleksandrs Vinarskis
60fdba1dcc arm64: dts: qcom: x1-crd: Enable HBR3 on external DPs 
When no link frequencies are set, msm/dp driver defaults to HBR2 speed.
Explicitly list supported frequencies including HBR3/8.1Gbps for all
external DisplayPort(s).

Signed-off-by: Aleksandrs Vinarskis <alex.vinarskis@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250630205514.14022-2-alex.vinarskis@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 21:22:51 -05:00
Laurent Pinchart
5433560caa arm64: dts: qcom: sdm845-db845c-navigation-mezzanine: Replace clock-frequency in camera sensor node 
The clock-frequency for camera sensors has been deprecated in favour of
the assigned-clocks and assigned-clock-rates properties. Replace it in
the device tree.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250710174808.5361-13-laurent.pinchart@ideasonboard.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 17:19:50 -05:00
Stephan Gerhold
ad9abc9ba4 arm64: dts: qcom: x1e80100-crd: Add USB multiport fingerprint reader 
The X1E80100 CRD has a Goodix fingerprint reader connected to the USB
multiport controller on eUSB6. All other ports (including USB super-speed
pins) are unused.

Set it up in the device tree together with the NXP PTN3222 repeater.

Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Tested-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250714-x1e80100-crd-fp-v2-1-3246eb02b679@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 17:15:08 -05:00
Krishna Kurapati
c5a87e3a6b arm64: dts: qcom: sm8450: Flatten usb controller node 
Flatten usb controller node and update to using latest bindings
and flattened driver approach.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250715052739.3831549-3-krishna.kurapati@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 17:11:31 -05:00
Krishna Kurapati
f578e5f0b8 arm64: dts: qcom: sm8450-qrd: add pmic glink node 
Add the pmic glink node linked with the DWC3 USB controller
switched to OTG mode and tagged with usb-role-switch.

Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250715052739.3831549-2-krishna.kurapati@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 17:11:30 -05:00
Sayali Lokhande
d81448d49c arm64: dts: qcom: qcs8300-ride: Enable SDHC1 node 
Enable sdhc1 support for qcs8300 ride platform.

Signed-off-by: Sayali Lokhande <quic_sayalil@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250716085125.27169-3-quic_sayalil@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 17:07:18 -05:00
Sayali Lokhande
43b8556e82 arm64: dts: qcom: qcs8300: Add eMMC support 
Add eMMC support for qcs8300 board.

Signed-off-by: Sayali Lokhande <quic_sayalil@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250716085125.27169-2-quic_sayalil@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 17:06:56 -05:00
Konrad Dybcio
bae72efa3c dt-bindings: arm: qcom: Remove sdm845-cheza 
Cheza was a prototype board, used mainly by the ChromeOS folks.

Almost no working devices are known to exist, and the small amount of
remaining ones are not in use anymore.

Remove the compatible strings reserved for it, as, quite frankly, Cheza
is no more.

Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20250716-topic-goodnight_cheza-v2-2-6fa8d3261813@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 17:06:28 -05:00
Konrad Dybcio
5e4ca587f5 arm64: dts: qcom: Remove sdm845-cheza boards 
Cheza was a prototype board, used mainly by the ChromeOS folks, whose
former efforts on making linux-arm-msm better we greatly appreciate.

There are close to zero known-working devices at this point in time
(see the link below) and it was never productized.

Remove it to ease maintenance burden.

Link: https://lore.kernel.org/linux-arm-msm/5567e441-055d-443a-b117-ec16b53dc059@oss.qualcomm.com/
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20250716-topic-goodnight_cheza-v2-1-6fa8d3261813@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 17:06:28 -05:00
Shivnandan Kumar
bc6776fab8 arm64: dts: qcom: sm8750: Add BWMONs 
Add the CPU BWMONs for SM8750 SoCs.

Notably, the one related to cluster0 requires that it's mapped with
the nE memory attribute. This is specific to a single instance, on this
platform only and should not be mimicked elsewhere.

Signed-off-by: Shivnandan Kumar <quic_kshivnan@quicinc.com>
[konrad: add nonposted-mmio where necessary, re-sort nodes]
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250716-8750_cpubwmon-v4-2-12212098e90f@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 16:50:19 -05:00
Arseniy Velikanov
e2ec684f82 arm64: dts: sm8250-xiaomi-pipa: Update battery info 
Added max design microvolt. Merged battery info into one node,
since pmic fuel-gauge uses mixed info about dual-cell battery.

Reviewed-by: Luka Panio <lukapanio@gmail.com>
Signed-off-by: Arseniy Velikanov <me@adomerle.pw>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250716141041.24507-3-me@adomerle.pw
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 16:49:29 -05:00
Arseniy Velikanov
56197c8737 arm64: dts: qcom: sm8250-xiaomi-pipa: Drop unused bq27z561 
It looks like the fuel gauge is not connected to the battery,
it reports nonsense info. Downstream kernel uses pmic fg.

Reviewed-by: Luka Panio <lukapanio@gmail.com>
Signed-off-by: Arseniy Velikanov <me@adomerle.pw>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250716141041.24507-2-me@adomerle.pw
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 16:49:29 -05:00
Arseniy Velikanov
92d05acead arm64: dts: qcom: sm8250-xiaomi-pipa: Drop nonexistent pm8009 pmic 
PM8009 was erroneously added since this device doesn't actually have it.
It triggers a big critical error at boot, so we're drop it.

Fixes: 264beb3cbd ("arm64: dts: qcom: sm8250-xiaomi-pipa: Add initial device tree")
Reviewed-by: Luka Panio <lukapanio@gmail.com>
Signed-off-by: Arseniy Velikanov <me@adomerle.pw>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250716141041.24507-1-me@adomerle.pw
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 16:49:29 -05:00
Krzysztof Kozlowski
474aa14da0 dt-bindings: arm: qcom-soc: Document new Milos and Glymur SoCs 
Extend the schema enforcing correct SoC-block naming to cover Milos
(compatibles already accepted by some maintainers for next release) and
Glymur (posted on mailing lists [1]) SoCs.

Link: https://lore.kernel.org/linux-devicetree/20250716152017.4070029-1-pankaj.patil@oss.qualcomm.com/ [1]
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250716162412.27471-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 16:48:47 -05:00
Ziyue Zhang
fba47ba8c8 arm64: dts: qcom: qcs615: Set LDO12A regulator to HPM to avoid boot hang 
On certain platforms (e.g., QCS615), consumers of LDO12A—such as PCIe,
UFS, and eMMC—may draw more than 10mA of current during boot. This can
exceed the regulator's limit in Low Power Mode (LPM), triggering current
limit protection and causing the system to hang.

To address this, there are two possible approaches:
a) Set the regulator's initial mode to High Performance Mode (HPM) in
   the device tree.
b) Keep the default LPM setting and have each consumer driver explicitly
   set its current load.

Since some regulators are shared among multiple consumers, and setting
the current must be coordinated across all of them, we will initially
adopt option a by setting the regulator to HPM. We can later migrate to
option b when the timing is appropriate and all consumer drivers are
ready.

Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>
Signed-off-by: Tingguo Cheng <quic_tingguoc@quicinc.com>
Link: https://lore.kernel.org/r/20250717072746.987298-1-quic_ziyuzhan@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 16:47:35 -05:00
Krishna Chaitanya Chundru
84f3849d05 arm64: dts: qcom: qcs6490-rb3gen2: Add missing clkreq pinctrl property 
Add the missing clkreq pinctrl entry to the PCIe1 node. This ensures proper
configuration of the CLKREQ# signal, which is needed for proper functioning
of PCIe ASPM.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250717-clkreq-v1-1-5a82c7e8e891@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 16:47:12 -05:00
George Moussalem
5ca3d42384 arm64: dts: qcom: Update IPQ5018 xo_board_clk to use fixed factor clock 
The xo_board_clk is fixed to 24 MHZ, which is routed from WiFi output
clock 96 MHZ (also being the reference clock of CMN PLL) divided by 4
to the analog block routing channel. Update the xo_board_clk nodes in
the board DTS files to use clock-div/clock-mult accordingly.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Link: https://lore.kernel.org/r/20250721-ipq5018-cmn-pll-v5-2-4cbf3479af65@outlook.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 16:44:56 -05:00
George Moussalem
c006b249c5 arm64: dts: ipq5018: Add CMN PLL node 
Add CMN PLL node for enabling output clocks to the networking
hardware blocks on IPQ5018 devices.

The reference clock of CMN PLL is routed from XO to the CMN PLL
through the internal WiFi block.
.XO (48 MHZ) --> WiFi (multiplier/divider)--> 96 MHZ to CMN PLL.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Link: https://lore.kernel.org/r/20250721-ipq5018-cmn-pll-v5-1-4cbf3479af65@outlook.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 16:44:56 -05:00
George Moussalem
ed5789ba7c arm64: dts: qcom: ipq5018: Add crypto nodes 
IPQ5018 uses Qualcomm QCE crypto engine v5.1 which is already supported.
So let's add the dts nodes for its DMA v1.7.4 and QCE itself.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250721-ipq5018-crypto-v3-1-b9cd9b0ef147@outlook.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 16:44:43 -05:00
George Moussalem
bf258fdaa2 arm64: dts: qcom: ipq5018: add PRNG node 
PRNG inside of IPQ5018 is already supported, so let's add the node for it.

Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250721-ipq5018-prng-v1-1-474310e0575d@outlook.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 16:44:37 -05:00
Raviteja Laggyshetty
bebacd802b arm64: dts: qcom: qcs8300: Add EPSS l3 interconnect provider node and CPUCP OPP tables to scale DDR/L3 
Add Epoch Subsystem (EPSS) L3 interconnect provider node and OPP tables
required to scale DDR and L3 per freq-domain on QCS8300 platform.
As QCS8300 and SA8775P SoCs have same EPSS hardware, added SA8775P
compatible as fallback for QCS8300 EPSS device node.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Co-developed-by: Imran Shaik <quic_imrashai@quicinc.com>
Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250722055039.135140-2-raviteja.laggyshetty@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 16:43:43 -05:00
Qiang Yu
df758a868d arm64: dts: qcom: x1e80100-qcp: enable pcie3 x8 slot for X1E80100-QCP 
Add perst, wake and clkreq sideband signals and required regulators in
PCIe3 controller and PHY device tree node. Describe the voltage rails of
the x8 PCI slots for PCIe3 port.

Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Signed-off-by: Wenbin Yao <quic_wenbyao@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250722091151.1423332-4-quic_wenbyao@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 16:43:07 -05:00
Qiang Yu
6facfaff0f arm64: dts: qcom: x1e80100: add bus topology for PCIe domain 3 
Add pcie3_port node to represent the PCIe bridge of PCIe3 so that PCI slot
voltage rails can be described under this node in the board's dts.

Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Signed-off-by: Wenbin Yao <quic_wenbyao@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250722091151.1423332-3-quic_wenbyao@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 16:43:07 -05:00
Krzysztof Kozlowski
f93e588213 dt-bindings: arm: qcom: Drop redundant free-form SoC list 
The schema and Devicetree specification defines how list of top-level
compatibles should be created, thus first paragraph explaining this is
completely redundant.

The list of SoCs is redundant as well, because the schema lists them.
On the other hand, Linux kernel should not be place to store marketing
names of some company products, so such list is irrelevant here.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250724132436.77160-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 16:17:12 -05:00
Krzysztof Kozlowski
8def31f8c1 arm64: dts: qcom: sm8650: Sort nodes by unit address 
Qualcomm DTS uses sorting of MMIO nodes by the unit address, so move
few nodes in SM8650 DTSI to fix that.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250727193652.4029-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 13:22:44 -05:00
Val Packett
1a67f85c69 dt-bindings: arm: qcom: Add Dell Latitude 7455 
Document the X1E80100-based Dell Latitude 7455 laptop.

Signed-off-by: Val Packett <val@packett.cool>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250525095341.12462-3-val@packett.cool
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 13:22:44 -05:00
George Moussalem
8d2a8e8dc4 arm64: dts: qcom: ipq5018: Add SPI nand support 
Add QPIC SPI NAND support for IPQ5018 SoC.

Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250501-ipq5018-spi-qpic-snand-v1-2-31e01fbb606f@outlook.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 13:22:44 -05:00
Bartosz Golaszewski
25197809e7 arm64: dts: qcom: sdm845-samsung-starqltechn: fix GPIO lookup flags for i2c SDA and SCL 
The I2C GPIO bus driver enforces the SDA and SCL pins as open-drain
outputs but the lookup flags in the DTS don't reflect that triggering
warnings from GPIO core. Add the appropriate flags.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Link: https://lore.kernel.org/r/20250811-qcom-gpio-lookup-open-drain-v1-3-b5496f80e047@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 13:22:44 -05:00
Bartosz Golaszewski
f07f492773 arm64: dts: qcom: qrb4210-rb2: fix GPIO lookup flags for i2c SDA and SCL 
The I2C GPIO bus driver enforces the SDA and SCL pins as open-drain
outputs but the lookup flags in the DTS don't reflect that triggering
warnings from GPIO core. Add the appropriate flags.

Reported-by: Alexey Klimov <alexey.klimov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Link: https://lore.kernel.org/r/20250811-qcom-gpio-lookup-open-drain-v1-2-b5496f80e047@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 13:22:44 -05:00
Bartosz Golaszewski
b2659ddbc2 arm64: dts: qcom: qrb2210-rb1: fix GPIO lookup flags for i2c SDA and SCL 
The I2C GPIO bus driver enforces the SDA and SCL pins as open-drain
outputs but the lookup flags in the DTS don't reflect that triggering
warnings from GPIO core. Add the appropriate flags.

Tested-by: Alexey Klimov <alexey.klimov@linaro.org>
Reported-by: Alexey Klimov <alexey.klimov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Link: https://lore.kernel.org/r/20250811-qcom-gpio-lookup-open-drain-v1-1-b5496f80e047@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 13:22:44 -05:00
Luca Weiss
35e0b432d5 arm64: dts: qcom: pmk8550: Correct gpio node name 
The reg for the GPIOs is 0xb800 and not 0x8800, so fix this copy-paste
mistake.

Fixes: e9c0a4e484 ("arm64: dts: qcom: Add PMK8550 pmic dtsi")
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250625-pmk8550-gpio-name-v1-1-58402849f365@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 13:22:44 -05:00
Yu Zhang(Yuriy)
b5634bf979 arm64: dts: qcom: qcs615-ride: Enable WiFi/BT nodes 
Enable WiFi/BT on qcs615-ride by adding a node for the PMU module of the
WCN6855 and assigning its LDO power outputs to the existing WiFi/BT
module.

Signed-off-by: Yu Zhang (Yuriy) <yu.zhang@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250727-615-v7-2-2adb6233bbb9@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 13:22:44 -05:00
Yu Zhang(Yuriy)
e13555a3e1 arm64: dts: qcom: qcs615: add a PCIe port for WLAN 
Add an original PCIe port for WLAN. This port will be referenced and
supplemented by specific WLAN devices.

Signed-off-by: Yu Zhang (Yuriy) <yu.zhang@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250727-615-v7-1-2adb6233bbb9@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 13:22:44 -05:00
Krishna chaitanya chundru
414be2b5a7 arm64: dts: qcom: qcs615-ride: Enable PCIe interface 
Add platform configurations in devicetree for PCIe, board related
gpios, PMIC regulators, etc.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250725112346.614316-3-ziyue.zhang@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 13:22:44 -05:00
Krishna chaitanya chundru
718cc7542a arm64: dts: qcom: qcs615: enable pcie 
Add configurations in devicetree for PCIe0, including registers, clocks,
interrupts and phy setting sequence.

Add PCIe lane equalization preset properties for 8 GT/s.

Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250725112346.614316-2-ziyue.zhang@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 13:22:44 -05:00
George Moussalem
f5f2b835e3 arm64: dts: qcom: ipq5018: Add GE PHY to internal mdio bus 
The IPQ5018 SoC contains an internal GE PHY, always at phy address 7.
As such, let's add the GE PHY node to the SoC dtsi.

The LDO controller found in the SoC must be enabled to provide constant
low voltages to the PHY. The mdio-ipq4019 driver already has support
for this, so adding the appropriate TCSR register offset.

In addition, the GE PHY outputs both the RX and TX clocks to the GCC
which gate controls them and routes them back to the PHY itself.
So let's create two DT fixed clocks and register them in the GCC node.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Link: https://lore.kernel.org/r/20250630-ipq5018-ge-phy-v6-3-01be06378c15@outlook.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 13:22:44 -05:00
George Moussalem
1e2261a669 arm64: dts: qcom: ipq5018: Add MDIO buses 
IPQ5018 contains two mdio buses of which one bus is used to control the
SoC's internal GE PHY, while the other bus is connected to external PHYs
or switches.

There's already support for IPQ5018 in the mdio-ipq4019 driver, so let's
simply add the mdio nodes for them.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Link: https://lore.kernel.org/r/20250630-ipq5018-ge-phy-v6-2-01be06378c15@outlook.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 13:22:43 -05:00
Luo Jie
e5612530e3 arm64: dts: qcom: Update IPQ5424 xo_board to use fixed factor clock 
xo_board is fixed to 24 MHZ, which is routed from WiFi output clock
48 MHZ (also being the reference clock of CMN PLL) divided 2 by
analog block routing channel.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
Link: https://lore.kernel.org/r/20250610-qcom_ipq5424_cmnpll-v3-4-ceada8165645@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 13:22:43 -05:00
Luo Jie
682c9d0e78 arm64: dts: qcom: ipq5424: Add CMN PLL node 
Add CMN PLL node for enabling output clocks to the networking
hardware blocks on IPQ5424 devices.

The reference clock of CMN PLL is routed from XO to the CMN PLL
through the internal WiFi block.
.XO (48 MHZ or 96 MHZ or 192 MHZ)-->WiFi (multiplier/divider)-->
48 MHZ to CMN PLL.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
Link: https://lore.kernel.org/r/20250610-qcom_ipq5424_cmnpll-v3-3-ceada8165645@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 13:22:43 -05:00
Luca Weiss
5ce2aa520d arm64: dts: qcom: sm7225-fairphone-fp4: Enable USB audio offload support 
Enable USB audio offloading which allows to play audio via a USB-C
headset with lower power consumption and enabling some other features.

This can be used like the following:

  $ amixer -c0 cset name='USB_RX Audio Mixer MultiMedia1' On
  $ aplay --device=plughw:0,0 test.wav

Compared to regular playback to the USB sound card no xhci-hcd
interrupts appear during playback, instead the ADSP will be handling the
USB transfers.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250501-fp4-usb-audio-offload-v2-5-30f4596281cd@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 13:22:43 -05:00