mirrors/linux
1
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git synced 2026-05-03 11:12:01 -04:00
Code Issues Packages Projects Releases Wiki Activity
1,268,048 Commits 1 Branch 928 Tags
514ca6dffb2b76c1593b558527e2c84bd7faa249
Commit Graph

1268048 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Ville Syrjälä
514ca6dffb drm/i915: Extract i9xx_plane_regs.h 
Relocate all pre-skl primary plane register definitions
into their own declutter i915_reg.h.

Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: Zhi Wang <zhi.wang.linux@gmail.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240516135622.3498-10-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
 2024-05-22 15:54:53 +03:00
Ville Syrjälä
561608610b drm/i915: Move PIPEGCMAX to intel_color_regs.h 
PIPEGCMAX was left behind when all other gamma registers moved
into intel_color_regs.h.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240516135622.3498-9-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
 2024-05-22 15:50:42 +03:00
Ville Syrjälä
9871927034 drm/i915: Add separate defines for cursor WM/DDB register bits 
Make a more thorough split between universal planes vs. cursors
by defining the contents of the cursor WM/DDB registers separately.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240516135622.3498-8-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
 2024-05-22 15:49:51 +03:00
Ville Syrjälä
0ff7639bb1 drm/i915: Rename selective fetch plane registers 
Rename the selective fetch plane registers to match the spec.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240516135622.3498-6-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
 2024-05-22 15:45:34 +03:00
Ville Syrjälä
04c09e4b87 drm/i915: Simplify PIPESRC_ERLY_TPT definition 
PIPESRC_ERLY_TPT is a pipe register, and it lives in the 0x70000 range.
so using _MMIO_TRANS2() for it is not really correct. Also since this
is a pipe register, and not present on CHV, the registers will be
equally spaced out, so we can use the simpler _MMIO_PIPE() instead
of _MMIO_PIPE2().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240516135622.3498-5-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
 2024-05-22 15:45:34 +03:00
Ville Syrjälä
199bc8c175 drm/i915: Add separate define for SEL_FETCH_CUR_CTL() 
Split the cursor stuff from the rest of the selective fetch
plane registers so that we can collect all cursor registers
in intel_cursor_regs.h. Also take the opportunity to rename
the registers to match the spec.

v2: Pass the correct register offset fpr pipe B (Jani)
    s/mtl+/tgl+/ as that's where this was introduced
    Drop the bogus SEL_FETCH_CUR_CTL_ENABLE bit, the contents
    actually match the normal CUR_CTL register

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240520171459.9661-1-ville.syrjala@linux.intel.com
 2024-05-22 15:45:34 +03:00
Ville Syrjälä
9cad70a940 drm/i915: Clean up the cursor register defines 
Group the cursor register defines such that everything to
do with one register is in one place.

Also, while we are touching these protect all the macro
arguments for good measure.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240516135622.3498-3-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
 2024-05-22 15:34:57 +03:00
Ville Syrjälä
df798d43b3 drm/i915: Add skl+ plane name aliases to enum plane_id 
Using PLANE_PRIMARY + PLANE_SPRITE? on skl+ results in a bunch
of unnecessary head scratching. Add aliases using the skl+ plane
names.
And for pre-skl we only need to keep PRIMARY,SPRITE0,SPRITE1
as we only ever have 0-2 sprites per pipe on those platforms.

v2: Don't break icl_nv12_y_plane_mask() (Jani)

Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240517171208.21313-1-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
 2024-05-22 15:31:59 +03:00
Vidya Srinivas
51064d471c drm/i915/dpt: Make DPT object unshrinkable 
In some scenarios, the DPT object gets shrunk but
the actual framebuffer did not and thus its still
there on the DPT's vm->bound_list. Then it tries to
rewrite the PTEs via a stale CPU mapping. This causes panic.

Cc: stable@vger.kernel.org
Reported-by: Shawn Lee <shawn.c.lee@intel.com>
Fixes: 0dc987b699 ("drm/i915/display: Add smem fallback allocation for dpt")
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
[vsyrjala: Add TODO comment]
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240520165634.1162470-1-vidya.srinivas@intel.com
 2024-05-22 15:31:08 +03:00
Ville Syrjälä
2689390b4e drm/i915: Bump max TMDS bitrate to 6 Gbps on ADL-S/ADL-P/DG2+ 
Bspec lists the mas TMDS bitrate as 6 Gbps on ADL-S/ADL-P/DG2.
Bump our limit to match.

v2: Bump for ADL-S as well (Jani)

Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240520164732.3682-1-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
 2024-05-22 15:26:15 +03:00
Gustavo Sousa
bb3c3e79d9 drm/i915/bmg: Load DMC 
Load Battlemage's DMC. We re-use XELPDP_DMC_MAX_FW_SIZE since BMG's
display is a derivative of Xe_LPD+ and has the same MMIO offset limits.

Reviewed-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240510140532.112352-2-gustavo.sousa@intel.com
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
 2024-05-22 09:11:51 -03:00
Suraj Kandpal
76e220d4d8 drm/i915/hdcp: Check mst_port to determine connector type 
Check mst_port field in intel_connector to check connector type
rather than rely on encoder as it may not be attached to connector
at times.

--v2
-Add closes tag [Imre]

Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10898
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240521081458.1500327-3-suraj.kandpal@intel.com
 2024-05-22 15:33:48 +05:30
Suraj Kandpal
1155de965e drm/i915/hdcp: Move aux assignment after connector type check 
Move assignment of aux after connector type check as port may not
exist if connector is not DPMST.

--v2
-Fix unwanted change in intel_encoder check [Jani]

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240521081458.1500327-2-suraj.kandpal@intel.com
 2024-05-22 15:33:46 +05:30
Jani Nikula
3c7bbd4c9d drm/i915: stop redefining INTEL_VGA_DEVICE 
Now that the PCI ID macros allow us to pass in the macro to use, stop
redefining INTEL_VGA_DEVICE.

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240515165651.1230465-2-jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
 2024-05-22 12:12:09 +03:00
Jani Nikula
cfa7772880 drm/i915/pciids: switch to xe driver style PCI ID macros 
The PCI ID macros in xe_pciids.h allow passing in the macro to operate
on each PCI ID, making it more flexible. Convert i915_pciids.h to the
same pattern.

INTEL_IVB_Q_IDS() for Quanta transcode remains a special case, and
unconditionally uses INTEL_QUANTA_VGA_DEVICE().

Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: linux-pci@vger.kernel.org
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240515165651.1230465-1-jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
 2024-05-22 12:12:09 +03:00
Ryszard Knop
a568ff8cd0 MAINTAINERS: Move the drm-intel repo location to fd.o GitLab 
The drm-intel repo is moving from the classic fd.o git host to GitLab.
Update its location with a URL matching other fd.o GitLab kernel trees.

Signed-off-by: Ryszard Knop <ryszard.knop@intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
Acked-by: Tvrtko Ursulin <tursulin@ursulin.net>
Acked-by: Lucas De Marchi <lucas.demarchi@intel.com>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240424114159.38719-1-ryszard.knop@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
 2024-05-21 07:31:33 -07:00
Jouni Högander
d370a9dba5 drm/i915/psr: PSR2_CTL[Block Count Number] not needed for LunarLake 
PSR2_CTL[Block Count Number] is not used by LunarLake do not configure it.

Bspec: 69885

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240517073005.2414293-4-jouni.hogander@intel.com
 2024-05-20 07:34:46 +03:00
Jouni Högander
30dee753ca drm/i915/psr: LunarLake PSR2_CTL[IO Wake Lines] is 6 bits wide 
On LunarLake  PSR2_CTL[IO Wake Lines] contains now bit 13:18. Take this
into account when enabling PSR2_CTL.

Bspec: 69885

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240517073005.2414293-3-jouni.hogander@intel.com
 2024-05-20 07:34:45 +03:00
Jouni Högander
45430e7b7c drm/i915/psr: LunarLake IO and Fast Wake time line count maximums are 68 
On LunarLake maximum for IO and Fast Wake time line counts are 68: 6 bits +
5 lines added by the HW. Take this into account in calculation and when
writing the IO Wake lines.

v2: maximum line count is 68 (6 bits + 5 lines added by HW)

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240517073005.2414293-2-jouni.hogander@intel.com
 2024-05-20 07:34:45 +03:00
Nirmoy Das
007ed70831 drm/i915/selftests: Set always_coherent to false when reading from CPU 
Commit 8d4ba9fc1c ("drm/i915/selftests: Pick correct caching mode.")
was not complete  as for non LLC  sharing platforms cpu read can happen
from LLC which probably doesn't have the latest changes made by GPU.

Cc: Andi Shyti <andi.shyti@linux.intel.com>
Cc: Janusz Krzysztofik <janusz.krzysztofik@linux.intel.com>
Cc: Jonathan Cavitt <jonathan.cavitt@intel.com>
Fixes: 8d4ba9fc1c ("drm/i915/selftests: Pick correct caching mode.")
Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240516151403.2875-1-nirmoy.das@intel.com
Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
 2024-05-17 14:37:02 +02:00
Jani Nikula
11abdbc22b drm/i915: pass dev_priv explicitly to CURSURFLIVE 
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the CURSURFLIVE register macro.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/86aa98ad9f883681f5c2e3aba839d02d8591bfbf.1715774156.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
 2024-05-16 11:23:00 +03:00
Jani Nikula
79a0bcadb4 drm/i915: pass dev_priv explicitly to CUR_CHICKEN 
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the CUR_CHICKEN register macro.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/0bd1fa8ab346ba2bb40f435136b975b472ad2bc8.1715774156.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
 2024-05-16 11:23:00 +03:00
Jani Nikula
3de9076e9f drm/i915: pass dev_priv explicitly to CUR_FBC_CTL 
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the CUR_FBC_CTL register macro.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/f5e76f916ccf02aaf6016ffd476e9544817ac179.1715774156.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
 2024-05-16 11:23:00 +03:00
Jani Nikula
2f757b4c40 drm/i915: pass dev_priv explicitly to CURSIZE 
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the CURSIZE register macro.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/521ca44416eb95dcfcf4bfbc32ac7f9371aeaf5d.1715774156.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
 2024-05-16 11:23:00 +03:00
Jani Nikula
224689e14a drm/i915: pass dev_priv explicitly to CURPOS_ERLY_TPT 
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the CURPOS_ERLY_TPT register macro.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/2263b6412e983026990f7f6730b0b1141be4fd0f.1715774156.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
 2024-05-16 11:23:00 +03:00
Jani Nikula
99ab1a29da drm/i915: pass dev_priv explicitly to CURPOS 
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the CURPOS register macro.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/ca229a123cb8a5d6a2970649a47236b3da1b02ad.1715774156.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
 2024-05-16 11:23:00 +03:00
Jani Nikula
0edd2d251b drm/i915: pass dev_priv explicitly to CURBASE 
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the CURBASE register macro.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/e552df69a4e6a3dbd562ba8c442d0219cda3bfd0.1715774156.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
 2024-05-16 11:23:00 +03:00
Jani Nikula
93160b2d17 drm/i915: pass dev_priv explicitly to CURCNTR 
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the CURCNTR register macro.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/06bc681558c86f351ae596e9600133bb10ae4bdd.1715774156.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
 2024-05-16 11:23:00 +03:00
Jani Nikula
d2c4b1db1c drm/i915/pciids: don't include RPL-U PCI IDs in RPL-P 
It's confusing for INTEL_RPLP_IDS() to include INTEL_RPLU_IDS(). Even if
we treat them the same elsewhere, the lists of PCI IDs should not.

Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: linux-pci@vger.kernel.org
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://patchwork.freedesktop.org/patch/msgid/28fe0910efb93a28c400728af14beff015667f42.1715340032.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
 2024-05-15 19:04:08 +03:00
Jani Nikula
7858cc0b55 drm/i915/pciids: remove 12 from INTEL_TGL_IDS() 
Most other PCI ID macros do not encode the gen in the name. Follow suit
for TGL.

Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: linux-pci@vger.kernel.org
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://patchwork.freedesktop.org/patch/msgid/044a5c553dc4564431bbef197d5e2dd085624fc2.1715340032.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
 2024-05-15 19:04:07 +03:00
Jani Nikula
bfbda47227 drm/i915/pciids: remove 11 from INTEL_ICL_IDS() 
Most other PCI ID macros do not encode the gen in the name. Follow suit
for ICL.

Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: linux-pci@vger.kernel.org
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://patchwork.freedesktop.org/patch/msgid/36973674bf333dfdd7cd32ae656754bfa150022b.1715340032.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
 2024-05-15 19:04:07 +03:00
Jani Nikula
aa3d586e16 drm/i915/pciids: don't include WHL/CML PCI IDs in CFL 
It's confusing for INTEL_CFL_IDS() to include all WHL and CML PCI
IDs. Even if we treat them the same in a lot of places, CML is a
platform of its own, and the lists of PCI IDs should not conflate them.

Largely go by the idea that if a platform has a name, group its PCI IDs
together.

That said, AML is special, having both KBL and CFL variants. Leave that
alone.

v2: Also split out WHL not just CML (Rodrigo)

Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: linux-pci@vger.kernel.org
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://patchwork.freedesktop.org/patch/msgid/7cca91dc78ed2b5982f14e400f03a1704645e475.1715340032.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
 2024-05-15 19:04:07 +03:00
Jani Nikula
5c8c22adc8 drm/i915/pciids: add INTEL_IVB_IDS() 
Add INTEL_IVB_IDS() to identify all IVBs except IVB Q transcode.

Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: linux-pci@vger.kernel.org
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://patchwork.freedesktop.org/patch/msgid/ed89a25b2c6bce318fe59e883d18b62d9453196b.1715340032.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
 2024-05-15 19:04:07 +03:00
Jani Nikula
7b43a37348 drm/i915/pciids: add INTEL_SNB_IDS() 
Add INTEL_SNB_IDS() to identify all SNBs.

Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: linux-pci@vger.kernel.org
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://patchwork.freedesktop.org/patch/msgid/ffcb2d954ad9bca78ccd39836dc0a3dc7c6c0253.1715340032.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
 2024-05-15 19:04:07 +03:00
Jani Nikula
41c0f8a36f drm/i915/pciids: add INTEL_ILK_IDS(), use acronym 
Most other PCI ID macros use platform acronyms. Follow suit for ILK. Add
INTEL_ILK_IDS() to identify all ILKs.

Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: linux-pci@vger.kernel.org
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://patchwork.freedesktop.org/patch/msgid/27ada56363cfa6a5b093cb31908a4b89aa912621.1715340032.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
 2024-05-15 19:04:07 +03:00
Jani Nikula
432ed92bfb drm/i915/pciids: add INTEL_PNV_IDS(), use acronym 
Most other PCI ID macros use platform acronyms. Follow suit for PNV. Add
INTEL_PNV_IDS() to identify all PNVs.

Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: linux-pci@vger.kernel.org
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://patchwork.freedesktop.org/patch/msgid/5f9b34a2cd388244be03263a5147776bfe64d5ac.1715340032.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
 2024-05-15 19:04:07 +03:00
Ville Syrjälä
19be15dcc0 drm/i915: Handle SKL+ WM/DDB registers next to all other plane registers 
Having the plane WM/DDB regitster write functions in skl_watermarks.c
is rather annoying when trying to implement DSB based plane updates.
Move them into the respective files that handle all other plane
register writes. Less places where I need to worry about the DSB
vs. MMIO decisions.

The downside is that we spread the wm struct details a bit further
afield. But if that becomes too annoying we can probably abstract
things a bit more with a few extra functions.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240510152329.24098-17-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
 2024-05-15 14:11:24 +03:00
Ville Syrjälä
09fc93141d drm/i915: Nuke skl_write_wm_level() and skl_ddb_entry_write() 
Get rid of skl_ddb_entry_write() and skl_write_wm_level() and
just call intel_de_write_fw() directly.

This is prep work towards DSB based plane updates where these
wrappers are more of a hinderance.

Done with cocci mostly:
@@
expression D, R, L;
@@
- skl_write_wm_level(D, R, L)
+ intel_de_write_fw(D, R, skl_plane_wm_reg_val(L))

@@
expression D, R, B;
@@
- skl_ddb_entry_write(D, R, B)
+ intel_de_write_fw(D, R, skl_plane_ddb_reg_val(B))

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240510152329.24098-16-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
 2024-05-15 14:11:24 +03:00
Ville Syrjälä
1b455361d5 drm/i915: Extract skl_plane_{wm,ddb}_reg_val() 
Extract helpers to calculate the final wm/ddb register
values for skl+. Will allow me to more cleanly remove the
register write wrappers for these registers.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240510152329.24098-15-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
 2024-05-15 14:11:24 +03:00
Ville Syrjälä
6f320c6a00 drm/i915: Refactor skl+ plane register offset calculations 
Currently every skl+ plane register defines some intermediate
macros to calculate the final register offset. Pull all of that
into common macros, simplifying the final register offset stuff
into just five defines:
- raw register offsets for the planes 1 and 2 on pipes A and B
- the final parametrized macro

v2: Rebase

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240513170040.15393-1-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
 2024-05-15 14:11:24 +03:00
Ville Syrjälä
b7d4e9074a drm/i915: Drop a few unwanted tabs from skl+ plane reg defines 
A few extra tabs have snuck into the skl+ plane register bit
definitions. Remove them.

v2: Rebase

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240513170008.15338-1-ville.syrjala@linux.intel.com
 2024-05-15 14:11:23 +03:00
Ville Syrjälä
7deb50baf8 drm/i915: Use REG_BIT for PLANE_WM bits 
A couple of PLANE_WM bits were still using the hand
rolled (1<<N) form. Replace with REG_BIT().

v2: Rebase

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240513165945.15285-1-ville.syrjala@linux.intel.com
 2024-05-15 14:11:23 +03:00
Ville Syrjälä
14947416b1 drm/i915: Shuffle the skl+ plane register definitions 
Rearrange the plane skl+ universal plane register definitions:
- keep everything related to the same register in one place
- sort based on register offset
- unify the whitespace/etc a bit

v2: Define register contents after all offsets (Jani)

Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240513165909.15234-1-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
 2024-05-15 14:11:23 +03:00
Ville Syrjälä
86a30fb122 drm/i915: Drop useless PLANE_FOO_3 register defines 
We only need register defines for the first two planes
on the first two pipes. Nuke everything else.

v2: Drop a few more that snuck through

Reviewed-by: Jani Nikula <jani.nikula@intel.com> #v1
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240513165842.15199-1-ville.syrjala@linux.intel.com
 2024-05-15 14:11:23 +03:00
Ville Syrjälä
94b110106b drm/i915/gvt: Use PLANE_CTL and PLANE_SURF defines 
Stop hand rolling PLANE_CTL and PLANE_SURF for the third plane
and just use the real thing.

Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
CC: Zhi Wang <zhi.wang.linux@gmail.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240510152329.24098-9-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
 2024-05-15 14:11:23 +03:00
Ville Syrjälä
72d2031070 drm/i915/gvt: Use the full PLANE_KEY*() defines 
Stop hand rolling PLANE_KEY*() register defines and just
use the real thing.

Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
CC: Zhi Wang <zhi.wang.linux@gmail.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240510152329.24098-8-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
 2024-05-15 14:11:23 +03:00
Ville Syrjälä
9d7d1e8b1c drm/i915/gvt: Use the proper PLANE_AUX_OFFSET() define 
Stop hand rolling PLANE_AUX_OFFSET() and just use the real thing.

Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
CC: Zhi Wang <zhi.wang.linux@gmail.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240510152329.24098-7-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
 2024-05-15 14:11:23 +03:00
Ville Syrjälä
b86f87af34 drm/i915/gvt: Use the proper PLANE_AUX_DIST() define 
Stop hand rolling PLANE_AUX_DIST() and just use the real thing.

Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
CC: Zhi Wang <zhi.wang.linux@gmail.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240510152329.24098-6-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
 2024-05-15 14:11:23 +03:00
Ville Syrjälä
88b2f5fbcc drm/i915: Move skl+ wm/ddb registers to proper headers 
On SKL+ the watermark/DDB registers are proper per-plane
registers. Move the definitons to their respective files.

Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
CC: Zhi Wang <zhi.wang.linux@gmail.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240510152329.24098-5-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
 2024-05-15 14:11:23 +03:00
Ville Syrjälä
8cecf4aec3 drm/i915: Extract intel_cursor_regs.h 
Move most cursor register definitions into their own file.
Declutters i915_reg.h a bit more.

Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
CC: Zhi Wang <zhi.wang.linux@gmail.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240510152329.24098-4-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
 2024-05-15 14:11:21 +03:00