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drm/i915/psr: LunarLake PSR2_CTL[IO Wake Lines] is 6 bits wide

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On LunarLake  PSR2_CTL[IO Wake Lines] contains now bit 13:18. Take this
into account when enabling PSR2_CTL.

Bspec: 69885

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240517073005.2414293-3-jouni.hogander@intel.com
This commit is contained in:
Jouni Högander
2024-05-17 10:30:04 +03:00
parent 45430e7b7c
commit 30dee753ca
2 changed files with 6 additions and 0 deletions
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2
drivers/gpu/drm/i915/display/intel_psr.c
View File

@@ -958,6 +958,8 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
tmp = map[psr->alpm_parameters.fast_wake_lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES];
val |= TGL_EDP_PSR2_FAST_WAKE(tmp + TGL_EDP_PSR2_FAST_WAKE_MIN_LINES);
} else if (DISPLAY_VER(dev_priv) >= 20) {
val |= LNL_EDP_PSR2_IO_BUFFER_WAKE(psr->alpm_parameters.io_wake_lines);
} else if (DISPLAY_VER(dev_priv) >= 12) {
val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(psr->alpm_parameters.io_wake_lines);
val |= TGL_EDP_PSR2_FAST_WAKE(psr->alpm_parameters.fast_wake_lines);

4
drivers/gpu/drm/i915/display/intel_psr_regs.h
View File

@@ -172,6 +172,10 @@
#define TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES 5
#define TGL_EDP_PSR2_IO_BUFFER_WAKE(lines) REG_FIELD_PREP(TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK, \
(lines) - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES)
#define LNL_EDP_PSR2_IO_BUFFER_WAKE_MASK REG_GENMASK(18, 13)
#define LNL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES 5
#define LNL_EDP_PSR2_IO_BUFFER_WAKE(lines) REG_FIELD_PREP(LNL_EDP_PSR2_IO_BUFFER_WAKE_MASK, \
(lines) - LNL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES)
#define EDP_PSR2_FAST_WAKE_MASK REG_GENMASK(12, 11)
#define EDP_PSR2_FAST_WAKE_MAX_LINES 8
#define EDP_PSR2_FAST_WAKE(lines) REG_FIELD_PREP(EDP_PSR2_FAST_WAKE_MASK, \