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drm/i915: Rename selective fetch plane registers

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Rename the selective fetch plane registers to match the spec.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240516135622.3498-6-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Ville Syrjälä
2024-05-16 16:56:14 +03:00
parent 04c09e4b87
commit 0ff7639bb1
2 changed files with 11 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
drivers/gpu/drm/i915/display/intel_psr_regs.h
View File

@@ -280,23 +280,23 @@
_SEL_FETCH_PLANE_BASE_A(plane))
#define _SEL_FETCH_PLANE_CTL_1_A 0x70890
#define PLANE_SEL_FETCH_CTL(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
#define SEL_FETCH_PLANE_CTL(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
_SEL_FETCH_PLANE_CTL_1_A - \
_SEL_FETCH_PLANE_BASE_1_A)
#define PLANE_SEL_FETCH_CTL_ENABLE REG_BIT(31)
#define SEL_FETCH_PLANE_CTL_ENABLE REG_BIT(31)
#define _SEL_FETCH_PLANE_POS_1_A 0x70894
#define PLANE_SEL_FETCH_POS(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
#define SEL_FETCH_PLANE_POS(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
_SEL_FETCH_PLANE_POS_1_A - \
_SEL_FETCH_PLANE_BASE_1_A)
#define _SEL_FETCH_PLANE_SIZE_1_A 0x70898
#define PLANE_SEL_FETCH_SIZE(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
#define SEL_FETCH_PLANE_SIZE(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
_SEL_FETCH_PLANE_SIZE_1_A - \
_SEL_FETCH_PLANE_BASE_1_A)
#define _SEL_FETCH_PLANE_OFFSET_1_A 0x7089C
#define PLANE_SEL_FETCH_OFFSET(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
#define SEL_FETCH_PLANE_OFFSET(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
_SEL_FETCH_PLANE_OFFSET_1_A - \
_SEL_FETCH_PLANE_BASE_1_A)

12
drivers/gpu/drm/i915/display/skl_universal_plane.c
View File

@@ -705,7 +705,7 @@ static void icl_plane_disable_sel_fetch_arm(struct intel_plane *plane,
if (!crtc_state->enable_psr2_sel_fetch)
return;
intel_de_write_fw(i915, PLANE_SEL_FETCH_CTL(pipe, plane->id), 0);
intel_de_write_fw(i915, SEL_FETCH_PLANE_CTL(pipe, plane->id), 0);
}
static void
@@ -1304,7 +1304,7 @@ static void icl_plane_update_sel_fetch_noarm(struct intel_plane *plane,
val = (clip->y1 + plane_state->uapi.dst.y1) << 16;
val |= plane_state->uapi.dst.x1;
intel_de_write_fw(i915, PLANE_SEL_FETCH_POS(pipe, plane->id), val);
intel_de_write_fw(i915, SEL_FETCH_PLANE_POS(pipe, plane->id), val);
x = plane_state->view.color_plane[color_plane].x;
@@ -1319,13 +1319,13 @@ static void icl_plane_update_sel_fetch_noarm(struct intel_plane *plane,
val = y << 16 | x;
intel_de_write_fw(i915, PLANE_SEL_FETCH_OFFSET(pipe, plane->id),
intel_de_write_fw(i915, SEL_FETCH_PLANE_OFFSET(pipe, plane->id),
val);
/* Sizes are 0 based */
val = (drm_rect_height(clip) - 1) << 16;
val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1;
intel_de_write_fw(i915, PLANE_SEL_FETCH_SIZE(pipe, plane->id), val);
intel_de_write_fw(i915, SEL_FETCH_PLANE_SIZE(pipe, plane->id), val);
}
static void
@@ -1414,8 +1414,8 @@ static void icl_plane_update_sel_fetch_arm(struct intel_plane *plane,
return;
if (drm_rect_height(&plane_state->psr2_sel_fetch_area) > 0)
intel_de_write_fw(i915, PLANE_SEL_FETCH_CTL(pipe, plane->id),
PLANE_SEL_FETCH_CTL_ENABLE);
intel_de_write_fw(i915, SEL_FETCH_PLANE_CTL(pipe, plane->id),
SEL_FETCH_PLANE_CTL_ENABLE);
else
icl_plane_disable_sel_fetch_arm(plane, crtc_state);
}