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Ekansh Gupta
32fbd42e6b arm64: dts: qcom: monaco: add GDSP fastrpc-compute-cb nodes 
Add GDSP fastrpc compute-cb nodes for monaco SoC.

Signed-off-by: Ekansh Gupta <ekansh.gupta@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260415-monacogdsp-v1-1-077ded36c7fc@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-05-16 21:49:05 -05:00
Harrison Vanderbyl
69442723f3 dt-bindings: arm: qcom: Add Microsoft Surface Pro 12in 
Document the compatible string for the Microsoft Surface Pro
12-inch, 1st Edition with Snapdragon, based on the Qualcomm X1P42100
SoC.

Signed-off-by: Harrison Vanderbyl <harrison.vanderbyl@gmail.com>
Link: https://lore.kernel.org/r/627a1e2506fbed99e971250dbba64902af54232c.1778498477.git.harrison.vanderbyl@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-05-13 12:13:18 -05:00
Richard Acayan
c4b423835e arm64: dts: qcom: sdm670: add lpi pinctrl 
The Snapdragon 670 has a separate TLMM for audio pins. Add the device
node for it.

Also add reserved GPIOs for the Pixel 3a, which blocks access to the
sensor GPIOs.

Signed-off-by: Richard Acayan <mailingradian@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Acked-by: Linus Walleij <linusw@kernel.org>
Link: https://lore.kernel.org/r/20260331200658.1306-5-mailingradian@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-05-12 15:48:53 -05:00
Kuldeep Singh
7fb3d0512d arm64: dts: qcom: sm8450: Fix ICE reg size 
The ICE register region size was originally described incorrectly when
the ICE hardware was first introduced. The same value was later carried
over unchanged when the ICE node was split out from the UFS node into
its own DT entry.

Correct the register size to match the hardware specification.

Fixes: 276ee34a40 ("arm64: dts: qcom: sm8450: add Inline Crypto Engine registers and clock")
Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
Reviewed-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260402-ice_dt_reg_fix-v1-2-74e4c2129238@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-05-12 15:48:16 -05:00
Kuldeep Singh
fa9c7403af arm64: dts: qcom: kodiak: Fix ICE reg size 
The ICE register region on Kodiak is currently defined as 0x8000 bytes.
According to the hardware specification, the correct register size is
0x18000.

Update the ICE node reg property to match the hardware.

Fixes: dfd5ee7b34 ("arm64: dts: qcom: sc7280: Add inline crypto engine")
Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
Reviewed-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260402-ice_dt_reg_fix-v1-1-74e4c2129238@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-05-12 15:48:16 -05:00
Krzysztof Kozlowski
f4d7c5875a arm64: dts: qcom: sm8750: Fix DSI1 phy reference clock rate 
The DSI PHY CXO clock input is the SoC CXO divided by two.  DSI0 already
uses correct one, but DSI1 got copy-paste from SM8650.  Wrong clock
parent will cause incorrect DSI1 PHY PLL frequencies to be used making
the DSI panel non-working, although there is no upstream user of DSI1.

Fixes: 818ae2b389 ("arm64: dts: qcom: sm8750: Add display (MDSS) with Display CC")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260331165645.233965-2-krzysztof.kozlowski@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-05-12 15:45:55 -05:00
Aaron Kling
3f5dcc05cd arm64: dts: qcom: sm8550: add cpu OPP table with DDR, LLCC & L3 bandwidths 
Add the OPP tables for each CPU clusters (cpu0-1-2, cpu3-4-5-6 & cpu7)
to permit scaling the Last Level Cache Controller (LLCC), DDR and L3 cache
frequency by aggregating bandwidth requests of all CPU core with referenc
to the current OPP they are configured in by the LMH/EPSS hardware.

The effect is a proper caches & DDR frequency scaling when CPU cores
changes frequency.

The OPP tables were built using the downstream memlat ddr, llcc & l3
tables for each cluster types with the actual EPSS cpufreq LUT tables
from running a QCS8550 device.

Also add the OSC L3 Cache controller node.

Also add the interconnect entry for each cpu, with 3 different paths:
- CPU to Last Level Cache Controller (LLCC)
- Last Level Cache Controller (LLCC) to DDR
- L3 Cache from CPU to DDR interface

Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
Link: https://lore.kernel.org/r/20260330-sm8550-ddr-bw-scaling-v4-1-5020c06983a0@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-05-12 15:44:18 -05:00
Wojciech Slenska
9c633eec37 arm64: dts: qcom: agatti: Add IPA nodes 
Added IPA nodes and definitions.

Signed-off-by: Wojciech Slenska <wojciech.slenska@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260310112309.79261-3-wojciech.slenska@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-05-12 15:41:42 -05:00
Taniya Das
4a1779f42e arm64: dts: qcom: sm8750: Add camera clock controller 
The camera clock controller is split into cambistmclk and camcc. The
cambist clock controller handles the mclks and the rest of the clocks of
camera are part of the camcc clock controller.
Add the camcc clock controller device node for SM8750 SoC.

Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260511-sm8750_camcc_dt-v4-1-eab4b6c3eaea@oss.qualcomm.com
[bjorn: Fixed include file order]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-05-12 15:05:50 -05:00
Sibi Sankar
377665c607 arm64: dts: qcom: glymur-crd: Enable ADSP and CDSP 
Enable ADSP and CDSP on Glymur CRD board.

Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260313120814.1312410-6-sibi.sankar@oss.qualcomm.com
[bjorn: Moved snippet to common glymur-crd.dtsi]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-05-11 21:18:47 -05:00
Sibi Sankar
cd1d174c75 arm64: dts: qcom: glymur: Add ADSP and CDSP for Glymur SoC 
Add remoteproc PAS loader for ADSP and CDSP with its fastrpc nodes.

Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260313120814.1312410-5-sibi.sankar@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-05-11 21:17:29 -05:00
Taniya Das
675fec65df arm64: dts: qcom: Add support for MM clock controllers for Glymur 
Add the device nodes for the multimedia clock controllers videocc, gpucc
and gxclkctl.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260410-glymur_mmcc_dt_config_v2-v3-1-acce9d106e72@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-05-11 20:04:07 -05:00
Abel Vesa
347fa2fa64 arm64: dts: qcom: glymur: Mark USB SS1 and SS2 as role-switch capable 
Like USB SS0, the USB SS1 and SS2 controllers on Glymur also support
USB role switching.

Describe this by adding the 'usb-role-switch' property to both controllers.

Fixes: 4eee57dd4d ("arm64: dts: qcom: glymur: Add USB related nodes")
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260415-dts-qcom-glymur-usb-role-switch-fix-v1-1-409e1a257f1f@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-05-11 19:59:54 -05:00
Abel Vesa
d9dc254945 arm64: dts: qcom: glymur-crd: Drop forced host mode for USB SS0 and SS1 
The two USB Type-C ports on Glymur CRD are dual-role capable.

Do not force their controllers into host mode. Drop the explicit
'dr_mode = "host"' properties so they can use their default OTG mode
instead.

Fixes: c8b6302945 ("arm64: dts: qcom: glymur-crd: Enable USB support")
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260415-dts-qcom-glymur-usb-role-switch-fix-v1-2-409e1a257f1f@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-05-11 19:59:52 -05:00
Kathiravan Thirumoorthy
c50080d313 arm64: dts: qcom: ipq9650: add watchdog node 
Add the watchdog device node for IPQ9650 SoC.

Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260511-ipq9650_wdt-v1-1-1948934c1e12@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-05-11 18:15:10 -05:00
Kathiravan Thirumoorthy
8cef25a004 arm64: dts: qcom: add IPQ9650 SoC and rdp488 board support 
Add initial device tree support for the Qualcomm IPQ9650 SoC and
rdp488 board.

Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260507-ipq9650_boot_to_shell-v3-4-62742b49c991@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-05-11 18:15:05 -05:00
Kathiravan Thirumoorthy
5bfa2c53c6 dt-bindings: qcom: add IPQ9650 boards 
Document the new IPQ9650 SoC/board device tree bindings.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260507-ipq9650_boot_to_shell-v3-3-62742b49c991@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-05-11 18:15:05 -05:00
Bjorn Andersson
da8d82b8b6 Merge branch '20260507-ipq9650_boot_to_shell-v3-1-62742b49c991@oss.qualcomm.com' into arm64-for-7.2 
Merge the QCS9650 GCC DeviceTree binding from topic branch, to get
access to clock and reset constants.
 2026-05-11 18:14:18 -05:00
Kathiravan Thirumoorthy
f92b778251 dt-bindings: clock: add Qualcomm IPQ9650 GCC 
Add binding for the Qualcomm IPQ9650 Global Clock Controller.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260507-ipq9650_boot_to_shell-v3-1-62742b49c991@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-05-11 18:13:21 -05:00
Haritha S K
f5fb358c7d arm64: dts: qcom: glymur: Enable cpufreq cooling devices 
Add cooling-cells property to the CPU nodes to support cpufreq
cooling devices.

Signed-off-by: Haritha S K <haritha.k@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260507-glymur_cpu_freq-v1-1-d566cc1d32c3@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-05-09 22:29:21 -05:00
Abel Vesa
627aab9bfe arm64: dts: qcom: glymur-crd: Enable LID sensor 
The Glymur CRD has a Hall-effect sensor used for detecting when the
lid is opened or closed. Describe it as an SW_LID gpio-key switch.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260428-glymur-dts-add-lid-sensor-v1-1-470cc168e70a@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-05-09 22:17:45 -05:00
Luca Weiss
b1b08554e3 arm64: defconfig: Enable LPASS LPI pin controller for SM6350 
Build the LPASS LPI pin controller driver for SM6350 as module, which is
required for audio functionality on boards such as the Fairphone 4.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20260430-sm6350-lpi-tlmm-v2-5-81d068025b97@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-05-09 21:35:18 -05:00
Luca Weiss
6303981271 arm64: dts: qcom: sm6350: add LPASS LPI pin controller 
Add LPASS LPI pinctrl node required for audio functionality on SM6350.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20260430-sm6350-lpi-tlmm-v2-4-81d068025b97@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-05-09 21:35:18 -05:00
Xin Liu
bde860892c arm64: dts: qcom: purwa: Add EL2 overlay for purwa-iot-evk 
Add support for building an EL2 combined DTB for the purwa-iot-evk
in the Qualcomm DTS Makefile.

The new purwa-iot-evk-el2.dtb is generated by combining the base
purwa-iot-evk.dtb with the x1-el2.dtbo overlay, enabling EL2-specific
configurations required by the platform.

Signed-off-by: Xin Liu <xin.liu@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260417054200.2402281-1-xin.liu@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-05-09 21:12:39 -05:00
Paul Sajna
0f7c65c11f arm64: dts: qcom: sdm845-lg: Enable qcom,snoc-host-cap-skip-quirk 
The WCN3990 firmware for judyln does not respond to the request for
host capabilities. Add the devicetree quirk to skip this request.

Signed-off-by: Paul Sajna <sajattack@postmarketos.org>
Reviewed-by: David Heidelberg <david@ixit.cz>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260408-judyln-followup-v1-4-823467519b59@postmarketos.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-05-09 10:33:00 -05:00
Paul Sajna
3f779220c6 arm64: dts: qcom: sdm845-lg-{judyln, judyp}: Reference memory region in fb 
To prevent duplicating the framebuffer address and size point out the
existing framebuffer memory region instead of specifying the address
manually.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Paul Sajna <sajattack@postmarketos.org>
Reviewed-by: David Heidelberg <david@ixit.cz>
Link: https://lore.kernel.org/r/20260408-judyln-followup-v1-3-823467519b59@postmarketos.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-05-09 10:32:59 -05:00
Paul Sajna
d2735f5690 arm64: dts: qcom: sdm845-lg-common: Change ipa gsi-loader to 'self', add memory-region 
The modem firmware for this device doesn't preload the IPA firmware
and requires the OS handles that instead. Set qcom,gsi-loader = "self"
to reflect that.

Ensure the ipa uses the correct memory.

ipa 1e40000.ipa: channel 4 limited to 256 TREs
ipa 1e40000.ipa: IPA driver initialized
ipa 1e40000.ipa: received modem starting event
ipa 1e40000.ipa: received modem running event

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Paul Sajna <sajattack@postmarketos.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260408-judyln-followup-v1-2-823467519b59@postmarketos.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-05-09 10:32:59 -05:00
Paul Sajna
4eacad2d8e arm64: dts: qcom: sdm845-lg-common: Add camera flash 
Camera doesn't work yet (imx351), but we can use the flash as a flashlight.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Paul Sajna <sajattack@postmarketos.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260408-judyln-followup-v1-1-823467519b59@postmarketos.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-05-09 10:32:59 -05:00
Shawn Guo
8222873cd4 arm64: dts: qcom: lemans: Move PCIe devices into soc node 
These PCIe devices with MMIO address should be inside soc node rather
than outside.

Fixes: 489f14be0e ("arm64: dts: qcom: sa8775p: Add pcie0 and pcie1 nodes")
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260331090147.18522-1-shengchao.guo@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-05-09 10:32:23 -05:00
Le Qi
141d7ea503 arm64: dts: qcom: talos-evk: Add sound card support with DA7212 codec 
Add the sound card node for QCS615 Talos EVK with DA7212 codec
connected over the Primary MI2S interface. The configuration enables
headphone playback and headset microphone capture, both of which have
been tested to work.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Le Qi <le.qi@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260409030156.155455-3-le.qi@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-05-09 10:30:31 -05:00
Le Qi
d962cd7c49 arm64: dts: qcom: talos: Add GPR node, audio services, and MI2S1 TLMM pins 
This patch adds the Generic Pack Router (GPR) node together with
Audio Process Manager (APM) and Proxy Resource Manager (PRM)
audio service nodes to the Talos device tree description.

It also introduces MI2S1 pinctrl states for data0, data1, sck,
and ws lines, grouped into a single entry at the SoC-level DTSI
for better reuse and clarity.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Le Qi <le.qi@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260409030156.155455-2-le.qi@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-05-09 10:30:31 -05:00
Krzysztof Kozlowski
08569936a1 arm64: dts: qcom: Use GIC_SPI macro for interrupt-map 
Make the complicated interrupt-map property (with multiple '0' entries)
a bit more readable by using known define for GIC_SPI.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260407201839.25759-2-krzysztof.kozlowski@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-05-09 10:29:34 -05:00
Amit Pundir
113343d576 arm64: dts: qcom: sdm845-xiaomi-beryllium: Enable ath10k host-cap skip quirk 
The Wi-Fi firmware used on Xiaomi Poco F1 (beryllium) phone doesn't
support the host-capability QMI request, so add a quirk to skip it on
this device.

Signed-off-by: Amit Pundir <amit.pundir@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: David Heidelberg <david@ixit.cz>
Link: https://lore.kernel.org/r/20260407-skip-host-cam-qmi-req-v5-3-dfa8a05c6538@ixit.cz
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-05-09 10:29:26 -05:00
Nickolay Goppen
dc11a2824f arm64: dts: qcom: sdm630: assign adsp_mem region to ADSP FastRPC node 
Downstream [1] ADSP FastRPC node has the adsp_mem region assigned, so
assign it to the ADSP FastRPC node.

[1]: https://github.com/xiaomi-sdm660/android_kernel_xiaomi_sdm660/blob/11-EAS/arch/arm/boot/dts/qcom/sdm660.dtsi#L1693

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Ekansh Gupta <ekansh.gupta@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Nickolay Goppen <setotau@mainlining.org>
Link: https://lore.kernel.org/r/20260429-qcom-sdm660-cdsp-adsp-fastrpc-dts-fix-v5-5-16bc82e622ad@mainlining.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-05-09 10:01:24 -05:00
Nickolay Goppen
ce414263e9 arm64: dts: qcom: sdm630: describe adsp_mem region properly 
Downstream [1] this region is marked as shared, reusable and dynamic so
describe it that way.

[1]: https://github.com/xiaomi-sdm660/android_kernel_xiaomi_sdm660/blob/11-EAS/arch/arm/boot/dts/qcom/sdm660.dtsi#L448

Fixes: b190fb0106 ("arm64: dts: qcom: sdm630: Add sdm630 dts file")
Cc: stable@vger.kernel.org
Reviewed-by: Ekansh Gupta <ekansh.gupta@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Nickolay Goppen <setotau@mainlining.org>
Link: https://lore.kernel.org/r/20260429-qcom-sdm660-cdsp-adsp-fastrpc-dts-fix-v5-4-16bc82e622ad@mainlining.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-05-09 10:01:24 -05:00
Nickolay Goppen
e8e1fb5c70 arm64: dts: qcom: sdm630: set adsp compute-cbs' regs properly 
Changing FastRPC compute-cbs' reg values to matching iommu streams
solves SMMU translation errors when trying to use FastRPC on ADSP
so change FastRPC compute-cbs' reg values that way

Fixes: af2ce72966 ("arm64: dts: qcom: sdm630: Add FastRPC nodes to ADSP")
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Ekansh Gupta <ekansh.gupta@oss.qualcomm.com>
Signed-off-by: Nickolay Goppen <setotau@mainlining.org>
Link: https://lore.kernel.org/r/20260429-qcom-sdm660-cdsp-adsp-fastrpc-dts-fix-v5-3-16bc82e622ad@mainlining.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-05-09 10:01:24 -05:00
Nickolay Goppen
708ab9d3bc arm64: dts: qcom: sdm660: set cdsp compute-cbs' regs properly 
Changing FastRPC compute-cbs' reg values to matching iommu streams
solves SMMU translation errors when trying to use FastRPC on CDSP
so change FastRPC compute-cbs' reg values that way

Fixes: c0c32a9e34 ("arm64: dts: qcom: sdm630/660: Add CDSP-related nodes")
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Ekansh Gupta <ekansh.gupta@oss.qualcomm.com>
Signed-off-by: Nickolay Goppen <setotau@mainlining.org>
Link: https://lore.kernel.org/r/20260429-qcom-sdm660-cdsp-adsp-fastrpc-dts-fix-v5-2-16bc82e622ad@mainlining.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-05-09 10:01:24 -05:00
Nickolay Goppen
db6ae6650c dt-bindings: firmware: qcom: scm: add CP_ADSP_SHARED VMID 
CP_ADSP_SHARED is used in FastRPC driver for older SoC's such as sdm660
for interacting with ADSP memory region [1]

[1]: https://github.com/xiaomi-sdm660/android_kernel_xiaomi_sdm660/blob/11-EAS/drivers/char/adsprpc.c#L3602

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Nickolay Goppen <setotau@mainlining.org>
Link: https://lore.kernel.org/r/20260429-qcom-sdm660-cdsp-adsp-fastrpc-dts-fix-v5-1-16bc82e622ad@mainlining.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-05-09 10:01:24 -05:00
Viken Dadhaniya
8289feadbc arm64: dts: qcom: sc7180: Add QSPI memory interconnect path 
Add the missing QSPI-to-memory interconnect path alongside the existing
configuration path. Without this path, the interconnect framework cannot
correctly vote for the bandwidth required by QSPI DMA data transfers.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260429-spi-nor-v5-7-993016c9711e@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-05-07 20:27:45 -05:00
Viken Dadhaniya
45287b9e5e arm64: dts: qcom: kodiak: Add QSPI memory interconnect path 
Add the missing QSPI-to-memory interconnect path alongside the existing
configuration path. Without it, the interconnect framework cannot vote for
the bandwidth required by QSPI DMA data transfers.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260429-spi-nor-v5-6-993016c9711e@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-05-07 20:27:45 -05:00
Viken Dadhaniya
d2ed3f777f arm64: dts: qcom: qcs615-ride: Enable QSPI and NOR flash 
The QCS615 Ride board has a SPI-NOR flash connected to the QSPI controller
on CS0. Enable the QSPI controller and add the corresponding SPI-NOR flash
node to allow the system to access it.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260429-spi-nor-v5-5-993016c9711e@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-05-07 20:27:45 -05:00
Viken Dadhaniya
ef4d269e55 arm64: dts: qcom: talos: Add QSPI support 
The Talos (QCS615) platform includes a QSPI controller used for accessing
external flash storage. Add the QSPI OPP table, TLMM pinmux entries, and
the QSPI controller node to enable support for this hardware.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260429-spi-nor-v5-4-993016c9711e@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-05-07 20:27:45 -05:00
Harshal Dev
93e08fdc55 arm64: dts: qcom: glymur: Add crypto engine and BAM 
On almost all Qualcomm platforms, including Glymur, there is a Crypto
engine IP block to which the CPU can off-load cryptographic computations
for achieving acceleration.
The engine is also DMA capable due to the presence of an associated Bus
Access Manager (BAM) module.

Describe the Crypto engine and its BAM.

Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260505-glymur_crypto_enablement-v2-2-bf115aeb1459@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-05-07 20:26:27 -05:00
Alexander Koskovich
208af18362 arm64: dts: qcom: milos: Add QCrypto nodes 
Add the QCE and Crypto BAM DMA nodes.

Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
Reviewed-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260405-milos-qce-v1-2-6996fb0b8a9c@pm.me
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-05-07 20:26:13 -05:00
Krzysztof Kozlowski
5a95bd4771 arm64: dts: qcom: eliza: Add QCE crypto 
Add nodes for the BAM DAM and QCE crypto engine.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260407-crypto-qcom-eliza-v1-2-40f61a1454a2@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-05-07 20:17:33 -05:00
Dikshita Agarwal
f8874bc579 arm64: dts: qcom: agatti: add higher OPP levels 
Add additional OPP entries for the Agatti platform to support higher
operating frequencies as specified in the hardware documentation.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260507-iris-ar50lt-v1-16-d22cccedc3e2@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-05-07 15:59:24 -05:00
Vishnu Saini
f0b64466e2 arm64: dts: qcom: lemans-evk-ifp-mezzanine: Enable mdss1 display Port 
Enable DP controllers, DPTX0 and DPTX1 alongside
their corresponding PHYs of mdss1 which corresponds to eDP2
and eDP3.

Signed-off-by: Vishnu Saini <vishnu.saini@oss.qualcomm.com>
Signed-off-by: Mani Chandana Ballary Kuntumalla <quic_mkuntuma@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260402095003.3758176-4-quic_mkuntuma@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-04-27 14:52:31 -05:00
Mani Chandana Ballary Kuntumalla
fcc1a19f5b arm64: dts: qcom: lemans-ride: Enable mdss1 display Port 
This change enables DP controllers, DPTX0 and DPTX1 alongside
their corresponding PHYs of mdss1 which corresponds to edp2
and edp3.

Signed-off-by: Mani Chandana Ballary Kuntumalla <quic_mkuntuma@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260402095003.3758176-3-quic_mkuntuma@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-04-27 14:52:31 -05:00
Mani Chandana Ballary Kuntumalla
3e6cd0c43c arm64: dts: qcom: lemans: add mdss1 display device nodes 
Add devicetree changes to enable second Mobile Display Subsystem (mdss1),
Display Processing Unit(DPU), Display Port(DP), Display clock controller
(dispcc1) and eDP PHYs on the Qualcomm Lemans platform.

Signed-off-by: Mahadevan P <mahadevan.p@oss.qualcomm.com>
Signed-off-by: Mani Chandana Ballary Kuntumalla <quic_mkuntuma@quicinc.com>
Link: https://lore.kernel.org/r/20260402095003.3758176-2-quic_mkuntuma@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-04-27 14:52:31 -05:00
Pengyu Luo
1825ac5e2a arm64: dts: qcom: sc8280xp: Add ADSP FastRPC node 
Add the FastRPC node to enable offloading compute tasks to the ADSP
via the FastRPC framework.

Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260403120753.105869-1-mitltlatltl@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-04-27 14:49:24 -05:00