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arm64: dts: qcom: sm8750: Add display (MDSS) with Display CC
Add device nodes for entire display: MDSS, DPU, DSI, DSI PHYs, DisplayPort and Display Clock Controller. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260317-sm8750-display-dts-v5-1-fb53371e251c@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Krzysztof Kozlowski
committed by
Bjorn Andersson
Bjorn Andersson
parent
2755bdd02a
commit
818ae2b389
@@ -3,7 +3,9 @@
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/clock/qcom,sm8750-dispcc.h>
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#include <dt-bindings/clock/qcom,sm8750-gcc.h>
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#include <dt-bindings/clock/qcom,sm8750-tcsr.h>
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#include <dt-bindings/clock/qcom,sm8750-videocc.h>
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@@ -3001,6 +3003,436 @@ videocc: clock-controller@aaf0000 {
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#power-domain-cells = <1>;
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};
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mdss: display-subsystem@ae00000 {
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compatible = "qcom,sm8750-mdss";
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reg = <0x0 0x0ae00000 0x0 0x1000>;
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reg-names = "mdss";
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&gcc GCC_DISP_HF_AXI_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_CLK>;
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resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
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interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
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<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
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&config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
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interconnect-names = "mdp0-mem",
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"cpu-cfg";
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power-domains = <&dispcc MDSS_GDSC>;
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iommus = <&apps_smmu 0x800 0x2>;
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interrupt-controller;
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#interrupt-cells = <1>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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status = "disabled";
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mdss_mdp: display-controller@ae01000 {
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compatible = "qcom,sm8750-dpu";
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reg = <0x0 0x0ae01000 0x0 0x93000>,
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<0x0 0x0aeb0000 0x0 0x2008>;
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reg-names = "mdp",
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"vbif";
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interrupts-extended = <&mdss 0>;
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clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
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<&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_CLK>,
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<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
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clock-names = "nrt_bus",
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"iface",
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"lut",
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"core",
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"vsync";
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assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
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assigned-clock-rates = <19200000>;
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operating-points-v2 = <&mdp_opp_table>;
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power-domains = <&rpmhpd RPMHPD_MMCX>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dpu_intf1_out: endpoint {
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remote-endpoint = <&mdss_dsi0_in>;
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};
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};
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port@1 {
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reg = <1>;
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dpu_intf2_out: endpoint {
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remote-endpoint = <&mdss_dsi1_in>;
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};
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};
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port@2 {
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reg = <2>;
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dpu_intf0_out: endpoint {
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remote-endpoint = <&mdss_dp0_in>;
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};
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};
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};
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mdp_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-156000000 {
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opp-hz = /bits/ 64 <156000000>;
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required-opps = <&rpmhpd_opp_low_svs_d1>;
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};
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opp-207000000 {
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opp-hz = /bits/ 64 <207000000>;
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required-opps = <&rpmhpd_opp_low_svs>;
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};
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opp-337000000 {
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opp-hz = /bits/ 64 <337000000>;
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required-opps = <&rpmhpd_opp_svs>;
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};
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opp-417000000 {
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opp-hz = /bits/ 64 <417000000>;
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required-opps = <&rpmhpd_opp_svs_l1>;
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};
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opp-532000000 {
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opp-hz = /bits/ 64 <532000000>;
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required-opps = <&rpmhpd_opp_nom>;
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};
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opp-575000000 {
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opp-hz = /bits/ 64 <575000000>;
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required-opps = <&rpmhpd_opp_nom_l1>;
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};
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};
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};
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mdss_dsi0: dsi@ae94000 {
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compatible = "qcom,sm8750-dsi-ctrl", "qcom,mdss-dsi-ctrl";
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reg = <0x0 0x0ae94000 0x0 0x400>;
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reg-names = "dsi_ctrl";
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interrupts-extended = <&mdss 4>;
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clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
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<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
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<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
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<&dispcc DISP_CC_MDSS_ESC0_CLK>,
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<&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&gcc GCC_DISP_HF_AXI_CLK>,
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<&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>,
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<&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
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<&dispcc DISP_CC_ESYNC0_CLK>,
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<&dispcc DISP_CC_OSC_CLK>,
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<&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
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<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
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clock-names = "byte",
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"byte_intf",
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"pixel",
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"core",
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"iface",
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"bus",
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"dsi_pll_pixel",
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"dsi_pll_byte",
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"esync",
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"osc",
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"byte_src",
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"pixel_src";
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operating-points-v2 = <&mdss_dsi_opp_table>;
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power-domains = <&rpmhpd RPMHPD_MMCX>;
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phys = <&mdss_dsi0_phy>;
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phy-names = "dsi";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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mdss_dsi0_in: endpoint {
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remote-endpoint = <&dpu_intf1_out>;
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};
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};
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port@1 {
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reg = <1>;
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mdss_dsi0_out: endpoint {
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};
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};
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};
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mdss_dsi_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-140630000 {
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opp-hz = /bits/ 64 <140630000>;
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required-opps = <&rpmhpd_opp_low_svs_d1>;
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};
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opp-187500000 {
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opp-hz = /bits/ 64 <187500000>;
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required-opps = <&rpmhpd_opp_low_svs>;
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};
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opp-300000000 {
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opp-hz = /bits/ 64 <300000000>;
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required-opps = <&rpmhpd_opp_svs>;
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};
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opp-358000000 {
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opp-hz = /bits/ 64 <358000000>;
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required-opps = <&rpmhpd_opp_svs_l1>;
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};
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};
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};
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mdss_dsi0_phy: phy@ae95000 {
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compatible = "qcom,sm8750-dsi-phy-3nm";
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reg = <0x0 0x0ae95000 0x0 0x200>,
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<0x0 0x0ae95200 0x0 0x280>,
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<0x0 0x0ae95500 0x0 0x400>;
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reg-names = "dsi_phy",
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"dsi_phy_lane",
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"dsi_pll";
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clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&bi_tcxo_div2>;
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clock-names = "iface",
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"ref";
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#clock-cells = <1>;
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#phy-cells = <0>;
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status = "disabled";
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};
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mdss_dsi1: dsi@ae96000 {
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compatible = "qcom,sm8750-dsi-ctrl", "qcom,mdss-dsi-ctrl";
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reg = <0x0 0x0ae96000 0x0 0x400>;
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reg-names = "dsi_ctrl";
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interrupts-extended = <&mdss 5>;
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clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
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<&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
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<&dispcc DISP_CC_MDSS_PCLK1_CLK>,
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<&dispcc DISP_CC_MDSS_ESC1_CLK>,
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<&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&gcc GCC_DISP_HF_AXI_CLK>,
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<&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>,
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<&mdss_dsi1_phy DSI_BYTE_PLL_CLK>,
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<&dispcc DISP_CC_ESYNC1_CLK>,
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<&dispcc DISP_CC_OSC_CLK>,
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<&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
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<&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
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clock-names = "byte",
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"byte_intf",
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"pixel",
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"core",
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"iface",
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"bus",
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"dsi_pll_pixel",
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"dsi_pll_byte",
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"esync",
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"osc",
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"byte_src",
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"pixel_src";
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operating-points-v2 = <&mdss_dsi_opp_table>;
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power-domains = <&rpmhpd RPMHPD_MMCX>;
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phys = <&mdss_dsi1_phy>;
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phy-names = "dsi";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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mdss_dsi1_in: endpoint {
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remote-endpoint = <&dpu_intf2_out>;
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};
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};
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port@1 {
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reg = <1>;
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mdss_dsi1_out: endpoint {
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};
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};
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};
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};
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mdss_dsi1_phy: phy@ae97000 {
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compatible = "qcom,sm8750-dsi-phy-3nm";
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reg = <0x0 0x0ae97000 0x0 0x200>,
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<0x0 0x0ae97200 0x0 0x280>,
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<0x0 0x0ae97500 0x0 0x400>;
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reg-names = "dsi_phy",
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"dsi_phy_lane",
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"dsi_pll";
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clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&rpmhcc RPMH_CXO_CLK>;
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clock-names = "iface",
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"ref";
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#clock-cells = <1>;
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#phy-cells = <0>;
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status = "disabled";
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};
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mdss_dp0: displayport-controller@af54000 {
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compatible = "qcom,sm8750-dp", "qcom,sm8650-dp";
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reg = <0x0 0xaf54000 0x0 0x104>,
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<0x0 0xaf54200 0x0 0xc0>,
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<0x0 0xaf55000 0x0 0x770>,
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<0x0 0xaf56000 0x0 0x9c>,
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<0x0 0xaf57000 0x0 0x9c>;
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interrupts-extended = <&mdss 12>;
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clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
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<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
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<&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
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<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
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<&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
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clock-names = "core_iface",
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"core_aux",
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"ctrl_link",
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"ctrl_link_iface",
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"stream_pixel",
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"stream_1_pixel";
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assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
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<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
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<&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
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assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
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<&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
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<&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
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operating-points-v2 = <&dp_opp_table>;
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power-domains = <&rpmhpd RPMHPD_MMCX>;
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phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>;
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phy-names = "dp";
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#sound-dai-cells = <0>;
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status = "disabled";
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dp_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-270000000 {
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opp-hz = /bits/ 64 <270000000>;
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required-opps = <&rpmhpd_opp_low_svs>;
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};
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opp-540000000 {
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opp-hz = /bits/ 64 <540000000>;
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required-opps = <&rpmhpd_opp_svs_l1>;
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};
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opp-810000000 {
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opp-hz = /bits/ 64 <810000000>;
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required-opps = <&rpmhpd_opp_nom>;
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};
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};
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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mdss_dp0_in: endpoint {
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remote-endpoint = <&dpu_intf0_out>;
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};
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};
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port@1 {
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reg = <1>;
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mdss_dp0_out: endpoint {
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data-lanes = <0 1 2 3>;
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};
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};
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};
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};
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};
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dispcc: clock-controller@af00000 {
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compatible = "qcom,sm8750-dispcc";
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reg = <0x0 0x0af00000 0x0 0x20000>;
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clocks = <&bi_tcxo_div2>,
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<&bi_tcxo_ao_div2>,
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<&gcc GCC_DISP_AHB_CLK>,
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<&sleep_clk>,
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<&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
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<&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>,
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<&mdss_dsi1_phy DSI_BYTE_PLL_CLK>,
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<&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>,
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<&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
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<&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
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<0>, /* dp1 */
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<0>,
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<0>, /* dp2 */
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<0>,
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<0>, /* dp3 */
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<0>;
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power-domains = <&rpmhpd RPMHPD_MMCX>;
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required-opps = <&rpmhpd_opp_low_svs>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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pdc: interrupt-controller@b220000 {
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compatible = "qcom,sm8750-pdc", "qcom,pdc";
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reg = <0x0 0x0b220000 0x0 0x10000>, <0x0 0x164400f0 0x0 0x64>;
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