mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-08-29 01:04:14 -04:00
arm64: dts: qcom: add IPQ9650 SoC and rdp488 board support
Add initial device tree support for the Qualcomm IPQ9650 SoC and rdp488 board. Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260507-ipq9650_boot_to_shell-v3-4-62742b49c991@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Kathiravan Thirumoorthy
committed by
Bjorn Andersson
Bjorn Andersson
parent
5bfa2c53c6
commit
8cef25a004
@@ -39,6 +39,7 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp433.dtb ipq9574-rdp433-emmc.dtb
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dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp449.dtb
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dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp453.dtb
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dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp454.dtb
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dtb-$(CONFIG_ARCH_QCOM) += ipq9650-rdp488.dtb
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dtb-$(CONFIG_ARCH_QCOM) += kaanapali-mtp.dtb
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dtb-$(CONFIG_ARCH_QCOM) += kaanapali-qrd.dtb
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dtb-$(CONFIG_ARCH_QCOM) += lemans-evk.dtb
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79
arch/arm64/boot/dts/qcom/ipq9650-rdp488.dts
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79
arch/arm64/boot/dts/qcom/ipq9650-rdp488.dts
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@@ -0,0 +1,79 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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*/
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/dts-v1/;
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#include "ipq9650.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. IPQ9650 RDP488";
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compatible = "qcom,ipq9650-rdp488", "qcom,ipq9650";
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aliases {
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serial0 = &uart1;
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};
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chosen {
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stdout-path = "serial0";
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};
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};
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&sdhc {
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max-frequency = <192000000>;
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bus-width = <4>;
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mmc-ddr-1_8v;
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mmc-hs200-1_8v;
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pinctrl-0 = <&sdhc_default_state>;
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pinctrl-names = "default";
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status = "okay";
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};
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&sleep_clk {
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clock-frequency = <32000>;
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};
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&tlmm {
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qup_uart1_default_state: qup-uart1-default-state {
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pins = "gpio43", "gpio44";
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function = "qup_se6";
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drive-strength = <8>;
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bias-pull-down;
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};
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sdhc_default_state: sdhc-default-state {
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clk-pins {
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pins = "gpio5";
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function = "sdc_clk";
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drive-strength = <8>;
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bias-disable;
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};
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cmd-pins {
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pins = "gpio4";
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function = "sdc_cmd";
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drive-strength = <8>;
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bias-pull-up;
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};
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data-pins {
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pins = "gpio0", "gpio1", "gpio2", "gpio3";
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function = "sdc_data";
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drive-strength = <8>;
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bias-pull-up;
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};
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};
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};
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&uart1 {
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pinctrl-0 = <&qup_uart1_default_state>;
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pinctrl-names = "default";
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status = "okay";
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};
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&xo_board {
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clock-frequency = <24000000>;
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};
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377
arch/arm64/boot/dts/qcom/ipq9650.dtsi
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377
arch/arm64/boot/dts/qcom/ipq9650.dtsi
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@@ -0,0 +1,377 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,ipq9650-gcc.h>
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#include <dt-bindings/reset/qcom,ipq9650-gcc.h>
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&intc>;
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clocks {
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sleep_clk: sleep-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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xo_board: xo-board-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0>;
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enable-method = "psci";
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next-level-cache = <&l2_0>;
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l2_0: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_0>;
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l3_0: l3-cache {
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compatible = "cache";
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cache-level = <3>;
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cache-unified;
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};
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};
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};
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cpu1: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x100>;
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enable-method = "psci";
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next-level-cache = <&l2_100>;
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l2_100: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_0>;
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};
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};
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cpu2: cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x200>;
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enable-method = "psci";
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l2_200: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_0>;
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};
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};
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cpu3: cpu@300 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x300>;
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enable-method = "psci";
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l2_300: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_0>;
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};
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};
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cpu4: cpu@400 {
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device_type = "cpu";
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compatible = "arm,cortex-a78";
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reg = <0x400>;
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enable-method = "psci";
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next-level-cache = <&l2_400>;
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l2_400: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_0>;
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};
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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core2 {
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cpu = <&cpu2>;
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};
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core3 {
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cpu = <&cpu3>;
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};
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core4 {
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cpu = <&cpu4>;
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};
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};
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};
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};
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firmware {
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optee {
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compatible = "linaro,optee-tz";
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method = "smc";
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};
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scm {
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compatible = "qcom,scm-ipq9650", "qcom,scm";
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};
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};
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memory@80000000 {
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device_type = "memory";
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/* We expect the bootloader to fill in the size */
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reg = <0x0 0x80000000 0x0 0x0>;
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};
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pmu-a55 {
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compatible = "arm,cortex-a55-pmu";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
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};
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pmu-a78 {
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compatible = "arm,cortex-a78-pmu";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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bootloader@8a100000 {
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reg = <0x0 0x8a100000 0x0 0x400000>;
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no-map;
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};
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smem@8a500000 {
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compatible = "qcom,smem";
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reg = <0x0 0x8a500000 0x0 0x40000>;
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no-map;
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hwlocks = <&tcsr_mutex 3>;
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};
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tfa@8a600000 {
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reg = <0x0 0x8a600000 0x0 0x80000>;
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no-map;
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};
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optee@8a680000 {
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reg = <0x0 0x8a680000 0x0 0x280000>;
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no-map;
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};
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};
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soc@0 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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dma-ranges = <0 0 0 0 0x10 0>;
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ranges = <0 0 0 0 0x10 0>;
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tlmm: pinctrl@1000000 {
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compatible = "qcom,ipq9650-tlmm";
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reg = <0x0 0x01000000 0x0 0x300000>;
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interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH 0>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&tlmm 0 0 54>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gcc: clock-controller@1800000 {
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compatible = "qcom,ipq9650-gcc";
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reg = <0x0 0x01800000 0x0 0x40000>;
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clocks = <&xo_board>,
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<&sleep_clk>,
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<0>,
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<0>,
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<0>,
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<0>,
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<0>,
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<0>,
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<0>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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tcsr_mutex: hwlock@1917000 {
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compatible = "qcom,tcsr-mutex";
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reg = <0x0 0x01917000 0x0 0x57000>;
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#hwlock-cells = <1>;
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};
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qupv3: geniqup@1ac0000 {
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compatible = "qcom,geni-se-qup";
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reg = <0x0 0x01ac0000 0x0 0x2000>;
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clocks = <&gcc GCC_QUPV3_AHB_MST_CLK>,
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<&gcc GCC_QUPV3_AHB_SLV_CLK>;
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clock-names = "m-ahb", "s-ahb";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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uart1: serial@1a98000 {
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compatible = "qcom,geni-debug-uart";
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reg = <0x0 0x01a98000 0x0 0x4000>;
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clocks = <&gcc GCC_QUPV3_WRAP_SE6_CLK>;
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clock-names = "se";
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interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH 0>;
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status = "disabled";
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};
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};
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sdhc: mmc@7804000 {
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compatible = "qcom,ipq9650-sdhci", "qcom,sdhci-msm-v5";
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reg = <0x0 0x07804000 0x0 0x1000>,
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<0x0 0x07805000 0x0 0x1000>;
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reg-names = "hc",
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"cqhci";
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interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
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interrupt-names = "hc_irq",
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"pwr_irq";
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clocks = <&gcc GCC_SDCC1_AHB_CLK>,
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<&gcc GCC_SDCC1_APPS_CLK>,
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<&xo_board>;
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clock-names = "iface",
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"core",
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"xo";
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non-removable;
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status = "disabled";
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};
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intc: interrupt-controller@f200000 {
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compatible = "arm,gic-v3";
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reg = <0x0 0x0f200000 0x0 0x10000>,
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<0x0 0x0f240000 0x0 0xa0000>;
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#interrupt-cells = <0x4>;
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interrupt-controller;
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#redistributor-regions = <1>;
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redistributor-stride = <0x0 0x20000>;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
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mbi-ranges = <800 160>;
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msi-controller;
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ppi-partitions {
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ppi_cluster0: interrupt-partition-0 {
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affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
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};
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ppi_cluster1: interrupt-partition-1 {
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affinity = <&cpu4>;
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};
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};
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};
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timer@f420000 {
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compatible = "arm,armv7-timer-mem";
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reg = <0x0 0x0f420000 0x0 0x1000>;
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ranges = <0 0 0 0x10000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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frame@f421000 {
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reg = <0x0f421000 0x1000>,
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<0x0f422000 0x1000>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
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frame-number = <0>;
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};
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frame@f423000 {
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reg = <0x0f423000 0x1000>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
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frame-number = <1>;
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status = "disabled";
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};
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frame@f425000 {
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reg = <0x0f425000 0x1000>,
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<0x0f426000 0x1000>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
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frame-number = <2>;
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status = "disabled";
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};
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frame@f427000 {
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reg = <0x0f427000 0x1000>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
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frame-number = <3>;
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status = "disabled";
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};
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frame@f429000 {
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reg = <0x0f429000 0x1000>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
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frame-number = <4>;
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status = "disabled";
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};
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frame@f42b000 {
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reg = <0x0f42b000 0x1000>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH 0>;
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frame-number = <5>;
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status = "disabled";
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};
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frame@f42d000 {
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reg = <0x0f42d000 0x1000>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
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frame-number = <6>;
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status = "disabled";
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};
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>,
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<GIC_PPI 12 IRQ_TYPE_LEVEL_LOW 0>;
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};
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};
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