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Author SHA1 Message Date
Nicolas Frattaroli
1938b585ed arm64: dts: rockchip: Add analog audio on Quartz64 
On the Quartz64 Model A, the I2S1 TDM controller is connected
to the rk817 codec in I2S mode. Enabling it and adding the
necessary simple-sound-card and codec nodes allows for analog
audio output on the PINE64 Quartz64 Model A SBC.

Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
Link: https://lore.kernel.org/r/20211016105354.116513-5-frattaroli.nicolas@gmail.com
[some property sorting]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 2021-10-17 14:35:05 +02:00
Nicolas Frattaroli
ef5c913570 arm64: dts: rockchip: Add i2s1 on rk356x 
This adds the necessary device tree node on rk3566 and rk3568
to enable the I2S1 TDM audio controller.

I2S0 has not been added, as it is connected to HDMI and there is
no way to test that it's working without a functioning video
clock (read: VOP2 driver).

Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
Link: https://lore.kernel.org/r/20211016105354.116513-4-frattaroli.nicolas@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 2021-10-17 14:29:53 +02:00
Johan Jonker
ec3028e7c8 arm64: dts: rockchip: change gpio nodenames 
Currently all gpio nodenames are sort of identical to there label.
Nodenames should be of a generic type, so change them all.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20211007144019.7461-3-jbx6244@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 2021-10-17 09:50:36 +02:00
Arnaud Ferraris
263b39bce2 arm64: dts: rockchip: add 'chassis-type' property 
A new 'chassis-type' root node property has recently been approved for
the device-tree specification, in order to provide a simple way for
userspace to detect the device form factor and adjust their behavior
accordingly.

This patch fills in this property for end-user devices (such as laptops,
smartphones and tablets) based on Rockchip ARM64 processors.

Signed-off-by: Arnaud Ferraris <arnaud.ferraris@collabora.com>
Link: https://lore.kernel.org/r/20211016102025.23346-5-arnaud.ferraris@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 2021-10-16 21:26:48 +02:00
Heiko Stuebner
b394e70cdc arm64: dts: rockchip: add powerdomains to rk3368 
Add the core io-domain node for rk3368.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20210925090405.2601792-3-heiko@sntech.de
 2021-10-16 20:44:41 +02:00
Heiko Stuebner
fff963f4ec dt-bindings: arm: rockchip: add rk3368 compatible string to pmu.yaml 
Add the compatible for the pmu mfd on rk3368.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210925090405.2601792-1-heiko@sntech.de
 2021-10-16 20:44:41 +02:00
Nicolas Frattaroli
7ab91acd36 arm64: dts: rockchip: enable spdif on Quartz64 A 
Add the necessary nodes to enable the spdif output on the
RK3566-Quartz-A board.

Co-developed-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
Link: https://lore.kernel.org/r/20211015111303.1365328-2-frattaroli.nicolas@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 2021-10-16 20:42:50 +02:00
Peter Geis
a65e6523e6 arm64: dts: rockchip: add spdif node to rk356x 
This adds the spdif node to the rk356x device tree.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
Link: https://lore.kernel.org/r/20211015111303.1365328-1-frattaroli.nicolas@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 2021-10-16 20:42:26 +02:00
Liang Chen
98419a39d1 arm64: dts: rockchip: add pwm nodes for rk3568 
Add the pwm controller nodes to the core rk3568 dtsi.

Signed-off-by: Liang Chen <cl@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20210726090355.1548483-2-heiko@sntech.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 2021-09-27 23:45:49 +02:00
Jakob Unterwurzacher
5a73d7ca7f arm64: dts: rockchip: add phandles to muxed i2c buses on rk3368-lion 
Other DTS files that include the dtsi will want to to add children
to the i2c buses from the i2c-mus. Without a label they would have to
specify the full path.

Signed-off-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
[add phandles for first mux as well]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20210922230429.2162535-3-heiko@sntech.de
 2021-09-23 21:44:04 +02:00
Jakob Unterwurzacher
0ed6b51dfd arm64: dts: rockchip: define iodomains for rk3368-lion 
This is not strictly needed, as 3.3V is the default,
but good to have for descriptive purposes nevertheless.

Signed-off-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
[fixed ordering]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20210922230429.2162535-2-heiko@sntech.de
 2021-09-23 21:44:03 +02:00
Jakob Unterwurzacher
3bd7f3ef3b arm64: dts: rockchip: fix LDO_REG4 / LDO_REG7 confusion on rk3368-lion 
LDO_REG7 is used for generating VCC_18.
LDO_REG4 is not connected to anything - delete it.

Signed-off-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20210922230429.2162535-1-heiko@sntech.de
 2021-09-23 21:44:03 +02:00
Krzysztof Kozlowski
a30f3d90e2 arm64: dts: rockchip: align operating-points table name with dtschema 
Align the name of operating-points node to dtschema to fix warnings
like:

  opp-table0: $nodename:0: 'opp-table0' does not match '^opp-table(-[a-z0-9]+)?$'

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Link: https://lore.kernel.org/r/20210819182311.223443-2-krzysztof.kozlowski@canonical.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 2021-09-20 15:25:12 +02:00
Heiko Stuebner
474a77395b arm64: dts: rockchip: hook up camera on px30-evb 
Enable the isp and csi phy on px30-evb and connect it to the board's
ov5695 camera.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Link: https://lore.kernel.org/r/20210830141318.66744-2-heiko@sntech.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 2021-09-20 15:16:34 +02:00
Heiko Stuebner
8df7b4537d arm64: dts: rockchip: add isp node for px30 
Add the rkisp1 node and iommu for the px30 soc.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Link: https://lore.kernel.org/r/20210830141318.66744-1-heiko@sntech.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 2021-09-20 15:16:34 +02:00
Brian Norris
75dccea503 arm64: dts: rockchip: add Coresight debug range for RK3399 
Per Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt.

This IP block can be used for sampling the PC of any given CPU, which is
useful in certain panic scenarios where you can't get the CPU to stop
cleanly (e.g., hard lockup).

Reviewed-by: Leo Yan <leo.yan@linaro.org>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Brian Norris <briannorris@chromium.org>
Link: https://lore.kernel.org/r/20210908111337.v2.3.Ibc87b4785709543c998cc852c1edaeb7a08edf5c@changeid
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 2021-09-20 15:13:24 +02:00
Chris Morgan
4b90e34d9a arm64: dts: rockchip: Correct regulator for USB host on Odroid-Go2 
When writing a battery driver, I noticed that the USB voltage was ~3.7V
while running off of battery on a mainline kernel. After consulting the
schematics for the Odroid Go Advance, it appears that the BOOST
regulator is involved in the process of powering the USB host. Power
for the USB host goes from the vccsys regulator into the PMIC, then out
from the PMIC BOOST regulator into the FC9516A (which is controlled by
GPIO), which then feeds power into the USB host. I named the regulator
usb_midu because on the datasheet the pin is described as "MIDU/BOOST -
middle point of USB power supply / boost output". Making these changes
solved the USB power issue on battery and I'm now reading approximately
5v.

Note that on my board at least there is a difference in time from the
USB PHY probing and the regulators being powered on. This causes the
USB port to be undervolted for a few seconds during boot up. The
solutions to this problem are either 1) to add the proper phy-supply
on the host port, or to 2) add regulator-boot-on to the regulator. I
chose to add regulator-boot-on because there is an issue with the phy
clk that causes a warning when booting (see v1 of this patch series).
Basically the clock usb480m is a child of the usb480m_phy clock (used
by the USB PHY) and also a critical clock. Setting the phy-supply
causes this driver to be EPROBE_DEFERed until the regulator is ready,
however upon unregistering the driver to be probed later the system
cannot remove the usb480m_phy clock due to a child being marked
critical.

Changes since v2:
 - Added notes about clk problem and regulator voltage at boot.
 - Added regulator-boot-on as a workaround for the voltage at boot.
 - Removed note about fixed regulator warning, as that has been
   fixed upstream.

Changes since v1:
 - Removed phy-supply, as this generated a warning in dmesg.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Link: https://lore.kernel.org/r/20210916190938.6175-1-macroalpha82@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 2021-09-20 15:07:22 +02:00
Tommaso Merciai
d146198a85 arm64: dts: rockchip: fix PCI reg address warning on rk3399-gru 
Warning (pci_device_reg): /pcie@f8000000/pcie@0,0:reg: PCI reg address is not configuration space

Signed-off-by: Tommaso Merciai <tomm.merciai@gmail.com>
Link: https://lore.kernel.org/r/20210918164153.207146-1-tomm.merciai@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 2021-09-20 15:05:39 +02:00
Michael Riesch
cf1944727c arm64: dts: rockchip: add saradc to rk3568-evb1-v10 
Add the SARADC to the device tree of the RK3568 EVB1.

Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
Link: https://lore.kernel.org/r/20210823110716.10038-1-michael.riesch@wolfvision.net
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 2021-09-15 17:50:45 +02:00
Alex Bee
932b4610f5 arm64: dts: rockchip: Fix GPU register width for RK3328 
As can be seen in RK3328's TRM the register range for the GPU is
0xff300000 to 0xff330000.
It would (and does in vendor kernel) overlap with the registers of
the HEVC encoder (node/driver do not exist yet in upstream kernel).
See already existing h265e_mmu node.

Fixes: 752fbc0c8d ("arm64: dts: rockchip: add rk3328 mali gpu node")
Signed-off-by: Alex Bee <knaerzche@gmail.com>
Link: https://lore.kernel.org/r/20210623115926.164861-1-knaerzche@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 2021-09-15 17:50:45 +02:00
Alex Bee
87543bb603 arm64: dts: rockchip: Re-add interrupt-names for RK3399's vpu 
Commit 53a05c8f6e8e ("arm64: dts: rockchip: remove interrupt-names from iommu nodes")
intended to remove the interrupt-names property for mmu nodes, but it
also removed it for the vpu node in rk3399.dtsi. That makes the driver
fail probing currently.
Fix this by re-adding the property for this node.

Fixes: 53a05c8f6e8e ("arm64: dts: rockchip: remove interrupt-names from iommu nodes")
Signed-off-by: Alex Bee <knaerzche@gmail.com>
Link: https://lore.kernel.org/r/20210822115755.3171937-1-knaerzche@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 2021-09-15 17:50:44 +02:00
Michael Riesch
95ad4dbe5f arm64: dts: rockchip: add missing rockchip,grf property to rk356x 
This commit fixes the error messages

  rockchip_clk_register_muxgrf: regmap not available
  rockchip_clk_register_branches: failed to register clock clk_ddr1x: -524

during boot by providing the missing rockchip,grf property.

Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
Tested-by: Peter Geis <pgwipeout@gmail.com>
Link: https://lore.kernel.org/r/20210823123911.12095-2-michael.riesch@wolfvision.net
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 2021-09-15 17:50:44 +02:00
Brian Norris
ae04430959 arm64: dts: rockchip: add RK3399 Gru gpio-line-names 
It's convenient to get nice names for GPIOs. In particular, Chrome OS
tooling looks for "AP_FLASH_WP" and "AP_FLASH_WP_L". The rest are
provided for convenience.

Gru-Bob and Gru-Kevin share the gru-chromebook.dtsi, and for the most
part they share pin meanings. I omitted a few areas where components
were available only on one or the other.

Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20210820133829.1.Ica46f428de8c3beb600760dbcd63cf879ec24baf@changeid
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 2021-09-15 17:50:43 +02:00
Chris Morgan
e31083f918 arm64: dts: rockchip: Enable SFC for Odroid Go Advance 
This enables the Rockchip Serial Flash Controller for the Odroid Go
Advance. Note that while the attached SPI NOR flash and the controller
both support quad read mode, only 2 of the required 4 pins are present.
The rx bus width is set to 2 for this reason, and tx bus width is set
to 1 for compatibility reasons.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Link: https://lore.kernel.org/r/20210812134639.31586-2-jon.lin@rock-chips.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 2021-09-15 17:50:42 +02:00
Chris Morgan
e2c58ea861 arm64: dts: rockchip: Add SFC to RK3308 
Add a devicetree entry for the Rockchip SFC for the RK3308 SOC.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Link: https://lore.kernel.org/r/20210812134639.31586-1-jon.lin@rock-chips.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 2021-09-15 17:50:41 +02:00
Chris Morgan
4d97b78aec arm64: dts: rockchip: Add SFC to PX30 
Add a devicetree entry for the Rockchip SFC for the PX30 SOC.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Link: https://lore.kernel.org/r/20210812134546.31340-4-jon.lin@rock-chips.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 2021-09-15 17:50:41 +02:00
Peter Geis
40b0bfbb95 arm64: dts: rockchip: add thermal support to Quartz64 Model A 
Add the thermal nodes for the Quartz64 Model A.
The Model A supports a single speed gpio fan.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Link: https://lore.kernel.org/r/20210728180034.717953-9-pgwipeout@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 2021-09-15 17:50:40 +02:00
Peter Geis
1330875dc2 arm64: dts: rockchip: add rk3568 tsadc nodes 
Add the thermal and tsadc nodes to the rk3568 device tree.
There are two sensors, one for the cpu, one for the gpu.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Link: https://lore.kernel.org/r/20210728180034.717953-6-pgwipeout@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 2021-09-15 17:50:40 +02:00
Peter Geis
3d9170c3ea arm64: dts: rockchip: add rk356x gpio debounce clocks 
The rk356x added a debounce clock to the gpio devices. This clock is
necessary for the new v2 gpio driver to bind.
Add the clocks to the rk356x device tree.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Link: https://lore.kernel.org/r/20210728180034.717953-4-pgwipeout@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 2021-09-15 17:50:39 +02:00
Michael Riesch
8a599b56a8 arm64: dts: rockchip: add pinctrl and alias to emmc node to rk3568-evb1-v10 
Since the EMMC pins can be used for other functions as well, we need to
configure the pinctrl.

Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
Link: https://lore.kernel.org/r/20210805120107.27007-8-michael.riesch@wolfvision.net
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 2021-09-15 17:50:38 +02:00
Michael Riesch
2a068e19ff arm64: dts: rockchip: add node for sd card to rk3568-evb1-v10 
Add the SD card reader to the device tree of the RK3568 EVB1.

Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
Link: https://lore.kernel.org/r/20210805120107.27007-7-michael.riesch@wolfvision.net
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 2021-09-15 17:50:38 +02:00
Michael Riesch
14f1c34eec arm64: dts: rockchip: add regulators of rk809 pmic to rk3568-evb1-v10 
Add the regulators of the RK809 PMIC to the device tree of the
RK3568 EVB1.

Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
Link: https://lore.kernel.org/r/20210805120107.27007-6-michael.riesch@wolfvision.net
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 2021-09-15 17:50:37 +02:00
Michael Riesch
e86d481098 arm64: dts: rockchip: enable io domains on rk3568-evb1-v10 
Enable the PMU IO domains in the device tree for the RK3568 EVB1.

Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
Link: https://lore.kernel.org/r/20210805120107.27007-5-michael.riesch@wolfvision.net
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 2021-09-15 17:50:36 +02:00
Michael Riesch
2dbcb2514c arm64: dts: rockchip: add core io domains node for rk356x 
Enable the PMU IO domains for the RK3566 and the RK3568.

Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
Link: https://lore.kernel.org/r/20210805120107.27007-4-michael.riesch@wolfvision.net
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 2021-09-15 17:50:36 +02:00
Peter Geis
d09ebc6ba9 arm64: dts: rockchip: add thermal fan control to rockpro64 
The rockpro64 had a fan node since
commit 5882d65c16 ("arm64: dts: rockchip: Add PWM fan for RockPro64")
however it was never tied into the thermal driver for automatic control.

Add the links to the thermal node to permit the kernel to handle this
automatically.
Borrowed from the (rk3399-khadas-edge.dtsi).

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Link: https://lore.kernel.org/r/20210730151727.729822-1-pgwipeout@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 2021-09-15 17:50:35 +02:00
Dan Johansen
ef914fb8f7 arm64: dts: rockchip: Setup USB typec port as datarole on for Pinebook Pro 
Some chargers try to put the charged device into device data
role. Before this commit this condition caused the tcpm state machine to
issue a hard reset due to a capability missmatch.

Signed-off-by: Dan Johansen <strit@manjaro.org>
Link: https://lore.kernel.org/r/20210805220426.2693062-1-strit@manjaro.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 2021-09-15 17:50:34 +02:00
Chen-Yu Tsai
5707e34166 arm64: dts: rockchip: Add gru-scarlet-dumo board 
Dumo is another variant of Scarlet, also known as the ASUS Chromebook
Tablet CT100. This is almost the same as Scarlet-Innolux, but uses a
board-specific calibration variant for the WiFi module.

Add a new device tree for it.

Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20210812094753.2359087-3-wenst@chromium.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 2021-09-15 17:50:34 +02:00
Chen-Yu Tsai
3cf697b45e dt-bindings: arm: rockchip: Add gru-scarlet-dumo board 
Dumo is another variant of Scarlet, also known as the ASUS Chromebook
Tablet CT100. This is almost the same as Scarlet-Innolux, but uses a
specific calibration variant for the WiFi module.

Add an entry for the board compatibles.

Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20210812094753.2359087-2-wenst@chromium.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 2021-09-15 17:50:33 +02:00
Michael Riesch
fc57d78344 arm64: dts: rockchip: rk3568-evb1-v10: add ethernet support 
Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
Link: https://lore.kernel.org/r/20210729093913.8917-3-michael.riesch@wolfvision.net
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 2021-09-15 17:50:32 +02:00
Michael Riesch
b8d41e5053 arm64: dts: rockchip: add gmac0 node to rk3568 
While both RK3566 and RK3568 feature the gmac1 node, the gmac0
node is exclusive to the RK3568.

Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
Link: https://lore.kernel.org/r/20210729093913.8917-2-michael.riesch@wolfvision.net
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 2021-09-15 17:50:32 +02:00
Peter Geis
c3dd497fbb arm64: dts: rockchip: enable gmac node on quartz64-a 
Enable the gmac controller on the Pine64 Quartz64 Model A.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Link: https://lore.kernel.org/r/20210728180034.717953-8-pgwipeout@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 2021-09-15 17:50:31 +02:00
Peter Geis
f7c5b9c2a1 arm64: dts: rockchip: adjust rk3568 pll clocks 
The rk3568 gpll should run at 1200mhz and the ppll should run at 200mhz.
These are set incorrectly by the bootloader, so fix them here.

gpll boots at 1188mhz, but to get most accurate dividers for all
gpll_dividers it needs to run at 1200mhz, otherwise everyone downstream
isn't quite right.

ppll feeds the combophys, which has a divide by 2 clock, so 200mhz is
required to reach a 100mhz clock input for them.

The vendor-kernel also makes this fix.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
[pulled deeper explanation from discussion into commit message]
Link: https://lore.kernel.org/r/20210728180034.717953-7-pgwipeout@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 2021-09-15 17:50:30 +02:00
Peter Geis
0dcec571ce arm64: dts: rockchip: add rk356x gmac1 node 
Add the gmac1 controller to the rk356x device tree.
This is the controller common to both the rk3568 and rk3566.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Link: https://lore.kernel.org/r/20210728180034.717953-5-pgwipeout@gmail.com
[adjusted sorting a bit]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 2021-09-15 17:50:30 +02:00
Peter Geis
b6c1a59014 arm64: dts: rockchip: fix rk3568 mbi-alias 
The mbi-alias incorrectly points to 0xfd100000 when it should point to
0xfd410000.
This fixes MSIs on rk3568.

Fixes: a3adc0b907 ("arm64: dts: rockchip: add core dtsi for RK3568 SoC")
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Link: https://lore.kernel.org/r/20210728180034.717953-2-pgwipeout@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 2021-09-15 17:50:29 +02:00
Paul Kocialkowski
6b4b2af5d2 arm64: dts: rockchip: Add VPU support for the PX30 
The PX30 has a VPU (both decoder and encoder) with a dedicated IOMMU.
Describe these two entities in device-tree.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
Link: https://lore.kernel.org/r/20210728230040.17368-1-ezequiel@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 2021-09-15 17:50:28 +02:00
Liang Chen
0edcfec3fa arm64: dts: rockchip: add watchdog to rk3568 
Add the watchdog node to rk3568.

Signed-off-by: Liang Chen <cl@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20210622102907.99242-2-heiko@sntech.de
 2021-09-15 17:50:28 +02:00
Heiko Stuebner
c349ae3817 arm64: dts: rockchip: add isp1 node on rk3399 
ISP1 is supplied by the tx1rx1 dphy, that is controlled from
inside the dsi1 controller, so include the necessary phy-link
for it.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Tested-by: Sebastian Fricke <sebastian.fricke@posteo.net>
Acked-by: Helen Koike <helen.koike@collabora.com>
Link: https://lore.kernel.org/r/20210210111020.2476369-7-heiko@sntech.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 2021-09-15 17:50:27 +02:00
Heiko Stuebner
f1400702ad arm64: dts: rockchip: add cif clk-control pinctrl for rk3399 
This enables variant a of the clkout signal for camera applications
and also the cifclkin pinctrl setting.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Tested-by: Sebastian Fricke <sebastian.fricke@posteo.net>
Acked-by: Helen Koike <helen.koike@collabora.com>
Link: https://lore.kernel.org/r/20210210111020.2476369-6-heiko@sntech.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 2021-09-15 17:50:26 +02:00
Heiko Stuebner
8d47d12e3b arm64: dts: rockchip: add #phy-cells to mipi-dsi1 on rk3399 
The dsi controller includes access to the dphy which might be used
not only for dsi output but also for csi input on dsi1, so add the
necessary #phy-cells to allow it to be used as phy.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Tested-by: Sebastian Fricke <sebastian.fricke@posteo.net>
Acked-by: Helen Koike <helen.koike@collabora.com>
Link: https://lore.kernel.org/r/20210210111020.2476369-5-heiko@sntech.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 2021-09-15 17:50:26 +02:00
Peter Geis
b33a22a1e7 arm64: dts: rockchip: add basic dts for Pine64 Quartz64-A 
Add a basic dts for the Pine64 Quartz64 Model A Single Board Computer.
This board outputs on uart2 for debug.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210710151034.32857-5-pgwipeout@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 2021-09-15 17:50:25 +02:00