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Author SHA1 Message Date
Bhupesh Sharma
eaa53a8574 arm64: dts: qcom: qrb4210-rb2: Enable USB node 
Enable the USB controller and HS/SS PHYs on qrb4210-rb2 board.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230516150511.2346357-5-bhupesh.sharma@linaro.org
 2023-05-29 10:50:45 -07:00
Bhupesh Sharma
9dd5f6dba7 arm64: dts: qcom: sm6115: Add USB SS qmp phy node 
Add USB superspeed qmp phy node to dtsi.

Make sure that the various board dts files (which include sm4250.dtsi file)
continue to work as intended.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230516150511.2346357-4-bhupesh.sharma@linaro.org
 2023-05-29 10:50:45 -07:00
Kathiravan T
a782318023 arm64: dts: qcom: ipq5332: add support for the RDP442 variant 
Add the initial device tree support for the Reference Design
Platform(RDP) 442 based on IPQ5332 family of SoC. This patch carries
the support for Console UART, SPI NOR, eMMC and I2C.

Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230509160133.3794-3-quic_kathirav@quicinc.com
 2023-05-27 07:41:49 -07:00
Kathiravan T
68c4c67156 dt-bindings: arm: qcom: document MI01.3 board based on IPQ5332 family 
Document the MI01.3 (Reference Design Platform 442) board based on IPQ5332
family of SoCs.

Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230509160133.3794-2-quic_kathirav@quicinc.com
 2023-05-27 07:41:49 -07:00
Jagadeesh Kona
9f7579423d arm64: dts: qcom: sm8550: Add graphics clock controller 
Add device node for graphics clock controller on Qualcomm
SM8550 platform.

Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230524181800.28717-4-quic_jkona@quicinc.com
 2023-05-26 20:55:18 -07:00
Bjorn Andersson
8368050625 Merge branch 'sm8450-sm8550-gpucc-binding' into arm64-for-6.5 
Introduce DeviceTree bindings for SM8450 and SM8550 GPU clock
controller, to introduce the constants necessary to referr to these
clocks.
 2023-05-26 18:27:58 -07:00
Jagadeesh Kona
778af143ad dt-bindings: clock: qcom: Add SM8550 graphics clock controller 
Add device tree bindings for the graphics clock controller on
Qualcomm SM8550 platform.

Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230524181800.28717-2-quic_jkona@quicinc.com
 2023-05-26 18:22:07 -07:00
Konrad Dybcio
63f4e4b6f5 dt-bindings: clock: Add Qcom SM8450 GPUCC 
Add device tree bindings for the graphics clock controller on Qualcomm
Technology Inc's SM8450 SoCs.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230517-topic-waipio-gpucc-v1-1-4f40e282af1d@linaro.org
 2023-05-26 18:22:04 -07:00
Shazad Hussain
a1f6bef213 arm64: dts: qcom: sa8775p-ride: enable i2c11 
This enables the i2c11 node on sa8775p-ride board for A2B controller
and audio port expander.

Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230526133122.16443-6-quic_shazhuss@quicinc.com
 2023-05-26 18:12:26 -07:00
Shazad Hussain
445a523d46 arm64: dts: qcom: sa8775p: add uart5 and uart9 nodes 
Add remaining uart5 and uart9 nodes for UART bus present on sa8775p
SoC.

Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230526133122.16443-5-quic_shazhuss@quicinc.com
 2023-05-26 18:12:26 -07:00
Shazad Hussain
1b2d7ad5ac arm64: dts: qcom: sa8775p: add missing spi nodes 
Add the missing nodes of the SPI buses present on sa8775p platform.

Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230526133122.16443-4-quic_shazhuss@quicinc.com
 2023-05-26 18:12:26 -07:00
Shazad Hussain
ee2f5f906d arm64: dts: qcom: sa8775p: add missing i2c nodes 
Add the missing nodes for the i2c buses present on sa8775p Soc.

Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230526133122.16443-3-quic_shazhuss@quicinc.com
 2023-05-26 18:12:26 -07:00
Shazad Hussain
07e3e17205 arm64: dts: qcom: sa8775p: add the QUPv3 #0 and #3 node 
Add zeroth and third instance of the QUPv3 engine to the sa8775p.dtsi.

Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230526133122.16443-2-quic_shazhuss@quicinc.com
 2023-05-26 18:12:26 -07:00
Krzysztof Kozlowski
c77612a07d arm64: dts: qcom: apq8096: fix fixed regulator name property 
Correct the typo in 'regulator-name' property.

  apq8096-ifc6640.dtb: v1p05-regulator: 'regulator-name' is a required property
  apq8096-ifc6640.dtb: v1p05-regulator: Unevaluated properties are not allowed ('reglator-name' was unexpected)

Fixes: 6cbdec2d3c ("arm64: dts: qcom: msm8996: Introduce IFC6640")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230507174516.264936-3-krzysztof.kozlowski@linaro.org
 2023-05-26 13:39:48 -07:00
Krzysztof Kozlowski
3e8188b4b6 arm64: dts: qcom: msm8996: correct MMCC clocks order 
Re-order the clocks for MMCC clock controller node to match the bindings (Linux
driver takes by name):

  msm8996-mtp.dtb: clock-controller@8c0000: clock-names:1: 'gpll0' was expected
  msm8996-mtp.dtb: clock-controller@8c0000: clock-names:2: 'gcc_mmss_noc_cfg_ahb_clk' was expected

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230507174516.264936-2-krzysztof.kozlowski@linaro.org
 2023-05-26 13:39:48 -07:00
Krzysztof Kozlowski
9903258a93 arm64: dts: qcom: msm8916: correct LPASS CPU clocks order 
Re-order the clocks for LPASS CPU node to match the bindings (Linux
driver takes by name):

  msm8916-asus-z00l.dtb: audio-controller@7708000: clock-names:1: 'mi2s-bit-clk0' was expected
  msm8916-asus-z00l.dtb: audio-controller@7708000: clock-names:2: 'mi2s-bit-clk1' was expected
  msm8916-asus-z00l.dtb: audio-controller@7708000: clock-names:3: 'mi2s-bit-clk2' was expected
  msm8916-asus-z00l.dtb: audio-controller@7708000: clock-names:4: 'mi2s-bit-clk3' was expected
  msm8916-asus-z00l.dtb: audio-controller@7708000: clock-names:5: 'pcnoc-mport-clk' was expected
  msm8916-asus-z00l.dtb: audio-controller@7708000: clock-names:6: 'pcnoc-sway-clk' was expected

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230507174516.264936-1-krzysztof.kozlowski@linaro.org
 2023-05-26 13:39:48 -07:00
Vijaya Krishna Nivarthi
0aa2811cf5 arm64: dts: qcom: sdm845: Add stream-id of qspi to iommus 
As part of DMA mode support to qspi driver.

Signed-off-by: Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/1682328761-17517-5-git-send-email-quic_vnivarth@quicinc.com
 2023-05-26 13:35:58 -07:00
Vijaya Krishna Nivarthi
cc40600612 arm64: dts: qcom: sc7280: Add stream-id of qspi to iommus 
As part of DMA mode support to qspi driver.

Signed-off-by: Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/1682328761-17517-4-git-send-email-quic_vnivarth@quicinc.com
 2023-05-26 13:35:58 -07:00
Vijaya Krishna Nivarthi
8164116023 arm64: dts: qcom: sc7180: Add stream-id of qspi to iommus 
As part of DMA mode support to qspi driver.

Signed-off-by: Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/1682328761-17517-3-git-send-email-quic_vnivarth@quicinc.com
 2023-05-26 13:35:58 -07:00
Krzysztof Kozlowski
24cf51a2e4 arm64: dts: qcom: msm8996: correct /soc/bus ranges 
The bus@0 node should have reg or ranges to fix dtbs W=1 warnings:

  Warning (unit_address_vs_reg): /soc@0/bus@0: node has a unit name, but no reg or ranges property
  Warning (simple_bus_reg): /soc@0/bus@0: missing or empty reg/ranges property

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Tested-by: Konrad Dybcio <konrad.dybcio@linaro.org> # MSM8996 Kagura
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230420180746.860934-1-krzysztof.kozlowski@linaro.org
 2023-05-26 13:35:10 -07:00
Krzysztof Kozlowski
5b85de0d51 arm64: dts: qcom: sdm630-nile: correct duplicated reserved memory node 
SoC DTSI already comes with 85800000 reserved memory node, so assume the
author wanted to update its length.  This fixes dtbs W=1 warning:

  Warning (unique_unit_address_if_enabled): /reserved-memory/qhee-code@85800000: duplicate unit-address (also used in node /reserved-memory/reserved@85800000)

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230419211921.79871-1-krzysztof.kozlowski@linaro.org
 2023-05-26 13:34:03 -07:00
Krzysztof Kozlowski
a2d8dcd48e arm64: dts: qcom: sm6125-sprout: align ADC channel node names with bindings 
Bindings expect ADC channel node names to follow specific pattern:

  sm6125-xiaomi-laurel-sprout.dtb: adc@3100: 'adc-chan@4d', 'adc-chan@4e', 'adc-chan@52', 'adc-chan@54' do not match any of the regexes: ...

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230416123730.300863-6-krzysztof.kozlowski@linaro.org
 2023-05-26 13:29:08 -07:00
Krzysztof Kozlowski
ec888e6cff arm64: dts: qcom: sm8550-qrd: add missing PCIE1 PHY AUX clock frequency 
The SM8550 DTSI defines a fixed PCIE1 PHY AUX clock and expects boards
to define frequency.  Use the same as in MTP8550 to fix:

  sm8550-qrd.dtb: pcie-1-phy-aux-clk: 'clock-frequency' is a required property

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230416123730.300863-5-krzysztof.kozlowski@linaro.org
 2023-05-26 13:29:08 -07:00
Krzysztof Kozlowski
2438aba45f arm64: dts: qcom: sm8250: add missing qcom,smmu-500 fallback 
Since commit 6c84bbd103 ("dt-bindings: arm-smmu: Add generic
qcom,smmu-500 bindings") the SMMU is supposed to use qcom,smmu-500
compatible fallback:

  ['qcom,sm8250-smmu-500', 'qcom,adreno-smmu', 'qcom,smmu-500', 'arm,mmu-500'] is too long
  'qcom,sm8250-smmu-500' is not one of ['qcom,msm8996-smmu-v2', 'qcom,msm8998-smmu-v2', 'qcom,sdm630-smmu-v2']
  'qcom,sm8250-smmu-500' is not one of ['qcom,msm8996-smmu-v2', 'qcom,sc7180-smmu-v2', 'qcom,sdm630-smmu-v2', 'qcom,sdm845-smmu-v2'

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230416123730.300863-4-krzysztof.kozlowski@linaro.org
 2023-05-26 13:26:28 -07:00
Krzysztof Kozlowski
395aba1b19 arm64: dts: qcom: qdu1000: add missing qcom,smmu-500 fallback 
Since commit 6c84bbd103 ("dt-bindings: arm-smmu: Add generic
qcom,smmu-500 bindings") the SMMU is supposed to use qcom,smmu-500
compatible fallback:

  ['qcom,qdu1000-smmu-500', 'arm,mmu-500'] is too short
  ['qcom,qdu1000-smmu-500', 'arm,mmu-500'] is too long

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230416123730.300863-3-krzysztof.kozlowski@linaro.org
 2023-05-26 13:26:28 -07:00
Krzysztof Kozlowski
e6e0e70694 arm64: dts: qcom: ipq8074: drop incorrect SPI bus spi-max-frequency 
The spi-max-frequency property belongs to SPI devices, not SPI
controller:

  ipq8074-hk01.dtb: spi@78b5000: Unevaluated properties are not allowed ('spi-max-frequency' was unexpected)

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230416123730.300863-2-krzysztof.kozlowski@linaro.org
 2023-05-26 13:26:28 -07:00
Krzysztof Kozlowski
b8420d478a arm64: dts: qcom: ipq6018: drop incorrect SPI bus spi-max-frequency 
The spi-max-frequency property belongs to SPI devices, not SPI
controller:

  ipq6018-cp01-c1.dtb: spi@78b5000: Unevaluated properties are not allowed ('spi-max-frequency' was unexpected)

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230416123730.300863-1-krzysztof.kozlowski@linaro.org
 2023-05-26 13:26:28 -07:00
Vignesh Viswanathan
0cd4e90cb2 arm64: dts: qcom: add few more reserved memory region 
In IPQ SoCs, bootloader will collect the system RAM contents upon crash
for the post morterm analysis. If we don't reserve the memory region used
by bootloader, obviously linux will consume it and upon next boot on
crash, bootloader will be loaded in the same region, which will lead to
loose some of the data, sometimes we may miss out critical information.
So lets reserve the region used by the bootloader.

Similarly SBL copies some data into the reserved region and it will be
used in the crash scenario. So reserve 1MB for SBL as well.

While at it, drop the size padding in the reserved memory region,
wherever applicable.

Signed-off-by: Vignesh Viswanathan <quic_viswanat@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230526110653.27777-4-quic_viswanat@quicinc.com
 2023-05-26 13:12:53 -07:00
Vignesh Viswanathan
9b2406aaba arm64: dts: qcom: enable the download mode support 
Like any other Qualcomm SoCs, IPQ8074 and IPQ6018 also supports the
download mode to collect the RAM dumps if system crashes, to perform
the post mortem analysis. Add support for the same.

Signed-off-by: Vignesh Viswanathan <quic_viswanat@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230526110653.27777-3-quic_viswanat@quicinc.com
 2023-05-26 13:12:53 -07:00
Neil Armstrong
b92b0d2f75 arm64: dts: qcom: sm8450: add crypto nodes 
Add crypto engine (CE) and CE BAM related nodes and definitions
for the SM8450 SoC.

Tested-by: Anders Roxell <anders.roxell@linaro.org>
Tested-by: Linux Kernel Functional Testing <lkft@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
[Bhupesh: Corrected the compatible list]
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230526192210.3146896-12-bhupesh.sharma@linaro.org
 2023-05-26 13:01:57 -07:00
Bhupesh Sharma
f1040a7fe8 arm64: dts: qcom: sm8350: Add Crypto Engine support 
Add crypto engine (CE) and CE BAM related nodes and definitions to
'sm8350.dtsi'.

Co-developed-by and Signed-off-by: Robert Foss <rfoss@kernel.org>
[Bhupesh: Switch to '#interconnect-cells = <2>', available since commit 4f287e31ff]

Tested-by: Anders Roxell <anders.roxell@linaro.org>
Tested-by: Linux Kernel Functional Testing <lkft@linaro.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230526192210.3146896-11-bhupesh.sharma@linaro.org
 2023-05-26 13:01:57 -07:00
Bhupesh Sharma
c58be6c87f arm64: dts: qcom: sm8250: Add Crypto Engine support 
Add crypto engine (CE) and CE BAM related nodes and definitions to
'sm8250.dtsi'.

Co-developed-by and Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>

Tested-by: Anders Roxell <anders.roxell@linaro.org>
Tested-by: Linux Kernel Functional Testing <lkft@linaro.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230526192210.3146896-10-bhupesh.sharma@linaro.org
 2023-05-26 13:01:57 -07:00
Bhupesh Sharma
f7f485f3dc arm64: dts: qcom: sm8150: Add Crypto Engine support 
Add crypto engine (CE) and CE BAM related nodes and definitions to
'sm8150.dtsi'.

Tested-by: Anders Roxell <anders.roxell@linaro.org>
Tested-by: Linux Kernel Functional Testing <lkft@linaro.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230526192210.3146896-9-bhupesh.sharma@linaro.org
 2023-05-26 13:01:57 -07:00
Bhupesh Sharma
61baef687d arm64: dts: qcom: sm6115: Add Crypto Engine support 
Add crypto engine (CE) and CE BAM related nodes and definitions to
'sm6115.dtsi'.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Anders Roxell <anders.roxell@linaro.org>
Tested-by: Linux Kernel Functional Testing <lkft@linaro.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230526192210.3146896-8-bhupesh.sharma@linaro.org
 2023-05-26 13:01:57 -07:00
Bhupesh Sharma
20bf3ac438 arm64: dts: qcom: sdm845: Fix the slimbam DMA engine compatible string 
As per documentation, Qualcomm SDM845 SoC supports SLIMBAM DMA
engine v1.7.4, so use the correct compatible strings.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Anders Roxell <anders.roxell@linaro.org>
Tested-by: Linux Kernel Functional Testing <lkft@linaro.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230526192210.3146896-5-bhupesh.sharma@linaro.org
 2023-05-26 13:01:57 -07:00
Bhupesh Sharma
31dfb8014f arm64: dts: qcom: sdm8550: Fix the BAM DMA engine compatible string 
As per documentation, Qualcomm SM8550 SoC supports BAM DMA
engine v1.7.4, so use the correct compatible strings.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Anders Roxell <anders.roxell@linaro.org>
Tested-by: Linux Kernel Functional Testing <lkft@linaro.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230526192210.3146896-4-bhupesh.sharma@linaro.org
 2023-05-26 13:01:57 -07:00
Kathiravan T
05e6b82f39 arm64: dts: qcom: ipq9574: add QFPROM node 
IPQ9574 has efuse region to determine the various HW quirks. Lets
add the initial support and the individual fuses will be added as they
are required.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230526125305.19626-5-quic_kathirav@quicinc.com
 2023-05-26 12:45:38 -07:00
Kathiravan T
546f0617a2 arm64: dts: qcom: ipq6018: add QFPROM node 
IPQ6018 has efuse region to determine the various HW quirks. Lets
add the initial support and the individual fuses will be added as they
are required.

Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230526125305.19626-4-quic_kathirav@quicinc.com
 2023-05-26 12:45:10 -07:00
Kathiravan T
2f34a2aa4c arm64: dts: qcom: ipq5332: add QFPROM node 
IPQ5332 has efuse region to determine the various HW quirks. Lets
add the initial support and the individual fuses will be added as they
are required.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230526125305.19626-3-quic_kathirav@quicinc.com
 2023-05-26 12:44:28 -07:00
Kathiravan T
8fa13a6e61 dt-bindings: nvmem: qfprom: add compatible for few IPQ SoCs 
Add the QFPROM compatible for IPQ5332, IPQ6018 and IPQ9574

Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230526125305.19626-2-quic_kathirav@quicinc.com
 2023-05-26 12:44:28 -07:00
Devi Priya
8a465494d6 arm64: dts: qcom: ipq9574: add support for RDP453 variant 
Add the initial device tree support for the Reference Design Platform (RDP)
453 based on IPQ9574 family of SoCs. This patch adds support for Console
UART, SPI NOR and SMPA1 regulator node.

Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230526153152.777-3-quic_devipriy@quicinc.com
 2023-05-26 12:33:13 -07:00
Devi Priya
b866fba436 dt-bindings: arm: qcom: document AL02-C8 board based on IPQ9574 family 
Document AL02-C8 (Reference Design Platform 453) board based on IPQ9574
family of SoCs.

Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230526153152.777-2-quic_devipriy@quicinc.com
 2023-05-26 12:32:34 -07:00
Devi Priya
aa261f13da arm64: dts: qcom: ipq9574: add support for RDP449 variant 
Add the initial device tree support for the Reference Design Platform (RDP)
449 based on IPQ9574 family of SoCs. This patch adds support for Console
UART, SPI NOR and SMPA1 regulator node.

Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230516135013.3547-3-quic_devipriy@quicinc.com
 2023-05-26 12:28:19 -07:00
Devi Priya
2e4cd263b9 dt-bindings: arm: qcom: document AL02-C6 board based on IPQ9574 family 
Document AL02-C6 (Reference Design Platform 449) board based on IPQ9574
family of SoCs.

Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230516135013.3547-2-quic_devipriy@quicinc.com
 2023-05-26 12:28:19 -07:00
Devi Priya
d8a83f8d2e arm64: dts: qcom: ipq9574: add support for RDP418 variant 
Add the initial device tree support for the Reference Design Platform (RDP)
418 based on IPQ9574 family of SoCs. This patch adds support for Console
UART, SPI NOR, eMMC and SMPA1 regulator node.

Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230510104359.16678-3-quic_devipriy@quicinc.com
 2023-05-26 12:28:11 -07:00
Devi Priya
e3c98aac28 dt-bindings: arm: qcom: document AL02-C2 board based on IPQ9574 family 
Document AL02-C2 (Reference Design Platform 418) board based on IPQ9574
family of SoCs.

Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230510104359.16678-2-quic_devipriy@quicinc.com
 2023-05-26 12:28:11 -07:00
Devi Priya
8f0ae6bc00 arm64: dts: qcom: ipq9574: Add cpufreq support 
Add cpu freq nodes in the device tree to bump cpu frequency above 800MHz.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Co-developed-by: Praveenkumar I <quic_ipkumar@quicinc.com>
Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230517172527.1968-4-quic_devipriy@quicinc.com
 2023-05-26 12:26:13 -07:00
Devi Priya
56ba2b3aeb arm64: dts: qcom: ipq9574: Add SMPA1 regulator node 
Add support for SMPA1 regulator node in IPQ9574.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Co-developed-by: Praveenkumar I <quic_ipkumar@quicinc.com>
Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230517172527.1968-3-quic_devipriy@quicinc.com
 2023-05-26 12:26:13 -07:00
Devi Priya
8cc864a437 arm64: dts: qcom: ipq9574: Add RPM related nodes 
Add RPM Glink & RPM message RAM nodes to support frequency scaling
on IPQ9574.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Co-developed-by: Praveenkumar I <quic_ipkumar@quicinc.com>
Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230517172527.1968-2-quic_devipriy@quicinc.com
 2023-05-26 12:25:55 -07:00
Devi Priya
84c4a652db arm64: dts: qcom: ipq9574: Add support for APSS clock controller 
Add the APCS & A73 PLL nodes to support CPU frequency scaling.

Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230406061314.10916-5-quic_devipriy@quicinc.com
 2023-05-26 12:16:55 -07:00