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arm64: dts: qcom: ipq9574: add support for RDP418 variant

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Add the initial device tree support for the Reference Design Platform (RDP)
418 based on IPQ9574 family of SoCs. This patch adds support for Console
UART, SPI NOR, eMMC and SMPA1 regulator node.

Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230510104359.16678-3-quic_devipriy@quicinc.com
This commit is contained in:
Devi Priya
2023-05-10 16:13:59 +05:30
committed by Bjorn Andersson
parent e3c98aac28
commit d8a83f8d2e
2 changed files with 125 additions and 0 deletions
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1
arch/arm64/boot/dts/qcom/Makefile
View File

@@ -10,6 +10,7 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c1.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c2.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp418.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp433.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-acer-a1-724.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb

124
arch/arm64/boot/dts/qcom/ipq9574-rdp418.dts Normal file
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@@ -0,0 +1,124 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* IPQ9574 RDP418 board device tree source
*
* Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include "ipq9574.dtsi"
/ {
model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C2";
compatible = "qcom,ipq9574-ap-al02-c2", "qcom,ipq9574";
aliases {
serial0 = &blsp1_uart2;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&blsp1_spi0 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
flash@0 {
compatible = "micron,n25q128a11", "jedec,spi-nor";
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <50000000>;
};
};
&blsp1_uart2 {
pinctrl-0 = <&uart2_pins>;
pinctrl-names = "default";
status = "okay";
};
&rpm_requests {
regulators {
compatible = "qcom,rpm-mp5496-regulators";
ipq9574_s1: s1 {
/*
* During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders.
* During regulator registration, kernel not knowing the initial voltage,
* considers it as zero and brings up the regulators with minimum supported voltage.
* Update the regulator-min-microvolt with SVS voltage of 725mV so that
* the regulators are brought up with 725mV which is sufficient for all the
* corner parts to operate at 800MHz
*/
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1075000>;
};
};
};
&sdhc_1 {
pinctrl-0 = <&sdc_default_state>;
pinctrl-names = "default";
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
max-frequency = <384000000>;
bus-width = <8>;
status = "okay";
};
&sleep_clk {
clock-frequency = <32000>;
};
&tlmm {
sdc_default_state: sdc-default-state {
clk-pins {
pins = "gpio5";
function = "sdc_clk";
drive-strength = <8>;
bias-disable;
};
cmd-pins {
pins = "gpio4";
function = "sdc_cmd";
drive-strength = <8>;
bias-pull-up;
};
data-pins {
pins = "gpio0", "gpio1", "gpio2",
"gpio3", "gpio6", "gpio7",
"gpio8", "gpio9";
function = "sdc_data";
drive-strength = <8>;
bias-pull-up;
};
rclk-pins {
pins = "gpio10";
function = "sdc_rclk";
drive-strength = <8>;
bias-pull-down;
};
};
spi_0_pins: spi-0-state {
pins = "gpio11", "gpio12", "gpio13", "gpio14";
function = "blsp0_spi";
drive-strength = <8>;
bias-disable;
};
};
&xo_board_clk {
clock-frequency = <24000000>;
};