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Author SHA1 Message Date
Manivannan Sadhasivam
8a8845e07b arm64: dts: qcom: sm8450: Supply clock from cpufreq node to CPUs 
Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks
to the CPU cores. But this relationship is not represented in DTS so far.

So let's make cpufreq node as the clock provider and CPU nodes as the
consumers. The clock index for each CPU node is based on the frequency
domain index.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221117053145.10409-3-manivannan.sadhasivam@linaro.org
 2022-12-06 11:05:31 -06:00
Bryan O'Donoghue
16b24fe54f arm64: dts: qcom: qrb5165-rb5-vision-mezzanine: Add vision mezzanine 
The Vision Mezzanine for the RB5 ships with an imx577 and ov9282 populated.
Other sensors and components may be added or stacked with additional
mezzanines.

Enable the IMX577 on the vision mezzanine.

An example media-ctl pipeline for the imx577 is:

media-ctl --reset
media-ctl -v -d /dev/media0 -V '"imx577 '22-001a'":0[fmt:SRGGB10/4056x3040 field:none]'
media-ctl -V '"msm_csiphy2":0[fmt:SRGGB10/4056x3040]'
media-ctl -V '"msm_csid0":0[fmt:SRGGB10/4056x3040]'
media-ctl -V '"msm_vfe0_rdi0":0[fmt:SRGGB10/4056x3040]'
media-ctl -l '"msm_csiphy2":1->"msm_csid0":0[1]'
media-ctl -l '"msm_csid0":1->"msm_vfe0_rdi0":0[1]'

yavta -B capture-mplane -c -I -n 5 -f SRGGB10P -s 4056x3040 -F /dev/video0

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221117003232.589734-8-bryan.odonoghue@linaro.org
 2022-12-06 11:05:31 -06:00
Bryan O'Donoghue
3c5aa4c758 arm64: dts: qcom: sm8250: camss: Define ports and ports address/size cells 
Define the set of possible ports, one for each CSI PHY along with the port
address and size cells @ the SoC dtsi level.

Suggested-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Suggested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221117003232.589734-7-bryan.odonoghue@linaro.org
 2022-12-06 11:05:31 -06:00
Bryan O'Donoghue
64cb4a4472 arm64: dts: qcom: sdm845-db845c-navigation-mezzanine: Add navigation mezzanine dts 
Move the dts data for the rb3 navigation mezzanine into its own dts file.

Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221117003232.589734-6-bryan.odonoghue@linaro.org
 2022-12-06 11:05:31 -06:00
Bryan O'Donoghue
5ceaa402f4 arm64: dts: qcom: sdm845-db845c: Use okay not ok, disabled not disable for status 
Use preferred "ok" not "okay".
Use preferred status "disabled" instead of "disable".

There's no functional change here so no Fixes has been applied.

Reported-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221117003232.589734-5-bryan.odonoghue@linaro.org
 2022-12-06 11:05:31 -06:00
Bryan O'Donoghue
693c65e2bd arm64: dts: qcom: sdm845-db845c: Drop redundant reg = in port 
The reg for the port is specified in the dtsi. Remove from the db845c dts.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221117003232.589734-4-bryan.odonoghue@linaro.org
 2022-12-06 11:05:31 -06:00
Bryan O'Donoghue
dacfbacc88 arm64: dts: qcom: sdm845-db845c: Drop redundant address-cells, size-cells declaration 
sdm845.dtsi camss already defines the address-cells and size-cells for
camss, no need to replicate in sdm845-db845c.dts.

Reported-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221117003232.589734-3-bryan.odonoghue@linaro.org
 2022-12-06 11:05:30 -06:00
Bryan O'Donoghue
0ddcea2f76 arm64: dts: qcom: sdm845: Define the number of available ports 
The number of available ports is SoC specific so we should define it in the
SoC dtsi. For the case of the sdm845 that is 4 CSI PHYs => four ports.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221117003232.589734-2-bryan.odonoghue@linaro.org
 2022-12-06 11:05:30 -06:00
Konrad Dybcio
1aaa077274 arm64: dts: qcom: sm8350-sagami: Wire up SDHCI2 
Adjust regulators, add required pin setup and finally enable SDHCI2
to get the SD Card slot going on Sagami Xperias.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221116123612.34302-4-konrad.dybcio@linaro.org
 2022-12-06 11:05:30 -06:00
Konrad Dybcio
dcbb6fe5d6 arm64: dts: qcom: sm8350-sagami: Add GPIO line names for TLMM 
Sony ever so graciously provides GPIO line names in their downstream
kernel (though sometimes they are not 100% accurate and you can judge
that by simply looking at them and with what drivers they are used).

Add these to the Sagami-common / PDX215 DTSIs to better document the
hardware.

Diff between 215 and common:
< 			  "NC",
< 			  "NC",
> 			  "WLC_I2C_SDA",
> 			  "WLC_I2C_SCL",
< 			  "NC",
> 			  "WLC_INT_N",
> 			  "CAM_MCLK4",
< 			  "NC",
< 			  "NC",
> 			  "TOF_RST_N",
< 			  "NC",
< 			  "NC",
< 			  "NC",
> 			  "QLINK1_REQ",
> 			  "QLINK1_EN",
> 			  "QLINK1_WMSS_RESET_N",

It's pretty logical as 1 III has WLC (WireLess Charging), and an
additional 3D iToF sensor. As for QLINK, no idea.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221116123612.34302-3-konrad.dybcio@linaro.org
 2022-12-06 11:05:30 -06:00
Konrad Dybcio
60477435e4 arm64: dts: qcom: sm8350: Add SDHCI2 
Add and configure the SDHCI host responsible for (mostly) SD Card and
its corresponding pins' sleep states.

The setup is *literally* 1:1 with 8450 (bar SDR50/104 may not be
broken).

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221116123612.34302-2-konrad.dybcio@linaro.org
 2022-12-06 11:05:30 -06:00
Johan Hovold
25f08f02f4 arm64: dts: qcom: clean up 'regulator-allowed-modes' indentation 
When recently adding the missing 'regulator-allowed-modes' properties it
appears that the binding example with its four-spaces indentation
(corresponding to a single tab, which is still to little) was copied
verbatim.

Drop the unnecessary first line break after 'regulator-allowed-modes'
properties and indent the single remaining continuation line properly.

Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221116102054.4673-3-johan+linaro@kernel.org
 2022-12-06 11:05:30 -06:00
Srinivasa Rao Mandadapu
7fa58dc94d arm64: dts: qcom: sc7280: Remove unused sleep pin control nodes 
Remove unused and redundant sleep pin control entries as they are
not referenced anywhere in sc7280 based platform's device tree variants.

Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Reported-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/1668591184-21099-1-git-send-email-quic_srivasam@quicinc.com
 2022-12-06 11:05:30 -06:00
Konrad Dybcio
f46ef374e0 arm64: dts: qcom: pmk8350: Specify PBS register for PON 
PMK8350 is the first PMIC to require both HLOS and PBS registers for
PON to function properly (at least in theory, sm8350 sees no change).
The support for it on the driver side has been added long ago,
but it has never been wired up. Do so.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221115132626.7465-1-konrad.dybcio@linaro.org
 2022-12-06 11:05:30 -06:00
Konrad Dybcio
a94ed9f38e arm64: dts: qcom: sm8150: Use defines for power domain indices 
Use the defines from qcom-rpmpd.h instead of bare numbers for
readability.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221115130936.6830-2-konrad.dybcio@linaro.org
 2022-12-06 11:05:30 -06:00
Konrad Dybcio
3d530a0f4c arm64: dts: qcom: sm8450: Use defines for power domain indices 
Use the defines from qcom-rpmpd.h instead of bare numbers for
readability.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221115130936.6830-1-konrad.dybcio@linaro.org
 2022-12-06 11:05:30 -06:00
Konrad Dybcio
a2ad207c41 arm64: dts: qcom: sm6375-pdx225: Enable ADSP & CDSP 
Enable the newly added remote processors and assign them a firmware
path.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221114105913.37044-4-konrad.dybcio@linaro.org
 2022-12-06 11:05:30 -06:00
Konrad Dybcio
fe6fd26aed arm64: dts: qcom: sm6375: Add ADSP&CDSP 
Add ADSP & CDSP remote processors.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221114105913.37044-3-konrad.dybcio@linaro.org
 2022-12-06 11:05:30 -06:00
Konrad Dybcio
6f86fe79da arm64: dts: qcom: sm6375: Add SMP2P for ADSP&CDSP 
Add nodes for ADSP&CDSP SMP2P.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221114105913.37044-2-konrad.dybcio@linaro.org
 2022-12-06 11:05:30 -06:00
Konrad Dybcio
ecbdcbcd6f arm64: dts: qcom: sm6375-pdx225: Enable SD card slot 
Set SDHCI VMMC/VQMMC to <=2v96 and allow load setting by the SDHCI
driver, as required by this use case.

Configure the SD Card Detect pin, enable the SDHCI2 controller and
assign it the aforementioned regulators.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221114105043.36698-4-konrad.dybcio@linaro.org
 2022-12-06 11:05:30 -06:00
Konrad Dybcio
51ed312aa5 arm64: dts: qcom: sm6375-pdx225: Configure Samsung touchscreen 
Add a pretty bog-standard-for-Xperias-for-the-past-3-years
touchscreen setup.

The OEM that built the Xperia 10 IV for SONY decided to use some
kind of a GPIO regulator that needs to be enabled at all times
for both the touch panel and the display panel to function.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221115152727.9736-10-konrad.dybcio@linaro.org
 2022-12-06 11:05:30 -06:00
Konrad Dybcio
a4fb3dd848 arm64: dts: qcom: sm6375-pdx225: Configure SMD RPM regulators 
Configure regulators present on the Xperia 10 IV that are reachable
via SMD RPM.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221115152727.9736-9-konrad.dybcio@linaro.org
 2022-12-06 11:05:30 -06:00
Konrad Dybcio
6742dca249 arm64: dts: qcom: sm6375-pdx225: Add PMIC peripherals 
Add and enable PMIC peripherals for PM6125, PMR735a and PMK8350 on
the Xperia 10 IV.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221115152727.9736-8-konrad.dybcio@linaro.org
 2022-12-06 11:05:30 -06:00
Konrad Dybcio
9d796b52bc arm64: dts: qcom: sm6375-pdx225: Enable QUPs & GPI DMA 
Enable QUPs & GPI DMA on the Xperia 10 IV.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221115152727.9736-7-konrad.dybcio@linaro.org
 2022-12-06 11:05:30 -06:00
Konrad Dybcio
6f196ab2ad arm64: dts: qcom: sm6375: Add SDHCI2 
Configure the second SDHCI bus controller, which usually the
interface used for SD cards.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221114105043.36698-3-konrad.dybcio@linaro.org
 2022-12-06 11:05:29 -06:00
Konrad Dybcio
b0dfe3c9d6 arm64: dts: qcom: sm6375: Add QUPs and corresponding SPI/I2C hosts 
Add necessary nodes to support various QUP configurations. Note that:

- QUP3/4/5 and 11 are straight up missing
- There may be more QUPs physically on the SoC that work perfectly
fine, but Qualcomm decided not to expose them on the downstream kernel
- Many are missing pinctrls, as there are both missing pin funcs in
the TLMM driver and missing configuration settings (though they are
possible to guesstimate quite easily)

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221115152727.9736-6-konrad.dybcio@linaro.org
 2022-12-06 11:05:29 -06:00
Konrad Dybcio
704edf03c0 arm64: dts: qcom: sm6375: Add pin configs for some QUP configurations 
Add the pin setup for SPI/I2C configurations that are supported
downstream. I can guesstimate the correct settings for other buses,
but:

- I have no hardware to test it on
- Some QUPs are straight up missing pin funcs in TLMM
- Vendors probably didn't really care and used whatever was there in
the reference design and BSP - should any other be used, they can be
configured at a later time

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221115152727.9736-5-konrad.dybcio@linaro.org
 2022-12-06 11:05:29 -06:00
Konrad Dybcio
42b8e5eeaf arm64: dts: qcom: sm6375: Add GPI DMA nodes 
Add nodes for GPI DMA hosts on SM6375.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221115152727.9736-4-konrad.dybcio@linaro.org
 2022-12-06 11:05:29 -06:00
Konrad Dybcio
f73de026a4 arm64: dts: qcom: pmk8350: Allow specifying arbitrary SID 
PMK8350 is shipped on SID6 with some SoCs, for example with SM6375.
Add some preprocessor logic to allow changing the SID in cases like
this.

While I am not in favour of adding #if's into the device tree, this
is the least messy way to handle this. If one isn't specified, it
will default to 0 (as it has been previously).

Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221115152727.9736-3-konrad.dybcio@linaro.org
 2022-12-06 11:05:29 -06:00
Konrad Dybcio
d409e44d2e arm64: dts: qcom: sm8450-nagara: Add Samsung touchscreen 
Add device node and required pinctrl settings (as well as a fixup for
an existing one, whoops!) to support the Samsung Electronics
touchscreen on Nagara devices.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221114095654.34561-4-konrad.dybcio@linaro.org
 2022-12-06 11:05:29 -06:00
Konrad Dybcio
7d54cdf564 arm64: dts: qcom: sm8450: Add Xperia 5 IV support 
Add a device tree for the Xperia 5 IV (pdx224). It's literally the 1 IV
with a smaller body, different panel, one camera lens (not sensor afaict)
swapped out and no 3D iToF sensor, hence the device-specific DT is tiny.

Be sure to follow the vbmeta disablement steps (detailed in pdx223
introduction commit message), otherwise your phone will not boot and
will reject anything and everything with just a non-descriptive
"Your device is corrupted" followed by a sad reboot. This should not
be the case, as vbmeta should be plainly ignored in unlocked state,
but what can we do..

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221114095654.34561-3-konrad.dybcio@linaro.org
 2022-12-06 11:05:29 -06:00
Konrad Dybcio
1620676b85 arm64: dts: qcom: sm8450-nagara: Separate out Nagara platform dtsi 
Turns out 1 IV is not the only Nagara device, reflect that in the DTS.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221114095654.34561-2-konrad.dybcio@linaro.org
 2022-12-06 11:05:29 -06:00
Mao Jinlong
7960de6421 arm64: dts: qcom: sm8250: Add coresight components 
Add coresight components for sm8250. STM/ETM are added.

Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221114091251.13939-1-quic_jinlmao@quicinc.com
 2022-12-06 11:05:29 -06:00
Dzmitry Sankouski
f86ae6f23a arm64: dts: qcom: sagit: add initial device tree for sagit 
New device support - Xiaomi Mi6 phone

What works:
- storage
- usb
- power regulators

Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Konrad Dybcio <konra.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221112203300.536010-3-dsankouski@gmail.com
 2022-12-06 11:05:29 -06:00
AngeloGioacchino Del Regno
ff7f6d34ca arm64: dts: qcom: Add support for SONY Xperia X/X Compact 
This adds support for the Sony Xperia Loire/SmartLoire platform
with a base configuration that is common across all of the
devices that are based on this project.

Also adds a base DT configuration for the Xperia X and Xperia
X Compact (respectively, Suzu and Kugo) which is valid for both
their RoW (single-sim), DSDS (dual-sim) and other regional
variants of these two smartphones, that makes us able to boot
to a UART console.

Please note that, currently, the APC0/1 (cluster 0/1) vregs
are set to a safe voltage in order to ensure boot stability
until a proper solution for CPU DVFS scaling lands.

Co-developed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Co-developed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221111120156.48040-12-angelogioacchino.delregno@collabora.com
 2022-12-06 11:05:29 -06:00
AngeloGioacchino Del Regno
0484d3ce09 arm64: dts: qcom: Add DTS for MSM8976 and MSM8956 SoCs 
This commit adds device trees for MSM8956 and MSM8976 SoCs.
They are *almost* identical, with minor differences, such as
MSM8956 having two A72 cores less.

However, there is a bug in Sony Loire bootloader that requires presence
of all 8 cores in the cpu{} node, so these will not be deleted.

Co-developed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Co-developed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221111120156.48040-11-angelogioacchino.delregno@collabora.com
 2022-12-06 11:05:29 -06:00
AngeloGioacchino Del Regno
0d97fdf380 arm64: dts: qcom: Add configuration for PMI8950 peripheral 
The PMI8950 features integrated peripherals like ADC, GPIO controller,
MPPs and others.

[luca@z3ntu.xyz: remove pm8950, style changes for 2022 standards, add wled]

Signed-off-by: AngeloGioacchino Del Regno <kholk11@gmail.com>
Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221101161801.1058969-2-luca@z3ntu.xyz
 2022-12-06 11:05:29 -06:00
AngeloGioacchino Del Regno
e07f41b0e1 arm64: dts: qcom: Add configuration for PM8950 peripheral 
The PM8950 features integrated peripherals like ADC, GPIO controller,
MPPs, PON keys and others.
Add them to DT files that will be imported on boards having this PMIC
combo (or one of them, anyways).

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Co-developed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221111120156.48040-10-angelogioacchino.delregno@collabora.com
 2022-12-06 11:05:29 -06:00
Johan Hovold
f8d8840c72 arm64: dts: qcom: sm8250: fix USB-DP PHY registers 
When adding support for the DisplayPort part of the QMP PHY the binding
(and devicetree parser) for the (USB) child node was simply reused and
this has lead to some confusion.

The third DP register region is really the DP_PHY region, not "PCS" as
the binding claims, and lie at offset 0x2a00 (not 0x2c00).

Similarly, there likely are no "RX", "RX2" or "PCS_MISC" regions as
there are for the USB part of the PHY (and in any case the Linux driver
does not use them).

Note that the sixth "PCS_MISC" region is not even in the binding.

Fixes: 5aa0d1becd ("arm64: dts: qcom: sm8250: switch usb1 qmp phy to USB3+DP mode")
Cc: stable@vger.kernel.org      # 5.13
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221111094729.11842-3-johan+linaro@kernel.org
 2022-12-06 11:05:29 -06:00
Johan Hovold
347b9491c5 arm64: dts: qcom: sm6350: fix USB-DP PHY registers 
When adding support for the DisplayPort part of the QMP PHY the binding
(and devicetree parser) for the (USB) child node was simply reused and
this has lead to some confusion.

The third DP register region is really the DP_PHY region, not "PCS" as
the binding claims, and lie at offset 0x2a00 (not 0x2c00).

Similarly, there likely are no "RX", "RX2" or "PCS_MISC" regions as
there are for the USB part of the PHY (and in any case the Linux driver
does not use them).

Note that the sixth "PCS_MISC" region is not even in the binding.

Fixes: 23737b9557 ("arm64: dts: qcom: sm6350: Add USB1 nodes")
Cc: stable@vger.kernel.org      # 5.16
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221111094729.11842-2-johan+linaro@kernel.org
 2022-12-06 11:05:29 -06:00
Johan Hovold
9eb18ed70b arm64: dts: qcom: sc8280xp: drop reference-clock source 
The source clock for the reference clock should not be described by the
devicetree binding and instead this relationship should be modelled in
the clock driver.

Update the USB PHY nodes to match the fixed binding.

Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221111093857.11360-4-johan+linaro@kernel.org
 2022-12-06 11:05:29 -06:00
Bjorn Andersson
64ebe7fc47 arm64: dts: qcom: sc8280xp: Add bwmon instances 
Add the two bwmon instances and define votes for CPU -> LLCC and LLCC ->
DDR, with bandwidth values based on the downstream DeviceTree.

Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Tested-by: Steev Klimaszewski <steev@kali.org>
Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221111032515.3460-11-quic_bjorande@quicinc.com
 2022-12-06 11:05:28 -06:00
Bjorn Andersson
33ba07ffd3 arm64: dts: qcom: sc8280xp: Set up L3 scaling 
Add the L3 interconnect path to all CPUs and define the bandwidth
requirements for all opp entries across sc8280xp and sa8540p.

The values are based on the tables reported by the hardware, distributed
such that each value is the largest value, lower than the cluster
frequency.

Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Tested-by: Steev Klimaszewski <steev@kali.org>
Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221111032515.3460-9-quic_bjorande@quicinc.com
 2022-12-06 11:05:28 -06:00
Bjorn Andersson
e4f68d6c32 arm64: dts: qcom: sc8280xp: Add epss_l3 node 
Add a device node for the EPSS L3 frequency domain.

Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Tested-by: Steev Klimaszewski <steev@kali.org>
Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221111032515.3460-8-quic_bjorande@quicinc.com
 2022-12-06 11:05:28 -06:00
Bjorn Andersson
a0289a1040 arm64: dts: qcom: Align with generic osm-l3/epss-l3 
Update all references to OSM or EPSS L3 compatibles, to include the
generic compatible, as defined by the updated binding.

Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Tested-by: Steev Klimaszewski <steev@kali.org>
Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221111032515.3460-7-quic_bjorande@quicinc.com
 2022-12-06 11:05:28 -06:00
Johan Hovold
33c4e6588e arm64: dts: qcom: sc8280xp: update UFS PHY nodes 
Update the UFS PHY nodes to match the new binding.

Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Brian Masney <bmasney@redhat.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221104092045.17410-3-johan+linaro@kernel.org
 2022-12-06 11:05:28 -06:00
Christian Marangi
08f399a818 arm64: dts: qcom: ipq6018: improve pcie phy pcs reg table 
This is not a fix on its own but more a cleanup. Phy qmp pcie driver
currently have a workaround to handle pcs_misc not declared and add
0x400 offset to the pcs reg if pcs_misc is not declared.

Correctly declare pcs_misc reg and reduce PCS size to the common value
of 0x1f0 as done for every other qmp based pcie phy device.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221103212125.17156-2-ansuelsmth@gmail.com
 2022-12-06 11:05:28 -06:00
Nícolas F. R. A. Prado
147e8b2080 arm64: dts: qcom: sc7180-trogdor: Remove VBAT supply from rt5682s 
These devicetrees override a rt5682 node to use the rt5682s compatible,
however, unlike rt5682, rt5682s doesn't have a VBAT supply. Remove the
inexistent supply in the rt5682s nodes.

Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221102182002.255282-9-nfraprado@collabora.com
 2022-12-06 11:05:28 -06:00
Nícolas F. R. A. Prado
172cb25fd2 arm64: dts: qcom: sc7180-trogdor: Add missing supplies for rt5682 
The DBVDD and LDO1-IN supplies for rt5682 are required but are missing.
They are supplied by the same power rail as AVDD. Add them.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221102182002.255282-8-nfraprado@collabora.com
 2022-12-06 11:05:28 -06:00
Bjorn Andersson
30d70ec8f7 arm64: dts: qcom: sa8295p-adp: Add RTC node 
The first PM8540 PMIC has an available RTC block, describe this in the
SA8295P ADP. Mark it as wakeup-source to allow waking the system from
sleep.

Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221205174309.16733-1-quic_bjorande@quicinc.com
 2022-12-06 11:05:28 -06:00