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arm64: dts: qcom: sc8280xp: update UFS PHY nodes

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Update the UFS PHY nodes to match the new binding.

Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Brian Masney <bmasney@redhat.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221104092045.17410-3-johan+linaro@kernel.org
This commit is contained in:
Johan Hovold
2022-11-04 10:20:45 +01:00
committed by Bjorn Andersson
parent 08f399a818
commit 33c4e6588e
1 changed files with 17 additions and 32 deletions
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49
arch/arm64/boot/dts/qcom/sc8280xp.dtsi
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@@ -1337,7 +1337,7 @@ ufs_mem_hc: ufs@1d84000 {
"jedec,ufs-2.0";
reg = <0 0x01d84000 0 0x3000>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufs_mem_phy_lanes>;
phys = <&ufs_mem_phy>;
phy-names = "ufsphy";
lanes-per-direction = <2>;
#reset-cells = <1>;
@@ -1378,27 +1378,20 @@ ufs_mem_hc: ufs@1d84000 {
ufs_mem_phy: phy@1d87000 {
compatible = "qcom,sc8280xp-qmp-ufs-phy";
reg = <0 0x01d87000 0 0x1c8>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
clock-names = "ref",
"ref_aux";
reg = <0 0x01d87000 0 0x1000>;
clocks = <&gcc GCC_UFS_CARD_CLKREF_CLK>,
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
clock-names = "ref", "ref_aux";
power-domains = <&gcc UFS_PHY_GDSC>;
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
status = "disabled";
ufs_mem_phy_lanes: phy@1d87400 {
reg = <0 0x01d87400 0 0x108>,
<0 0x01d87600 0 0x1e0>,
<0 0x01d87c00 0 0x1dc>,
<0 0x01d87800 0 0x108>,
<0 0x01d87a00 0 0x1e0>;
#phy-cells = <0>;
};
#phy-cells = <0>;
status = "disabled";
};
ufs_card_hc: ufs@1da4000 {
@@ -1406,7 +1399,7 @@ ufs_card_hc: ufs@1da4000 {
"jedec,ufs-2.0";
reg = <0 0x01da4000 0 0x3000>;
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufs_card_phy_lanes>;
phys = <&ufs_card_phy>;
phy-names = "ufsphy";
lanes-per-direction = <2>;
#reset-cells = <1>;
@@ -1446,28 +1439,20 @@ ufs_card_hc: ufs@1da4000 {
ufs_card_phy: phy@1da7000 {
compatible = "qcom,sc8280xp-qmp-ufs-phy";
reg = <0 0x01da7000 0 0x1c8>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
clock-names = "ref",
"ref_aux";
reg = <0 0x01da7000 0 0x1000>;
clocks = <&gcc GCC_UFS_1_CARD_CLKREF_CLK>,
<&gcc GCC_UFS_CARD_PHY_AUX_CLK>;
clock-names = "ref", "ref_aux";
power-domains = <&gcc UFS_CARD_GDSC>;
resets = <&ufs_card_hc 0>;
reset-names = "ufsphy";
status = "disabled";
#phy-cells = <0>;
ufs_card_phy_lanes: phy@1da7400 {
reg = <0 0x01da7400 0 0x108>,
<0 0x01da7600 0 0x1e0>,
<0 0x01da7c00 0 0x1dc>,
<0 0x01da7800 0 0x108>,
<0 0x01da7a00 0 0x1e0>;
#phy-cells = <0>;
};
status = "disabled";
};
tcsr_mutex: hwlock@1f40000 {