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Krzysztof Kozlowski
79dd160c67 arm64: dts: qcom: sm8750-mtp: Enable USB headset and Type-C accessory mode 
MTP8750 does not have audio jack connected and relies on USB mux
(WCD9395).  Add necessary nodes for proper audio headset support along
with USB Type-C accessory mode and orientation.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260317-sm8750-display-dts-v5-3-fb53371e251c@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-26 09:40:39 -05:00
Krzysztof Kozlowski
20a7612116 arm64: dts: qcom: sm8750-mtp: Enable display 
Enable display on MTP8750 board with Novatek NT37801 panel.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260317-sm8750-display-dts-v5-2-fb53371e251c@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-26 09:40:39 -05:00
Krzysztof Kozlowski
818ae2b389 arm64: dts: qcom: sm8750: Add display (MDSS) with Display CC 
Add device nodes for entire display: MDSS, DPU, DSI, DSI PHYs,
DisplayPort and Display Clock Controller.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260317-sm8750-display-dts-v5-1-fb53371e251c@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-26 09:40:39 -05:00
Dmitry Baryshkov
2755bdd02a arm64: dts: qcom: sm8750: correct Iris corners for the MXC rail 
The corners of the MVS0 / MVS0C clocks on the MMCX rail don't always
match the PLL corners on the MXC rail. Correct the performance corners
for the MXC rail following the PLL documentation.

Fixes: c0d11ff904 ("arm64: dts: qcom: sm8750: Add Iris VPU v3.5")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260313-iris-fix-corners-v1-6-32a393c25dda@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-26 09:40:39 -05:00
Dmitry Baryshkov
7c302a2a6c arm64: dts: qcom: sm8650: correct Iris corners for the MXC rail 
The corners of the MVS0 / MVS0C clocks on the MMCX rail don't always
match the PLL corners on the MXC rail. Correct the performance corners
for the MXC rail following the PLL documentation.

Fixes: 56cf5ad39a ("arm64: dts: qcom: sm8650: add iris DT node")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260313-iris-fix-corners-v1-5-32a393c25dda@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-26 09:40:38 -05:00
Dmitry Baryshkov
ff8edb5bc8 arm64: dts: qcom: sm8550: correct Iris corners for the MXC rail 
The corners of the MVS0 / MVS0C clocks on the MMCX rail don't always
match the PLL corners on the MXC rail. Correct the performance corners
for the MXC rail following the PLL documentation.

Fixes: 41661853ae ("arm64: dts: qcom: sm8550: add iris DT node")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260313-iris-fix-corners-v1-4-32a393c25dda@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-26 09:40:38 -05:00
Dmitry Baryshkov
bba8d9ba7d arm64: dts: qcom: monaco: correct Iris corners for the MXC rail 
The corners of the MVS0 / MVS0C clocks on the MMCX rail don't always
match the PLL corners on the MXC rail. Correct the performance corners
for the MXC rail following the PLL documentation.

Fixes: bf6ec39c3f ("arm64: dts: qcom: qcs8300: add video node")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260313-iris-fix-corners-v1-3-32a393c25dda@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-26 09:40:38 -05:00
Dmitry Baryshkov
85a6cf5ef8 arm64: dts: qcom: lemans: correct Iris corners for the MXC rail 
The corners of the MVS0 / MVS0C clocks on the MMCX rail don't always
match the PLL corners on the MXC rail. Correct the performance corners
for the MXC rail following the PLL documentation.

Fixes: 7bc95052c6 ("arm64: dts: qcom: sa8775p: add support for video node")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260313-iris-fix-corners-v1-2-32a393c25dda@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-26 09:40:38 -05:00
Dmitry Baryshkov
baac8b5e43 arm64: dts: qcom: hamoa: correct Iris corners for the MXC rail 
The corners of the MVS0 / MVS0C clocks on the MMCX rail don't always
match the PLL corners on the MXC rail. Correct the performance corners
for the MXC rail following the PLL documentation.

Fixes: 9065340ac0 ("arm64: dts: qcom: x1e80100: Add IRIS video codec")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260313-iris-fix-corners-v1-1-32a393c25dda@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-26 09:40:38 -05:00
Luca Weiss
cf11d15613 arm64: dts: qcom: milos: add ADSP GPR 
Add the ADSP Generic Packet Router (GPR) device node as part of audio
subsystem in Qualcomm Milos SoC.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260306-milos-fastrpc-gpr-v1-2-893eb98869ce@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-26 09:40:38 -05:00
Luca Weiss
a6a2c01db7 arm64: dts: qcom: milos: Add fastrpc nodes 
Add fastrpc nodes for both ADSP and CDSP.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260306-milos-fastrpc-gpr-v1-1-893eb98869ce@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-26 09:40:37 -05:00
Abel Vesa
2a5d4fc6f3 arm64: dts: qcom: eliza: Enable Eliza MTP board support 
The MTP is a one of the boards that comes with the Eliza SoC.
So add dedicated board dts for it.

The initial support enables:
- UART debug console
- Ob-board UFS storage
- Qualcomm RPMh regulators (PMIC) and VPH_PWR
- board specific clocks & reserved GPIO ranges

Co-developed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260318-eliza-base-dt-v3-3-8a50bd2201ed@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-26 09:40:37 -05:00
Abel Vesa
af20af39fc arm64: dts: qcom: Introduce Eliza Soc base dtsi 
Introduce the initial support for the Qualcomm Eliza SoC. It comes in
different flavors. There is SM7750 for mobiles and then QC7790S/M for IoT.
Describe the common parts under a common dtsi.

The initial submission enables support for:
- CPU nodes with cpufreq and cpuidle support
- Global Clock Controller (GCC)
- Resource State Coordinator (RSC) with clock controller & genpd provider
- Interrupt controller
- Power Domain Controller (PDC)
- Vendor specific SMMU
- SPMI bus arbiter
- Top Control and Status Register (TCSR)
- Top Level Mode Multiplexer (TLMM)
- Debug UART
- Reserved memory nodes
- Interconnect providers
- System timer
- UFS

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Co-developed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260318-eliza-base-dt-v3-2-8a50bd2201ed@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-26 09:40:37 -05:00
Abel Vesa
38ddb6110d dt-bindings: arm: qcom: Document Eliza SoC and its MTP board 
Qualcomm Eliza SoC comes with different flavors. There is SM7750 for
mobiles and then QC7790S/M for IoT. One of the boards that comes with
Eliza SoC is the MTP.

So document both the SoC and MTP board compatibles.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260318-eliza-base-dt-v3-1-8a50bd2201ed@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-26 09:40:37 -05:00
Bjorn Andersson
c6d976b89d Merge branch 'icc-eliza' of https://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc into HEAD 
Merge the Eliza interconnect DeviceTree bindings from topic branch, in
order to introduce the interconnect constants used in the Eliza
DeviceTree source.
 2026-03-26 09:40:37 -05:00
Bjorn Andersson
c10e71b0b7 Merge branch '20260311-eliza-clocks-v6-1-453c4cf657a2@oss.qualcomm.com' into HEAD 
Merge Eliza Global, RPMH, and TCSR clock controller bindings from topic
branch, in order to gain access to the clock defines.
 2026-03-26 09:40:36 -05:00
Gopikrishna Garmidi
c1014a629d arm64: dts: qcom: Add Mahua SoC and CRD 
Introduce support for the Mahua SoC and the CRD based on it. Some of
the notable differences are the absent CPU cluster, interconnect, TLMM,
thermal zones and adjusted PCIe west clocks. Everything else should
work as-is.

Co-developed-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
Co-developed-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
Co-developed-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com>
Signed-off-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com>
Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260318124100.212992-4-gopikrishna.garmidi@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-26 09:40:36 -05:00
Gopikrishna Garmidi
a5ad8a8e47 arm64: dts: qcom: Commonize Glymur CRD DTSI 
Commonize the existing Glymur CRD DTSI to allow reuse with Mahua CRDs.

Leave the PCIe3b nodes disabled by default, since the UEFI has the instance
disabled to avoid boot delays due to link failures.

Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260318124100.212992-3-gopikrishna.garmidi@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-26 09:40:36 -05:00
Gopikrishna Garmidi
2c93d2986f dt-bindings: arm: qcom: Document Mahua SoC and board 
Mahua is a derivative of Glymur SoC with the third CPU cluster disabled.
Document the compatible strings for the Mahua SoC and the Compute
Reference Device (CRD) board based on it.

Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260318124100.212992-2-gopikrishna.garmidi@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-26 09:40:36 -05:00
Gaurav Kohli
71ede5c790 arm64: dts: qcom: hamoa-iot-evk: Update TSENS thermal zone configuration 
Hamoa IOT boards support a different thermal junction temperature
specification compared to the base Hamoa platform due to package
level differences.

Update the passive trip thresholds to 105°C to align with the higher
temperature specification.

Signed-off-by: Gaurav Kohli <gaurav.kohli@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260302-higher_tj-v1-1-4c0d288f8e7f@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-26 09:40:36 -05:00
Wei Deng
ca4d6e4b83 arm64: dts: qcom: qcs8300-ride: Enable Bluetooth support 
Enable BT on qcs8300-ride by adding a BT device tree node.

Since the platform uses the QCA6698 Bluetooth chip. While
the QCA6698 shares the same IP core as the WCN6855, it has
different RF components and RAM sizes, requiring new firmware
files. Use the firmware-name property to specify the NVM and
rampatch firmware to load.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Wei Deng <wei.deng@oss.qualcomm.com>
Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260302024658.2836798-1-wei.deng@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-26 09:40:35 -05:00
Wei Zhang
1752a96fe7 arm64: dts: qcom: qcs8300-ride: enable WLAN on qcs8300-ride 
Enable WLAN on qcs8300-ride by adding a node for the PMU module
of the WCN6855 and assigning its LDO power outputs to the existing
WiFi module.

On the qcs8300-ride platform, the corresponding firmware and BDF
are QCA6698AQ instead of WCN6855, which have been added in the
20250211 release.

Signed-off-by: Wei Zhang <wei.zhang@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260225071459.1600394-1-wei.zhang@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-26 09:40:35 -05:00
Sarthak Garg
c679452028 arm64: dts: qcom: hamoa-iot-evk: Add SDC2 node for hamoa iot evk board 
Enable SD Card host controller for hamoa iot evk board.

Signed-off-by: Sarthak Garg <sarthak.garg@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260227040201.3700324-1-sarthak.garg@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-26 09:40:35 -05:00
Tobias Heider
9ffb2dfcc9 arm64: dts: qcom: add missing denali-oled.dtb to Makefile 
The DeviceTree for the OLED variant of the Microsoft Surface Pro 11th
Edition was originally added in commit '0d72ccaa1e84 ("arm64: dts: qcom:
Add support for X1-based Surface Pro 11")'. The original patch on the
mailing list also added the new device tree to the Makefile but that
part seems to have been dropped (by accident) when it got merged.

Signed-off-by: Tobias Heider <tobias.heider@canonical.com>
Fixes: 0d72ccaa1e ("arm64: dts: qcom: Add support for X1-based Surface Pro 11")
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260226140429.232544-3-tobias.heider@canonical.com
[bjorn: Rewrote commit message reference to offending commit]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-26 09:40:35 -05:00
Erikas Bitovtas
6c4b960981 arm64: dts: qcom: msm8939-asus-z00t: add ambient light and proximity sensor 
This device uses Capella CM36686 as its ambient light and proximity
sensor. It is fully compatible with Vishay VCNL4040. Downstream device
tree reports Capella CM36283, but upon probe, a device ID for CM36686 is
actually found. This commit adds support for Capella CM36686 ambient
light and proximity sensor.

Signed-off-by: Erikas Bitovtas <xerikasxx@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260225-z00t-capella-sensor-v1-1-99f767bc326a@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-26 09:40:35 -05:00
Biswapriyo Nath
b2c79f3583 arm64: dts: qcom: pm6125: Enable RTC by default 
sm6125 soc uses this for real time clock.

Signed-off-by: Biswapriyo Nath <nathbappai@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260121-xiaomi-ginkgo-features-v2-5-fb3ee94922d0@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-26 09:40:35 -05:00
Biswapriyo Nath
20b50a4615 arm64: dts: qcom: sm6125-xiaomi-ginkgo: Enable debug UART 
Enable the debug uart node in xiaomi ginkgo exposed as test points.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Biswapriyo Nath <nathbappai@gmail.com>
Link: https://lore.kernel.org/r/20260121-xiaomi-ginkgo-features-v2-4-fb3ee94922d0@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-26 09:40:34 -05:00
Biswapriyo Nath
ec6896cfa0 arm64: dts: qcom: sm6125: Add debug UART node 
qup0 on sm6125 has 6 SEs and SE4 is used as debug uart. The uart node
and the associated pinctrl are added here.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Biswapriyo Nath <nathbappai@gmail.com>
Link: https://lore.kernel.org/r/20260121-xiaomi-ginkgo-features-v2-3-fb3ee94922d0@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-26 09:40:34 -05:00
Biswapriyo Nath
0a586c2c8e arm64: dts: qcom: sm6125: Add PRNG node 
Add a node for the PRNG to enable hardware accelerated pseudo random
number generation.

Signed-off-by: Biswapriyo Nath <nathbappai@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260121-xiaomi-ginkgo-features-v2-2-fb3ee94922d0@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-26 09:40:34 -05:00
Biswapriyo Nath
c0580b57a3 arm64: dts: qcom: sm6125-xiaomi-ginkgo: Fix volume up button 
gpio6 in pm6125 is used for EMMC and UFS thermal monitoring. It is
changed to the correct gpio for volume up button.

Fixes: 9b1a6c925c ("arm64: dts: qcom: sm6125: Initial support for xiaomi-ginkgo")
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Biswapriyo Nath <nathbappai@gmail.com>
Link: https://lore.kernel.org/r/20260121-xiaomi-ginkgo-features-v2-1-fb3ee94922d0@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-26 09:40:34 -05:00
Nihal Kumar Gupta
95b97fe010 arm64: dts: qcom: monaco-evk-camera: Add DT overlay 
Monaco EVK board does not include a camera sensor in its default hardware
configuration. Introducing a device tree overlay to support optional
integration of the IMX577 sensor via CSIPHY1.

Camera reset is handled through an I2C expander, and power is enabled
via TLMM GPIO74.

An example media-ctl pipeline for the imx577 is:

media-ctl --reset
media-ctl -V '"imx577 3-001a":0[fmt:SRGGB10/4056x3040 field:none]'
media-ctl -V '"msm_csiphy1":0[fmt:SRGGB10/4056x3040]'
media-ctl -V '"msm_csid0":0[fmt:SRGGB10/4056x3040]'
media-ctl -V '"msm_vfe0_rdi0":0[fmt:SRGGB10/4056x3040]'
media-ctl -l '"msm_csiphy1":1->"msm_csid0":0[1]'
media-ctl -l '"msm_csid0":1->"msm_vfe0_rdi0":0[1]'
yavta -B capture-mplane -c -I -n 5 -f SRGGB10P -s 4056x3040 -F /dev/video1

Co-developed-by: Ravi Shankar <quic_rshankar@quicinc.com>
Signed-off-by: Ravi Shankar <quic_rshankar@quicinc.com>
Co-developed-by: Vishal Verma <quic_vishverm@quicinc.com>
Signed-off-by: Vishal Verma <quic_vishverm@quicinc.com>
Signed-off-by: Nihal Kumar Gupta <quic_nihalkum@quicinc.com>
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260213132058.521474-6-quic_nihalkum@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-26 09:40:34 -05:00
Nihal Kumar Gupta
66e70dea65 arm64: dts: qcom: monaco-evk: Add camera AVDD regulators 
Define three fixed regulators for camera AVDD rails, each gpio-controlled
with corresponding pinctrl definitions.

Signed-off-by: Nihal Kumar Gupta <quic_nihalkum@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Link: https://lore.kernel.org/r/20260213132058.521474-5-quic_nihalkum@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-26 09:40:34 -05:00
Nihal Kumar Gupta
14733a228b arm64: dts: qcom: monaco: Add camera MCLK pinctrl 
Define pinctrl definitions to enable camera master clocks on Monaco.

Signed-off-by: Nihal Kumar Gupta <quic_nihalkum@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Link: https://lore.kernel.org/r/20260213132058.521474-4-quic_nihalkum@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-26 09:40:33 -05:00
Nihal Kumar Gupta
a16f9d5373 arm64: dts: qcom: monaco: Add CCI definitions 
Qualcomm QCS8300 SoC contains three Camera Control Interface (CCI).
Compared to Lemans, the key difference is in SDA/SCL GPIO assignments
and number of CCIs.

Co-developed-by: Ravi Shankar <quic_rshankar@quicinc.com>
Signed-off-by: Ravi Shankar <quic_rshankar@quicinc.com>
Co-developed-by: Vishal Verma <quic_vishverm@quicinc.com>
Signed-off-by: Vishal Verma <quic_vishverm@quicinc.com>
Co-developed-by: Suresh Vankadara <quic_svankada@quicinc.com>
Signed-off-by: Suresh Vankadara <quic_svankada@quicinc.com>
Signed-off-by: Nihal Kumar Gupta <quic_nihalkum@quicinc.com>
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260213132058.521474-3-quic_nihalkum@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-26 09:40:33 -05:00
Luca Weiss
9fc67d20c9 arm64: dts: qcom: milos-fairphone-fp6: Add Hall Effect sensor 
Add a node for the Hall Effect sensor, used to detect whether the Flip
Cover is closed or not.

The sensor is powered through vreg_l10b, so let's put a
regulator-always-on on that to make sure the sensor gets power.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260213-fp6-hall-sensor-v2-1-ecd113d4919c@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-26 09:40:33 -05:00
Ayushi Makhija
8540abbf33 arm64: dts: qcom: qcs8300-ride: add anx7625 DSI to DP bridge node 
Add anx7625 DSI to DP bridge device node.

Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260217090955.2446470-3-quic_amakhija@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-26 09:40:33 -05:00
Ayushi Makhija
3333dfc08a arm64: dts: qcom: qcs8300: add Display Serial Interface device nodes 
Add device tree nodes for the DSI0 controller with their corresponding
PHY found on Qualcomm QCS8300 SoC.

Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260217090955.2446470-2-quic_amakhija@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-26 09:40:33 -05:00
Luca Weiss
ed9d901253 arm64: dts: qcom: milos: Sort pinctrl subnodes by pins 
As documented in the "Devicetree Sources (DTS) Coding Style" document,
pinctrl subnodes should be sorted by the pins property. Do this once for
milos.dtsi so that future additions can be added at the right places.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260213-milos-pinctrl-sort-v1-1-799bae597074@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-26 09:40:32 -05:00
Dmitry Baryshkov
d5574bb935 arm64: dts: qcom: qrb2210-arduino-imola: describe DSI / DP bridge 
Aruino Uno-Q uses Analogix ANX7625 DSI-to-DP bridge to convert DSI
signals to the connected USB-C DisplayPort dongles. Decribe the chip,
USB-C connector and routing of USB and display signals.

Co-developed-by: Martino Facchin <m.facchin@arduino.cc>
Signed-off-by: Martino Facchin <m.facchin@arduino.cc>
Tested-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260213-uno-q-anx7625-v2-1-c23359616528@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-26 09:40:32 -05:00
Riccardo Mereu
1a040df09f arm64: dts: qcom: arduino-imola: fix faulty spidev node 
CS pin added on pinctrl0 property is causing spidev to return -ENODEV
since that GPIO is already part of spi5 pinmuxing.

Fixes: 3f745bc0f1 ("arm64: dts: qcom: qrb2210: add dts for Arduino unoq")
Signed-off-by: Riccardo Mereu <r.mereu@arduino.cc>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260213101002.105238-1-r.mereu.kernel@arduino.cc
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-26 09:40:32 -05:00
Xilin Wu
99e38f5683 arm64: dts: qcom: sm8550: Add UART15 
Add uart15 node for UART bus present on sm8550 SoC.

Signed-off-by: Molly Sophia <mollysophia379@gmail.com>
Signed-off-by: Xilin Wu <wuxilin123@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260212-sm8550-uart15-v3-1-b90405f94bec@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-26 09:40:32 -05:00
Yedaya Katsman
8cbbb33904 arm64: dts: qcom: sm6125-xiaomi-laurel-sprout: Add Focaltech FT3518 touchscreen 
Add device tree node for the Focaltech FT3518 touchscreen on
Xiaomi Mi A3 (laurel-sprout).

Enable qupv3_id_0 and i2c2 bus that the touchscreen is on.

Downstream references:
Link: https://github.com/MiCode/Xiaomi_Kernel_OpenSource/blob/laurel-r-oss/arch/arm64/boot/dts/qcom/trinket-pinctrl.dtsi
Link: https://github.com/MiCode/Xiaomi_Kernel_OpenSource/blob/laurel-r-oss/arch/arm64/boot/dts/qcom/laurel_sprout-qrd.dtsi

Co-developed-by: Kamil Gołda <kamil.golda@protonmail.com>
Signed-off-by: Kamil Gołda <kamil.golda@protonmail.com>
Signed-off-by: Yedaya Katsman <yedaya.ka@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260208-touchscreen-patches-v5-1-5821dff9c9a2@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-26 09:40:32 -05:00
Aleksandrs Vinarskis
09d72b0ef8 arm64: dts: qcom: x1-asus-zenbook-a14: add HDMI port 
Add HDMI port that utilizes qmpphy via Parade PS185HDM DP-HDMI
bridge.

Based on commit 34d76723c4 ("arm64: dts: qcom: x1e80100-vivobook-s15:
add HDMI port")

Signed-off-by: Aleksandrs Vinarskis <alex@vinarskis.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260211-zenbook-a14-improvements-v1-1-d970af6e25a3@vinarskis.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-26 09:40:32 -05:00
Xueyao An
cb7db0f401 arm64: dts: qcom: hamoa-iot-som: Add firmware-name to QUPv3 nodes 
Traditionally, firmware loading for Serial Engines (SE) in the QUP hardware
of Qualcomm SoCs has been managed by TrustZone (TZ). While this approach
ensures secure SE assignment and access control, it limits flexibility for
developers who need to enable various protocols on different SEs.

Add the firmware-name property to QUPv3 nodes in the device tree to enable
firmware loading from the Linux environment. Handle SE assignments and
access control permissions directly within Linux, removing the dependency
on TrustZone.

Signed-off-by: Xueyao An <xueyao.an@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260212082558.2811953-1-xueyao.an@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-26 09:40:31 -05:00
Luca Weiss
73feb0d1e2 arm64: dts: qcom: kodiak: Add I2S1 pinctrl definitions 
Add the pinctrl definitions to configure gpio6-gpio9 of the lpass_tlmm
for I2S output.

Co-developed-by: Bharadwaj Raju <bharadwaj.raju@machinesoul.in>
Signed-off-by: Bharadwaj Raju <bharadwaj.raju@machinesoul.in>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260211-kodiak-i2s1-v1-1-b3a7fad8014e@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-26 09:40:31 -05:00
Manivannan Sadhasivam
408b79c097 arm64: dts: qcom: x1e80100: Add '#cooling-cells' for CPU nodes 
Enable passive cooling for CPUs in the X1E80100 SoC by adding the
'#cooling-cells' property. This will allow the OS to mitigate the CPU
power dissipation with the help of SCMI DVFS.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Tested-by: Gaurav Kohli <gaurav.kohli@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260210070321.17033-1-manivannan.sadhasivam@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-18 07:16:51 -05:00
Krzysztof Kozlowski
90b7cc18e9 arm64: dts: qcom: x1-crd: add USB DisplayPort audio 
Add support for playing audio over USB DisplayPort (the two left USB-C
ports on the CRD device).

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260209093237.33287-2-krzysztof.kozlowski@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-18 07:14:54 -05:00
Roger Shimizu
1cde54c54b arm64: dts: qcom: qcs6490: Add Thundercomm AI Mini PC G1 IoT 
Thundercomm AI MiniPC G1 IoT is single board computer with
AI capability based on Qualcomm QCS6490 platform.

This device tree is confirmed to work as below:
- GPU
- HDMI output port
- PCIe M.2 port (for external Wi-Fi or 5G connectivity)
- UART / serial console port
- UFS
- USB Type-C port, with Display Port

Signed-off-by: Roger Shimizu <rosh@debian.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260207-next-20260130_rosh-v2-3-548bbe0c7742@debian.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-18 07:14:18 -05:00
Roger Shimizu
5230355252 arm64: dts: qcom: kodiak: Add missing usb-role-switch property 
Add missing usb-role-switch property to usb_1 node.

Signed-off-by: Roger Shimizu <rosh@debian.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260207-next-20260130_rosh-v2-2-548bbe0c7742@debian.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-18 07:13:43 -05:00
Roger Shimizu
bc7cc1c4a3 dt-bindings: arm: qcom: Add Thundercomm AI Mini PC G1 IoT 
Document Thundercomm AI Mini PC G1 IoT.

Signed-off-by: Roger Shimizu <rosh@debian.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260207-next-20260130_rosh-v2-1-548bbe0c7742@debian.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-18 07:13:43 -05:00