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arm64: dts: qcom: sm8550: Add UART15

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Add uart15 node for UART bus present on sm8550 SoC.

Signed-off-by: Molly Sophia <mollysophia379@gmail.com>
Signed-off-by: Xilin Wu <wuxilin123@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260212-sm8550-uart15-v3-1-b90405f94bec@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Xilin Wu
2026-02-12 10:41:25 -06:00
committed by Bjorn Andersson
parent 8cbbb33904
commit 99e38f5683
1 changed files with 24 additions and 0 deletions
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24
arch/arm64/boot/dts/qcom/sm8550.dtsi
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@@ -1251,6 +1251,22 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
#size-cells = <0>;
status = "disabled";
};
uart15: serial@89c000 {
compatible = "qcom,geni-uart";
reg = <0 0x0089c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_uart15_default>;
interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>;
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
};
i2c_master_hub_0: geniqup@9c0000 {
@@ -5103,6 +5119,14 @@ qup_uart14_cts_rts: qup-uart14-cts-rts-state {
bias-pull-down;
};
qup_uart15_default: qup-uart15-default-state {
/* TX, RX */
pins = "gpio74", "gpio75";
function = "qup2_se7";
drive-strength = <2>;
bias-pull-up;
};
sdc2_sleep: sdc2-sleep-state {
clk-pins {
pins = "sdc2_clk";