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arm64: dts: qcom: x1e80100: Add '#cooling-cells' for CPU nodes

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Enable passive cooling for CPUs in the X1E80100 SoC by adding the
'#cooling-cells' property. This will allow the OS to mitigate the CPU
power dissipation with the help of SCMI DVFS.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Tested-by: Gaurav Kohli <gaurav.kohli@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260210070321.17033-1-manivannan.sadhasivam@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Manivannan Sadhasivam
2026-02-10 12:33:21 +05:30
committed by Bjorn Andersson
parent 90b7cc18e9
commit 408b79c097
1 changed files with 12 additions and 0 deletions
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12
arch/arm64/boot/dts/qcom/hamoa.dtsi
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@@ -75,6 +75,7 @@ cpu0: cpu@0 {
next-level-cache = <&l2_0>;
power-domains = <&cpu_pd0>, <&scmi_dvfs 0>;
power-domain-names = "psci", "perf";
#cooling-cells = <2>;
l2_0: l2-cache {
compatible = "cache";
@@ -91,6 +92,7 @@ cpu1: cpu@100 {
next-level-cache = <&l2_0>;
power-domains = <&cpu_pd1>, <&scmi_dvfs 0>;
power-domain-names = "psci", "perf";
#cooling-cells = <2>;
};
cpu2: cpu@200 {
@@ -101,6 +103,7 @@ cpu2: cpu@200 {
next-level-cache = <&l2_0>;
power-domains = <&cpu_pd2>, <&scmi_dvfs 0>;
power-domain-names = "psci", "perf";
#cooling-cells = <2>;
};
cpu3: cpu@300 {
@@ -111,6 +114,7 @@ cpu3: cpu@300 {
next-level-cache = <&l2_0>;
power-domains = <&cpu_pd3>, <&scmi_dvfs 0>;
power-domain-names = "psci", "perf";
#cooling-cells = <2>;
};
cpu4: cpu@10000 {
@@ -121,6 +125,7 @@ cpu4: cpu@10000 {
next-level-cache = <&l2_1>;
power-domains = <&cpu_pd4>, <&scmi_dvfs 1>;
power-domain-names = "psci", "perf";
#cooling-cells = <2>;
l2_1: l2-cache {
compatible = "cache";
@@ -137,6 +142,7 @@ cpu5: cpu@10100 {
next-level-cache = <&l2_1>;
power-domains = <&cpu_pd5>, <&scmi_dvfs 1>;
power-domain-names = "psci", "perf";
#cooling-cells = <2>;
};
cpu6: cpu@10200 {
@@ -147,6 +153,7 @@ cpu6: cpu@10200 {
next-level-cache = <&l2_1>;
power-domains = <&cpu_pd6>, <&scmi_dvfs 1>;
power-domain-names = "psci", "perf";
#cooling-cells = <2>;
};
cpu7: cpu@10300 {
@@ -157,6 +164,7 @@ cpu7: cpu@10300 {
next-level-cache = <&l2_1>;
power-domains = <&cpu_pd7>, <&scmi_dvfs 1>;
power-domain-names = "psci", "perf";
#cooling-cells = <2>;
};
cpu8: cpu@20000 {
@@ -167,6 +175,7 @@ cpu8: cpu@20000 {
next-level-cache = <&l2_2>;
power-domains = <&cpu_pd8>, <&scmi_dvfs 2>;
power-domain-names = "psci", "perf";
#cooling-cells = <2>;
l2_2: l2-cache {
compatible = "cache";
@@ -183,6 +192,7 @@ cpu9: cpu@20100 {
next-level-cache = <&l2_2>;
power-domains = <&cpu_pd9>, <&scmi_dvfs 2>;
power-domain-names = "psci", "perf";
#cooling-cells = <2>;
};
cpu10: cpu@20200 {
@@ -193,6 +203,7 @@ cpu10: cpu@20200 {
next-level-cache = <&l2_2>;
power-domains = <&cpu_pd10>, <&scmi_dvfs 2>;
power-domain-names = "psci", "perf";
#cooling-cells = <2>;
};
cpu11: cpu@20300 {
@@ -203,6 +214,7 @@ cpu11: cpu@20300 {
next-level-cache = <&l2_2>;
power-domains = <&cpu_pd11>, <&scmi_dvfs 2>;
power-domain-names = "psci", "perf";
#cooling-cells = <2>;
};
cpu-map {