mirrors/linux
2
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git synced 2026-05-07 23:20:32 -04:00
Code Issues Packages Projects Releases Wiki Activity
1,351,152 Commits 1 Branch 929 Tags
7459da16c9a4bf324e7f5789f296e02e7bc24b68
Commit Graph

1351152 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Stephen Boyd
7459da16c9 Merge branches 'clk-bindings', 'clk-renesas', 'clk-spacemit' and 'clk-cleanup' into clk-next 
* clk-bindings:
  dt-bindings: clock: Drop st,stm32h7-rcc.txt
  dt-bindings: clock: convert bcm2835-aux-clock to yaml
  dt-bindings: clock: Drop maxim,max77686.txt
  dt-bindings: clock: convert vf610-clock.txt to yaml format

* clk-renesas: (26 commits)
  clk: renesas: r9a09g047: Add XSPI clock/reset
  clk: renesas: r9a09g047: Add support for xspi mux and divider
  dt-bindings: clock: renesas,r9a09g047-cpg: Add XSPI and GBETH PTP core clocks
  clk: renesas: Use str_on_off() helper
  clk: renesas: r9a09g057: Add clock and reset entries for USB2
  dt-bindings: clock: renesas,r9a09g057-cpg: Add USB2 PHY and GBETH PTP core clocks
  clk: renesas: rzv2h: Use both CLK_ON and CLK_MON bits for clock state validation
  clk: renesas: rzv2h: Use str_on_off() helper in rzv2h_mod_clock_endisable()
  clk: renesas: rzv2h: Support static dividers without RMW
  clk: renesas: rzv2h: Add macro for defining static dividers
  clk: renesas: rzv2h: Add support for static mux clocks
  clk: renesas: r9a09g047: Add clock and reset entries for GE3D
  clk: renesas: rzv2h: Fix a typo
  clk: renesas: rzv2h: Add support for RZ/V2N SoC
  clk: renesas: rzv2h: Sort compatible list based on SoC part number
  dt-bindings: pinctrl: renesas: Document RZ/V2N SoC
  dt-bindings: clock: renesas: Document RZ/V2N SoC CPG
  dt-bindings: soc: renesas: Document SYS for RZ/V2N SoC
  dt-bindings: soc: renesas: Document Renesas RZ/V2N SoC variants and EVK
  clk: renesas: rzv2h: Simplify rzv2h_cpg_assert()/rzv2h_cpg_deassert()
  ...

* clk-spacemit:
  clk: spacemit: k1: Add TWSI8 bus and function clocks
  clk: spacemit: Add clock support for SpacemiT K1 SoC
  dt-bindings: clock: spacemit: Add spacemit,k1-pll
  dt-bindings: soc: spacemit: Add spacemit,k1-syscon

* clk-cleanup:
  clk: test: Forward-declare struct of_phandle_args in kunit/clk.h
  clk: davinci: Use of_get_available_child_by_name()
  clk: bcm: rpi: Add NULL check in raspberrypi_clk_register()
  clk: bcm: rpi: Drop module alias
  clk: bcm: kona: Remove unused scaled_div_build
 2025-05-29 00:30:17 -07:00
Stephen Boyd
1ffbdb7aa8 Merge tag 'renesas-clk-for-v6.16-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas 
Pull Renesas clk driver updates from Geert Uytterhoeven:

 - Add Expanded Serial Peripheral Interface (xSPI) clocks and resets on
   Renesas RZ/G3E

* tag 'renesas-clk-for-v6.16-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: r9a09g047: Add XSPI clock/reset
  clk: renesas: r9a09g047: Add support for xspi mux and divider
  dt-bindings: clock: renesas,r9a09g047-cpg: Add XSPI and GBETH PTP core clocks
  clk: renesas: Use str_on_off() helper
 2025-05-22 15:26:04 -07:00
Biju Das
28548f3f79 clk: renesas: r9a09g047: Add XSPI clock/reset 
Add XSPI clock and reset entries.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250424081400.135028-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-05-08 20:17:55 +02:00
Biju Das
38a7eb9119 clk: renesas: r9a09g047: Add support for xspi mux and divider 
The mux smux2_xspi_clk{0,1} used for selecting spi and spix2 clocks and
pllcm33_xspi divider to select different clock rates. Add support for
both.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250424081400.135028-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-05-08 20:17:55 +02:00
Geert Uytterhoeven
d4da08ea37 Merge tag 'renesas-r9a09g047-dt-binding-defs-tag3' into renesas-clk-for-v6.16 
Renesas RZ/G3E XSPI and GBETH Core DT Binding Definitions

XSPI and Gigabit Ethernet PTP reference core clock DT binding
definitions for the Renesas RZ/G3E (R9A09G047) SoC, shared by driver and
DT source files.
 2025-05-08 20:17:14 +02:00
Biju Das
f21923f3f4 dt-bindings: clock: renesas,r9a09g047-cpg: Add XSPI and GBETH PTP core clocks 
Add definitions for XSPI core clock and Gigabit Ethernet PTP reference
core clocks in the R9A09G047 CPG DT bindings header file.

The clk_spi is modelled as a fixed divider clock with parent clk_spix2 and
factor two as both parent and child share same gating bit.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250424081400.135028-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-05-08 20:11:00 +02:00
Richard Fitzgerald
7a0c1872ee clk: test: Forward-declare struct of_phandle_args in kunit/clk.h 
Add a forward-declare of struct of_phandle_args to prevent the compiler
warning:

../include/kunit/clk.h:29:63: warning: ‘struct of_phandle_args’ declared
inside parameter list will not be visible outside of this definition or
declaration
   struct clk_hw *(*get)(struct of_phandle_args *clkspec, void *data),

Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20250327125214.82598-1-rf@opensource.cirrus.com
Fixes: a82fcb16d9 ("clk: test: Add test managed of_clk_add_hw_provider()")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2025-05-06 14:50:01 -07:00
Biju Das
6064cfaa1a clk: davinci: Use of_get_available_child_by_name() 
Simplify of_davinci_pll_init() by using of_get_available_child_by_name().

While at it, move of_node_put(child) inside the if block to avoid
additional check if of_child is NULL.

Reviewed-by: David Lechner <david@lechnology.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20250410062040.6346-1-biju.das.jz@bp.renesas.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2025-05-06 14:46:00 -07:00
Henry Martin
73c46d9a93 clk: bcm: rpi: Add NULL check in raspberrypi_clk_register() 
devm_kasprintf() returns NULL when memory allocation fails. Currently,
raspberrypi_clk_register() does not check for this case, which results
in a NULL pointer dereference.

Add NULL check after devm_kasprintf() to prevent this issue.

Fixes: 93d2725aff ("clk: bcm: rpi: Discover the firmware clocks")
Signed-off-by: Henry Martin <bsdhenrymartin@gmail.com>
Reviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Link: https://lore.kernel.org/r/20250402020513.42628-1-bsdhenrymartin@gmail.com
Reviewed-by: Stefan Wahren <wahrenst@gmx.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2025-05-06 14:41:55 -07:00
Stefan Wahren
d6fbdae4f3 clk: bcm: rpi: Drop module alias 
Since commit fbac2e7787 ("clk: bcm: rpi: Allow the driver to
be probed by DT") the module alias isn't necessary anymore. So
we can drop it.

Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
Link: https://lore.kernel.org/r/20250415185614.16292-1-wahrenst@gmx.net
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2025-05-06 14:40:56 -07:00
Dr. David Alan Gilbert
1dc5da9f3c clk: bcm: kona: Remove unused scaled_div_build 
scaled_div_build() was added in 2014 by
commit 1f27f15258 ("clk: bcm281xx: add initial clock framework support")
but hasn't been used.

Remove it.

Signed-off-by: Dr. David Alan Gilbert <linux@treblig.org>
Link: https://lore.kernel.org/r/20250505013545.359745-1-linux@treblig.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2025-05-06 14:35:50 -07:00
Rob Herring (Arm)
72b421e645 dt-bindings: clock: Drop st,stm32h7-rcc.txt 
The binding is already covered by st,stm32-rcc.yaml.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250505161933.1432791-1-robh@kernel.org
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2025-05-06 14:15:02 -07:00
Stefan Wahren
619ddc6935 dt-bindings: clock: convert bcm2835-aux-clock to yaml 
Convert the DT binding document for BCM2835 auxiliary peripheral clock
from .txt to YAML.

Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
Link: https://lore.kernel.org/r/20250503080949.3945-1-wahrenst@gmx.net
Acked-by: Conor Dooley <conor.dooley@microchip.com>
[sboyd@kernel.org: Drop aux label]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2025-05-06 14:13:01 -07:00
Rob Herring (Arm)
66bd98084f dt-bindings: clock: Drop maxim,max77686.txt 
The clock binding for Maxim MAX77686/MAX77802/MAX77620 is already
covered by mfd/maxim,max77686.yaml.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250505161943.1433081-1-robh@kernel.org
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2025-05-06 14:10:36 -07:00
Stephen Boyd
f37f6ba230 Merge tag 'spacemit-clk-for-6.16-1' of https://github.com/spacemit-com/linux into clk-spacemit 
Pull SpacemiT clk driver updates from Yixun Lan:

 - Add clock driver for SpacemiT K1 SoC
 - Add TWSI8 clock, workaround the read quirk

* tag 'spacemit-clk-for-6.16-1' of https://github.com/spacemit-com/linux:
  clk: spacemit: k1: Add TWSI8 bus and function clocks
  clk: spacemit: Add clock support for SpacemiT K1 SoC
  dt-bindings: clock: spacemit: Add spacemit,k1-pll
  dt-bindings: soc: spacemit: Add spacemit,k1-syscon
 2025-05-06 10:56:52 -07:00
Stephen Boyd
bef9652131 Merge tag 'renesas-clk-for-v6.16-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas 
Pull Renesas clk driver updates from Geert Uytterhoeven:

 - Add GPU and USB2 clocks and resets on Renesas RZ/V2H(P)
 - Add support for the Renesas RZ/V2N (R9A09G056) SoC
 - Add GPU clocks and resets on Renesas RZ/G3E

* tag 'renesas-clk-for-v6.16-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: (22 commits)
  clk: renesas: r9a09g057: Add clock and reset entries for USB2
  dt-bindings: clock: renesas,r9a09g057-cpg: Add USB2 PHY and GBETH PTP core clocks
  clk: renesas: rzv2h: Use both CLK_ON and CLK_MON bits for clock state validation
  clk: renesas: rzv2h: Use str_on_off() helper in rzv2h_mod_clock_endisable()
  clk: renesas: rzv2h: Support static dividers without RMW
  clk: renesas: rzv2h: Add macro for defining static dividers
  clk: renesas: rzv2h: Add support for static mux clocks
  clk: renesas: r9a09g047: Add clock and reset entries for GE3D
  clk: renesas: rzv2h: Fix a typo
  clk: renesas: rzv2h: Add support for RZ/V2N SoC
  clk: renesas: rzv2h: Sort compatible list based on SoC part number
  dt-bindings: pinctrl: renesas: Document RZ/V2N SoC
  dt-bindings: clock: renesas: Document RZ/V2N SoC CPG
  dt-bindings: soc: renesas: Document SYS for RZ/V2N SoC
  dt-bindings: soc: renesas: Document Renesas RZ/V2N SoC variants and EVK
  clk: renesas: rzv2h: Simplify rzv2h_cpg_assert()/rzv2h_cpg_deassert()
  clk: renesas: rzv2h: Improve rzv2h_ddiv_set_rate()
  clk: renesas: r9a09g057: Add clock and reset entries for GE3D
  clk: renesas: rzv2h: Rename PLL field macros for consistency
  clk: renesas: rzv2h: Add support for enabling PLLs
  ...
 2025-05-06 10:52:40 -07:00
Geert Uytterhoeven
aff664cc8c clk: renesas: Use str_on_off() helper 
Use the str_on_off() helper instead of open-coding the same operation.
Note that this does change the case of the flags, which doesn't matter
much for debug messages.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/622f8554dcb815c8fc73511a1a118c1724570fa9.1745840497.git.geert+renesas@glider.be
 2025-05-05 10:48:07 +02:00
Frank Li
7021a86694 dt-bindings: clock: convert vf610-clock.txt to yaml format 
Convert vf610-clock.txt to yaml format.

Additional changes:
- swap audio_ext and enet_ext to match existed dts order
- remove clock consumer in example

Signed-off-by: Frank Li <Frank.Li@nxp.com>
Link: https://lore.kernel.org/r/20250411212339.3273202-1-Frank.Li@nxp.com
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2025-04-29 14:05:14 -07:00
Lad Prabhakar
93f2878136 clk: renesas: r9a09g057: Add clock and reset entries for USB2 
Add clock and reset entries for USB2.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250407165202.197570-9-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-04-22 11:38:28 +02:00
Geert Uytterhoeven
4902413495 Merge tag 'renesas-r9a09g057-dt-binding-defs-tag3' into renesas-clk-for-v6.16 
Renesas RZ/V2H USB2 and GBETH Clock DT Binding Definitions

USB2 and Gigabit Ethernet clock DT binding definitions for the Renesas
RZ/V2H (R9A09G057) SoC, shared by driver and DT source files.
 2025-04-22 11:37:21 +02:00
Lad Prabhakar
ad227dab30 dt-bindings: clock: renesas,r9a09g057-cpg: Add USB2 PHY and GBETH PTP core clocks 
Add definitions for USB2 PHY core clocks and Gigabit Ethernet PTP
reference core clocks in the R9A09G057 CPG DT bindings header file.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250407165202.197570-8-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-04-22 11:29:44 +02:00
Lad Prabhakar
ef224dd26c clk: renesas: rzv2h: Use both CLK_ON and CLK_MON bits for clock state validation 
Update the clock enable/disable logic to follow the latest hardware
manual's guidelines, ensuring that both CLK_ON and CLK_MON bits are used
to confirm the clock state.

According to the manual, enabling a clock requires setting the
CPG_CLK_ON bit and verifying the clock has started using the CPG_CLK_MON
bit.  Similarly, disabling a clock requires clearing the CPG_CLK_ON bit
and confirming the clock has stopped via the CPG_CLK_MON bit.

Modify `rzv2h_mod_clock_is_enabled()` to check CLK_MON first and then
validate CLK_ON for a more accurate clock status evaluation.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250407165202.197570-6-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-04-22 11:27:12 +02:00
Lad Prabhakar
e6c2b4ed49 clk: renesas: rzv2h: Use str_on_off() helper in rzv2h_mod_clock_endisable() 
Replace hard-coded "ON"/"OFF" strings with the `str_on_off()` helper in
`rzv2h_mod_clock_endisable()`.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250407165202.197570-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-04-22 11:27:12 +02:00
Biju Das
52239ebe62 clk: renesas: rzv2h: Support static dividers without RMW 
Add support for static dividers that do not require read-modify-write
(RMW) operations.  This enables the use of the generic clk_divider_ops
instead of the custom RMW-based implementation.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Co-developed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250407165202.197570-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-04-22 11:27:12 +02:00
Lad Prabhakar
6e1c795071 clk: renesas: rzv2h: Add macro for defining static dividers 
Unlike dynamic dividers, static dividers do not have a monitor bit.
Introduce the `DEF_CSDIV()` macro for defining static dividers, ensuring
consistency with existing dynamic divider macros.

Additionally, introduce the `CSDIV_NO_MON` macro to indicate the absence
of a monitor bit, allowing the monitoring step to be skipped when `mon`
is set to `CSDIV_NO_MON`.

Note, `rzv2h_cpg_ddiv_clk_register()` will be re-used instead of generic
`clk_hw_register_divider_table()` for registering satic dividers as some
of the static dividers require RMW operations.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250407165202.197570-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-04-22 11:27:12 +02:00
Lad Prabhakar
c1d6f686e5 clk: renesas: rzv2h: Add support for static mux clocks 
Add support for `CLK_TYPE_SMUX` to register static muxed clocks on the
Renesas RZ/V2H(P) SoC.  Extend `cpg_core_clk` to include parent names,
mux flags, and a new `smuxed` struct.  Update clock registration to
handle static mux clocks.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250407165202.197570-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-04-22 11:27:12 +02:00
Tommaso Merciai
9375d704d2 clk: renesas: r9a09g047: Add clock and reset entries for GE3D 
Add CLK_PLLVDO_GPU along with the necessary clock and reset entries for
GE3D.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250402131142.1270701-2-tommaso.merciai.xr@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-04-22 11:26:40 +02:00
Biju Das
506f96095e clk: renesas: rzv2h: Fix a typo 
Fix a typo montor->monitor in kernel-doc comment.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250320093107.36784-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-04-22 11:18:07 +02:00
Haylen Chu
49625c6e4d clk: spacemit: k1: Add TWSI8 bus and function clocks 
The control register for TWSI8 clocks, APBC_TWSI8_CLK_RST, contains mux
selection bits, reset assertion bit and enable bits for function and bus
clocks. It has a quirk that reading always results in zero.

As a workaround, let's hardcode the mux value as zero to select
pll1_d78_31p5 as parent and treat twsi8_clk as a gate, whose enable mask
is combined from the real bus and function clocks to avoid the
write-only register being shared between two clk_hws, in which case
updates of one clk_hw zero the other's bits.

With a 1:1 factor serving as placeholder for the bus clock, the I2C-8
controller could be brought up, which is essential for boards attaching
power-management chips to it.

Signed-off-by: Haylen Chu <heylenay@4d2.org>
Reviewed-by: Alex Elder <elder@riscstar.com>
Reviewed-by: Yixun Lan <dlan@gentoo.org>
Link: https://lore.kernel.org/r/20250416135406.16284-5-heylenay@4d2.org
Signed-off-by: Yixun Lan <dlan@gentoo.org>
 2025-04-17 03:22:56 +08:00
Haylen Chu
1b72c59db0 clk: spacemit: Add clock support for SpacemiT K1 SoC 
The clock tree of K1 SoC contains three main types of clock hardware
(PLL/DDN/MIX) and has control registers split into several multifunction
devices: APBS (PLLs), MPMU, APBC and APMU.

All register operations are done through regmap to ensure atomicity
between concurrent operations of clock driver and reset,
power-domain driver that will be introduced in the future.

Signed-off-by: Haylen Chu <heylenay@4d2.org>
Reviewed-by: Alex Elder <elder@riscstar.com>
Reviewed-by: Inochi Amaoto <inochiama@outlook.com>
Reviewed-by: Yixun Lan <dlan@gentoo.org>
Link: https://lore.kernel.org/r/20250416135406.16284-4-heylenay@4d2.org
Signed-off-by: Yixun Lan <dlan@gentoo.org>
 2025-04-17 03:22:53 +08:00
Haylen Chu
8090804045 dt-bindings: clock: spacemit: Add spacemit,k1-pll 
Add definition for the PLL found on SpacemiT K1 SoC, which takes the
external 24MHz oscillator as input and generates clocks in various
frequencies for the system.

Signed-off-by: Haylen Chu <heylenay@4d2.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Alex Elder <elder@riscstar.com>
Reviewed-by: Yixun Lan <dlan@gentoo.org>
Link: https://lore.kernel.org/r/20250416135406.16284-3-heylenay@4d2.org
Signed-off-by: Yixun Lan <dlan@gentoo.org>
 2025-04-17 03:22:49 +08:00
Haylen Chu
61e312a001 dt-bindings: soc: spacemit: Add spacemit,k1-syscon 
Document APMU, MPMU and APBC syscons found on SpacemiT K1 SoC, which are
capable of generating clock and reset signals. Additionally, APMU and MPMU
manage power domains.

Signed-off-by: Haylen Chu <heylenay@4d2.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Alex Elder <elder@riscstar.com>
Reviewed-by: Yixun Lan <dlan@gentoo.org>
Link: https://lore.kernel.org/r/20250416135406.16284-2-heylenay@4d2.org
Signed-off-by: Yixun Lan <dlan@gentoo.org>
 2025-04-17 03:22:46 +08:00
Lad Prabhakar
f6462eb04f clk: renesas: rzv2h: Add support for RZ/V2N SoC 
The clock structure for RZ/V2N is almost identical to RZ/V2H(P) SoC
with less IP blocks compared to RZ/V2H(P). For eg: CRU2/3 are present
only on the RZ/V2H(P) SoC.

Add minimal clock and reset entries required to boot the Renesas
RZ/V2N EVK and binds it with the RZ/V2H CPG family driver.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250407191628.323613-9-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-04-14 10:58:14 +02:00
Geert Uytterhoeven
019b1a8454 Merge tag 'renesas-r9a09g056-dt-binding-defs-tag1' into renesas-clk-for-v6.16 
Renesas RZ/V2N DT Bindings and Definitions

DT bindings and binding definitions for the Renesas RZ/V2N (R9A09G056)
SoC, shared by driver and DT source files.
 2025-04-14 10:56:36 +02:00
Lad Prabhakar
c3400fd7c7 clk: renesas: rzv2h: Sort compatible list based on SoC part number 
Reorder the compatible entries in `rzv2h_cpg_match[]` to follow a
numerical sequence based on the SoC part numbers.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250407191628.323613-8-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-04-14 10:54:41 +02:00
Lad Prabhakar
626acded47 dt-bindings: pinctrl: renesas: Document RZ/V2N SoC 
Add documentation for the pin controller found on the Renesas RZ/V2N
(R9A09G056) SoC. The RZ/V2N PFC differs slightly from the RZ/G2L family
and is almost identical to the RZ/V2H(P) SoC, except that the RZ/V2H(P) SoC
has an additional dedicated pin.

To account for this, a SoC-specific compatible string,
'renesas,r9a09g056-pinctrl', is introduced for the RZ/V2N SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250407191628.323613-10-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-04-14 10:48:18 +02:00
Lad Prabhakar
c04269c022 dt-bindings: clock: renesas: Document RZ/V2N SoC CPG 
Document the device tree bindings for the Renesas RZ/V2N (R9A09G056)
SoC Clock Pulse Generator (CPG).

Update `renesas,rzv2h-cpg.yaml` to include the compatible string for
RZ/V2N SoC and adjust the title and description accordingly.

Additionally, introduce `renesas,r9a09g056-cpg.h` to define core clock
constants for the RZ/V2N SoC. Note the existing RZ/V2H(P) family-specific
clock driver will be reused for this SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250407191628.323613-7-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-04-14 10:48:18 +02:00
Lad Prabhakar
dc7af24bd6 dt-bindings: soc: renesas: Document SYS for RZ/V2N SoC 
Add the RZ/V2N (R9A09G056) variant to the existing RZ/V2H(P) System
Controller (SYS) binding, as both IPs are very similar.

However, they have different SoC IDs, and the RZ/V2N does not have
PCIE1 configuration registers, unlike the RZ/V2H(P) SYS IP. To handle
these differences, introduce a new compatible string
`renesas,r9a09g056-sys`.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250407191628.323613-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-04-14 10:48:18 +02:00
Lad Prabhakar
abc43c0f3c dt-bindings: soc: renesas: Document Renesas RZ/V2N SoC variants and EVK 
Document the Renesas RZ/V2N (R9A09G056) SoC variants, distinguishing
between configurations with and without specific hardware features such
as GPU, ISP, and cryptographic extensions. Also, document the
"renesas,rzv2n-evk" compatible string for the RZ/V2N EVK board.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250407191628.323613-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-04-14 10:48:18 +02:00
Tommaso Merciai
b224c42568 clk: renesas: rzv2h: Simplify rzv2h_cpg_assert()/rzv2h_cpg_deassert() 
rzv2h_cpg_assert() and rzv2h_cpg_deassert() functions are similar. Share
this code via __rzv2h_cpg_assert(). This avoid code duplication.

Reported-by: Pavel Machek <pavel@denx.de>
Closes: https://lore.kernel.org/cip-dev/Z9QA9rwuXCuVbOXp@duo.ucw.cz/
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250317083213.371614-4-tommaso.merciai.xr@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-04-14 10:09:59 +02:00
Tommaso Merciai
ce0a97ff71 clk: renesas: rzv2h: Improve rzv2h_ddiv_set_rate() 
Remove duplicate code into rzv2h_ddiv_set_rate().

Reported-by: Pavel Machek <pavel@denx.de>
Closes: https://lore.kernel.org/cip-dev/Z9QBZo4GgtMjid0v@duo.ucw.cz/
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250317083213.371614-3-tommaso.merciai.xr@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-04-14 10:09:40 +02:00
Lad Prabhakar
b6f2c6bd4e clk: renesas: r9a09g057: Add clock and reset entries for GE3D 
Add PLLGPU along with the necessary clock and reset entries for GE3D.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250309211402.80886-6-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-04-08 10:16:09 +02:00
Lad Prabhakar
360387a8f1 clk: renesas: rzv2h: Rename PLL field macros for consistency 
Rename PLL field extraction macros to include the associated register name
(`CPG_PLL_CLK1` or `CPG_PLL_CLK2`) to maintain consistency with other PLL
register macros. Update all corresponding macro references accordingly.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250309211402.80886-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-04-08 10:16:09 +02:00
Lad Prabhakar
fea942bc15 clk: renesas: rzv2h: Add support for enabling PLLs 
Some RZ/V2H(P) SoC variants do not have a GPU, resulting in PLLGPU being
disabled by default in TF-A. Add support for enabling PLL clocks in the
RZ/V2H(P) CPG driver to manage this.

Introduce `is_enabled` and `enable` callbacks to handle PLL state
transitions. With the `enable` callback, PLLGPU will be turned ON only
when the GPU node is enabled; otherwise, it will remain off. Define new
macros for PLL standby and monitor registers to facilitate this process.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250309211402.80886-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-04-08 10:16:09 +02:00
Lad Prabhakar
18510fd7bf clk: renesas: rzv2h: Remove unused type field from struct pll_clk 
Remove the redundant `type` field from `struct pll_clk`, as it is not used
in the PLL clock handling logic.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250309211402.80886-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-04-08 10:16:09 +02:00
Lad Prabhakar
20fc4ea6d7 clk: renesas: rzv2h: Refactor PLL configuration handling 
Refactor PLL handling by introducing a `struct pll` to encapsulate PLL
configuration parameters, ensuring consistency with the existing dynamic
divider structure.

Introduce the `PLL_PACK()` macro to simplify PLL structure initialization
and update the `DEF_PLL()` macro to use the new `pll` structure. Modify
relevant clock register functions to utilize the structured PLL data
instead of raw configuration values.

This refactoring improves code readability, maintainability, and
alignment with the existing clock configuration approach.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250309211402.80886-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-04-08 10:16:09 +02:00
Linus Torvalds
0af2f6be1b Linux 6.15-rc1 v6.15-rc1 2025-04-06 13:11:33 -07:00
Thomas Weißschuh
0efdedb335 tools/include: make uapi/linux/types.h usable from assembly 
The "real" linux/types.h UAPI header gracefully degrades to a NOOP when
included from assembly code.

Mirror this behaviour in the tools/ variant.

Test for __ASSEMBLER__ over __ASSEMBLY__ as the former is provided by the
toolchain automatically.

Reported-by: Mark Brown <broonie@kernel.org>
Closes: https://lore.kernel.org/lkml/af553c62-ca2f-4956-932c-dd6e3a126f58@sirena.org.uk/
Fixes: c9fbaa8795 ("selftests: vDSO: parse_vdso: Use UAPI headers instead of libc headers")
Signed-off-by: Thomas Weißschuh <thomas.weissschuh@linutronix.de>
Link: https://patch.msgid.link/20250321-uapi-consistency-v1-1-439070118dc0@linutronix.de
Signed-off-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
 2025-04-06 12:55:31 -07:00
Linus Torvalds
710329254d Merge tag 'turbostat-2025.05.06' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux 
Pull turbostat updates from Len Brown:

 - support up to 8192 processors

 - add cpuidle governor debug telemetry, disabled by default

 - update default output to exclude cpuidle invocation counts

 - bug fixes

* tag 'turbostat-2025.05.06' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux:
  tools/power turbostat: v2025.05.06
  tools/power turbostat: disable "cpuidle" invocation counters, by default
  tools/power turbostat: re-factor sysfs code
  tools/power turbostat: Restore GFX sysfs fflush() call
  tools/power turbostat: Document GNR UncMHz domain convention
  tools/power turbostat: report CoreThr per measurement interval
  tools/power turbostat: Increase CPU_SUBSET_MAXCPUS to 8192
  tools/power turbostat: Add idle governor statistics reporting
  tools/power turbostat: Fix names matching
  tools/power turbostat: Allow Zero return value for some RAPL registers
  tools/power turbostat: Clustered Uncore MHz counters should honor show/hide options
 2025-04-06 12:32:43 -07:00
Linus Torvalds
59f392fa7c Merge tag 'soundwire-6.15-rc1-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/soundwire 
Pull soundwire fix from Vinod Koul:

 - add missing config symbol CONFIG_SND_HDA_EXT_CORE required for asoc
   driver CONFIG_SND_SOF_SOF_HDA_SDW_BPT

* tag 'soundwire-6.15-rc1-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/soundwire:
  ASoC: SOF: Intel: Let SND_SOF_SOF_HDA_SDW_BPT select SND_HDA_EXT_CORE
 2025-04-06 12:04:53 -07:00