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clk: renesas: rzv2h: Use both CLK_ON and CLK_MON bits for clock state validation

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Update the clock enable/disable logic to follow the latest hardware
manual's guidelines, ensuring that both CLK_ON and CLK_MON bits are used
to confirm the clock state.

According to the manual, enabling a clock requires setting the
CPG_CLK_ON bit and verifying the clock has started using the CPG_CLK_MON
bit.  Similarly, disabling a clock requires clearing the CPG_CLK_ON bit
and confirming the clock has stopped via the CPG_CLK_MON bit.

Modify `rzv2h_mod_clock_is_enabled()` to check CLK_MON first and then
validate CLK_ON for a more accurate clock status evaluation.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250407165202.197570-6-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Lad Prabhakar
2025-04-07 17:51:58 +01:00
committed by Geert Uytterhoeven
parent e6c2b4ed49
commit ef224dd26c
1 changed files with 6 additions and 3 deletions
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9
drivers/clk/renesas/rzv2h-cpg.c
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@@ -573,11 +573,14 @@ static int rzv2h_mod_clock_is_enabled(struct clk_hw *hw)
if (clock->mon_index >= 0) {
offset = GET_CLK_MON_OFFSET(clock->mon_index);
bitmask = BIT(clock->mon_bit);
} else {
offset = GET_CLK_ON_OFFSET(clock->on_index);
bitmask = BIT(clock->on_bit);
if (!(readl(priv->base + offset) & bitmask))
return 0;
}
offset = GET_CLK_ON_OFFSET(clock->on_index);
bitmask = BIT(clock->on_bit);
return readl(priv->base + offset) & bitmask;
}