Commit Graph

1461762 Commits

Author SHA1 Message Date
Gerald Loacker
333c23c316 phy: rockchip: phy-rockchip-inno-csidphy: add clock lane phase tuning
At high data rates like 4K60 (2500 Mbps), such as when using an
LT6911GXD bridge chip on an RK3588 board, fixed default timing parameters
can cause signal integrity issues and clock-data recovery failures.
The driver currently lacks a mechanism to adjust the clock lane sampling
phase to compensate for board-specific trace variations.

Resolve this by parsing and applying the optional 'rockchip,clk-lane-phase'
device tree property. This enables board-specific tuning of the clock
lane sampling phase in ~40 ps steps (range 0-7) to optimize link
stability. If the property is absent, the driver falls back to the
hardware default.

Signed-off-by: Gerald Loacker <gerald.loacker@wolfvision.net>
Reviewed-by: Michael Riesch <michael.riesch@collabora.com>
Link: https://patch.msgid.link/20260725-feature-mipi-csi-dphy-4k60-v4-3-5b2c4626d31e@wolfvision.net
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-08-06 21:35:36 +05:30
Gerald Loacker
f82ff8609f dt-bindings: phy: rockchip-inno-csi-dphy: add rockchip,clk-lane-phase property
Add support for the optional rockchip,clk-lane-phase device tree property
to allow board-specific tuning of the clock lane sampling phase for
improved signal integrity across supported data rates.

Acked-by: Rob Herring (Arm) <robh@kernel.org>
Acked-by: Michael Riesch <michael.riesch@collabora.com>
Signed-off-by: Gerald Loacker <gerald.loacker@wolfvision.net>
Link: https://patch.msgid.link/20260725-feature-mipi-csi-dphy-4k60-v4-2-5b2c4626d31e@wolfvision.net
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-08-06 21:35:36 +05:30
Gerald Loacker
4fae43e33a phy: rockchip: phy-rockchip-inno-csidphy: fix rk1808 hsfreq table
The rk1808 hsfreq table capped at 2499 Mbps, preventing a data rate of
exactly 2500 Mbps. Extend the final entry to 2500 Mbps to support this
rate.

This is essential for RK3588 reusing this array and fully supporting
rates up to 2500 Mbps.

Fixes: bd1f775d60 ("phy/rockchip: add Innosilicon-based CSI dphy")
Reviewed-by: Michael Riesch <michael.riesch@collabora.com>
Signed-off-by: Gerald Loacker <gerald.loacker@wolfvision.net>
Link: https://patch.msgid.link/20260725-feature-mipi-csi-dphy-4k60-v4-1-5b2c4626d31e@wolfvision.net
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-08-06 21:35:36 +05:30
Felix Gu
8b2683bc4c phy: sunplus: fix error handling in sp_uphy_init()
Fix the error paths of sp_uphy_init() to undo exactly what each stage
did: return directly if clk_prepare_enable() fails, release only the clock
if reset_control_deassert() fails, and jump to err_reset if
update_disc_vol() fails so the clock and reset are not leaked.

Fixes: 99d9ccd973 ("phy: usb: Add USB2.0 phy driver for Sunplus SP7021")
Signed-off-by: Felix Gu <ustc.gu@gmail.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Link: https://patch.msgid.link/20260803-sunplus-usb3-v1-1-5a562524c869@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-08-06 21:34:42 +05:30
Felix Gu
b780b8929c phy: renesas: rcar-gen2: Fix double of_node_put on phy creation failure
for_each_child_of_node_scoped() releases the node reference on scope
exit, so the explicit of_node_put(np) in the devm_phy_create() error
path drops it twice.

Drop the redundant of_node_put() and let the scoped cleanup handle it.

Fixes: b64b32791f ("phy: renesas: rcar-gen2: Simplify with scoped for each OF child loop")
Signed-off-by: Felix Gu <ustc.gu@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://patch.msgid.link/20260803-rcar-gen2-v1-1-9aa35c36d7d7@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-08-06 21:31:57 +05:30
Xu Yang
ee9e2b39ea phy: fsl-imx8mq-usb: keep PHY power domain runtime always-on for i.MX8MP
On i.MX8MP, the USB PHY has a dedicated power domain that was previously
never powered off at runtime. With the introduction of runtime PM support,
the power domain will be powered off if the device is runtime suspended,
which breaks USB wakeup functionality.

To preserve wakeup functionality, mark the PHY power domain as runtime
always-on for i.MX8MP platform. To limit the behavior to i.MX8MP, add a
need_genpd_rpm_on to imx8mq_usb_phy_drvdata and set it as true for i.MX8MP.

Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20260731-imx8mp-usb-phy-improvement-v8-6-2ec8d6b3854d@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-08-06 21:15:09 +05:30
Xu Yang
2d9dcffd5d phy: fsl-imx8mq-usb: introduce per-variant driver data structure
Replace direct use of phy_ops pointer in of_device_id .data with a
dedicated imx8mq_usb_phy_drvdata structure. This allows per-variant
driver data to be extended in the future without changing the match
table.

Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
Link: https://patch.msgid.link/20260731-imx8mp-usb-phy-improvement-v8-5-2ec8d6b3854d@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-08-06 21:15:08 +05:30
Xu Yang
01e9e84a43 phy: fsl-imx8mq-usb: add control register regmap
The CR port is a simple 16-bit data/address parallel port that is
accessed through 32-bit MMIO registers for on-chip access to the
control registers inside the USB 3.0 femtoPHY. Add control register
regmap and export these registers by debugfs to help PHY's diagnostic.

Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
Link: https://patch.msgid.link/20260731-imx8mp-usb-phy-improvement-v8-4-2ec8d6b3854d@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-08-06 21:15:08 +05:30
Xu Yang
56eec5d966 phy: fsl-imx8mq-usb: add runtime PM support
Add runtime PM support to ensure the PHY clocks are properly gated
when the PHY is not in use, reducing power consumption.

Clock management is moved from power_on()/power_off() callbacks into
the runtime_resume()/runtime_suspend() callbacks respectively. The PHY
subsystem core already holds a runtime PM reference around init() and
power_on/off() calls, so no explicit clock handling is needed there.

Use devm_clk_get_enabled() and devm_clk_get_optional_enabled() in
probe() to keep clocks enabled initially. This ensures the PHY remains
functional when CONFIG_PM is disabled, where runtime suspend/resume
callbacks are never invoked.

In tca_blk_typec_switch_set(), replace the manual clk_prepare_enable()
/ clk_disable_unprepare() pair with PM_RUNTIME_ACQUIRE_IF_ENABLED() to
guard register access against a concurrently suspended PHY.

Move devm_regulator_get() before pm_runtime_enable() to avoid having
to clean up runtime PM state on regulator acquisition failure.

In remove(), call pm_runtime_get_sync() before pm_runtime_disable() to
ensure the PHY is resumed and clocks are enabled before the devres
teardown disables them.

Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20260731-imx8mp-usb-phy-improvement-v8-3-2ec8d6b3854d@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-08-06 21:15:08 +05:30
Xu Yang
2602012b8c phy: fsl-imx8mq-usb: set usb phy to be wakeup capable
Set PHY wakeup capable because this PHY supports remote wakeup function.

Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
Link: https://patch.msgid.link/20260731-imx8mp-usb-phy-improvement-v8-2-2ec8d6b3854d@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-08-06 21:15:08 +05:30
Felix Gu
87a1805b1c phy: fsl-imx8mq-usb: fix typec switch leak on probe error path
If probe fails after imx95_usb_phy_get_tca() succeeds, the typec
switch leaks because the only cleanup path was in .remove(), which
never runs on probe failure.

Use devm_add_action_or_reset() so the switch is cleaned up on both
probe failure and driver removal. The imx95_usb_phy_put_tca() is no
longer needed, it will be removed in .remove() too.

Fixes: b58f0f86fd ("phy: fsl-imx8mq-usb: add tca function driver for imx95")
Cc: stable@vger.kernel.org
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Xu Yang <xu.yang_2@nxp.com>
Signed-off-by: Felix Gu <ustc.gu@gmail.com>
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
Link: https://patch.msgid.link/20260731-imx8mp-usb-phy-improvement-v8-1-2ec8d6b3854d@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-08-06 21:15:08 +05:30
Esteban Urrutia
9583243a52 phy: qcom: qmp-combo: Add SM8475 support
Has been tested with the following capabilities:
- USB Type-C at 10Gb/s
- DP Alt Mode, using HBR2
- USB Type-C at 480Mb/s + DP Alt Mode, using HBR2

RX and PCS USB tables had to be added, while serdes, TX and PCS tables were
reused from other SoCs.

Some SoCs such as SAR2130P, SM7550, SM7635 and SM8475 use 4nm-v1 PLLs.
For SM8475, trying to use qmp_v6_dp_serdes_tbl structs (which are for
4nm-v1.1 PLLs) causes link training to fail because of ref clock
differences, which in turn makes these structs differ.
Add structs for v1 PLLs as well.

Signed-off-by: Esteban Urrutia <esteuwu@proton.me>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://patch.msgid.link/20260804-sm8475-bup-usbss-v3-2-9a5b9ebf62de@proton.me
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-08-06 21:11:39 +05:30
Esteban Urrutia
f8bb67fa36 dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Add SM8475 QMP PHY
SM8450 init sequence for this PHY varies significantly and can't be used in
SM8475.
Add bindings for the PHY found in this SoC.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Esteban Urrutia <esteuwu@proton.me>
Link: https://patch.msgid.link/20260804-sm8475-bup-usbss-v3-1-9a5b9ebf62de@proton.me
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-08-06 21:11:39 +05:30
Biju Das
49c9b71b45 phy: renesas: phy-rcar-gen3-usb2: Fix devm action registration for disabled VBUS regulator
devm_regulator_get_exclusive() initialises the regulator with
enable_count = 1, requiring the consumer to disable it before release.

The devm disable action was previously only registered when the caller
explicitly requested enable, so when the regulator was left in its initial
enabled state without an explicit enable call, the cleanup path skipped
decrementing enable_count, triggering a WARN_ON during regulator
release on device removal.

Fix this by always registering the devm disable action based on the actual
enabled state via regulator_is_enabled(), regardless of whether the
caller requested an explicit enable. This covers both the explicitly
enabled case and the initial state set by devm_regulator_get_exclusive().

Fixes: 24843404ef ("phy: renesas: phy-rcar-gen3-usb2: Control VBUS for RZ/G2L SoCs")
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://patch.msgid.link/20260806102236.149159-9-biju.das.jz@bp.renesas.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-08-06 21:08:38 +05:30
Biju Das
881f6b6f4c phy: renesas: phy-rcar-gen3-usb2: Add RZ/G3L support
Add renesas,usb2-phy-r9a08g046 to the OF match table, reusing
rz_g3s_phy_usb2_data as the PHY configuration is shared with RZ/G3S.

While the PHY data is shared, RZ/G3L differs from RZ/G3S in that it has
two OTG controllers, OTG interrupts on port 2, and a controllable
OTG_PERI bit in COMMCTRL for host/device switching on the port 2 USB
controller, which is fixed to host-only on RZ/G3S.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://patch.msgid.link/20260806102236.149159-8-biju.das.jz@bp.renesas.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-08-06 21:08:38 +05:30
Biju Das
e6c3be558d dt-bindings: phy: renesas,usb2-phy: Document RZ/G3L PHY bindings
Add device tree binding support for the RZ/G3L (r9a08g046) USB2 PHY.
The RZ/G3L USB PHY is almost identical to the RZ/G3S USB PHY, the
difference being 2 OTG blocks on RZ/G3L compared to 1 on RZ/G3S.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://patch.msgid.link/20260806102236.149159-7-biju.das.jz@bp.renesas.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-08-06 21:08:38 +05:30
Ronak Raheja
eca0e717aa phy: qualcomm: qmp-combo: Add support for Hawi SoC
Add support for the USB3-DP combo PHY found on Hawi platform.

The QMP PHY for Hawi uses QSERDES V10 register layouts. Add the required
PHY sequences from the hardware programming guide and new V10 register
header files. Also add a new v10 offset structure to incorporate the new
COM AON register module.

Signed-off-by: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
Link: https://patch.msgid.link/20260803091441.3040830-5-mukesh.ojha@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-08-06 21:05:05 +05:30
Ronak Raheja
7abc2c575d dt-bindings: phy: qcom,m31-eusb2-phy: Document M31 eUSB2 PHY for Hawi
Document the M31 eUSB2 PHY for Hawi which handles the USB2 path. Use
fallback to indicate the compatibility of the M31 eUSB2 PHY on the Hawi
with that on the SM8750.

Signed-off-by: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
Link: https://patch.msgid.link/20260803091441.3040830-3-mukesh.ojha@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-08-06 21:05:05 +05:30
Ronak Raheja
19d8eca1be dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Add Hawi QMP PHY
Document the Hawi compatible string for the QMP combo PHY.

Hawi uses a new QSERDES V10 register layout with a new COM AON module
and hardware-specific PHY init sequences compared to previous targets,
requiring a dedicated compatible string.

Signed-off-by: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
Link: https://patch.msgid.link/20260803091441.3040830-2-mukesh.ojha@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-08-06 21:05:05 +05:30
Kathiravan Thirumoorthy
ee6aa0f01d phy: qcom: qmp-pcie: Add IPQ9650 PCIe PHY support
Add support for the IPQ9650 platform, which includes three Gen3 x2 PCIe
controllers and two Gen3 x1 PCIe controllers. The PHY instances require
the on-chip refgen supply.

Add the IPQ9650 Gen3 x1 and x2 QMP PCIe PHY configurations along with
the refgen regulator supply. Note that an on-chip LDO, driven by the SoC
CX, supplies the PHY voltages without requiring software control. Note
that IPQ9650 does not support CX power collapse or rail scaling.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
Link: https://patch.msgid.link/20260710-ipq9650_pcie_phy-v3-2-ef6018818d33@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-07-22 21:13:32 +05:30
Kathiravan Thirumoorthy
7218d17e76 dt-bindings: phy: qcom,ipq8074-qmp-pcie: document IPQ9650 QMP PCIe PHYs
Document the single-lane and dual-lane QMP PCIe PHYs found on the
IPQ9650 SoC.

Unlike the PHYs in the other supported IPQ SoCs, the IPQ9650 PHYs require
the on-chip refgen supply to power up. Add the refgen-supply property
and require it only for the IPQ9650 compatibles.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
Link: https://patch.msgid.link/20260710-ipq9650_pcie_phy-v3-1-ef6018818d33@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-07-22 21:13:32 +05:30
Radhey Shyam Pandey
02f447eabd MAINTAINERS: Add Radhey Shyam Pandey as ZynqMP PHY maintainer
I am maintaining phy-zynqmp driver in xilinx tree and would like to
maintain it in the mainline kernel as well. Hence adding myself as a
maintainer.

Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Link: https://patch.msgid.link/20260627162233.2803425-1-radhey.shyam.pandey@amd.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-07-22 20:44:32 +05:30
Varadarajan Narayanan
3c25d3d974 phy: qcom-qmp-pcie: Add support for ipq5210 PCIe phys
Add support for a PCIe phys found on Qualcomm ipq5210 platform.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
Link: https://patch.msgid.link/20260721-pcie-phy-v5-2-8d403ef7e780@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-07-22 13:53:06 +05:30
Varadarajan Narayanan
9bc7329891 dt-bindings: phy: qcom,ipq8074-qmp-pcie: Document the ipq5210 QMP PCIe PHY
The ipq5210 has one dual lane and one single lane PCIe phy.

The dual lane phy is similar to the dual lane phy present in ipq9574. Hence
qcom,ipq5210-qmp-gen3x2-pcie-phy is documented with ipq9574's dual lane phy
as fallback compatible.

The single lane phy (qcom,ipq5210-qmp-gen3x1-pcie-phy) is documented as
specific compatible as it uses a combination of its own initialization
tables and some of the existing tables.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
Link: https://patch.msgid.link/20260721-pcie-phy-v5-1-8d403ef7e780@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-07-22 13:53:06 +05:30
Krishna Kurapati
edb7772bb3 phy: qcom: qmp-usbc: Add qmp configuration for Shikra
Add init sequence and phy configuration for the Super Speed port on Shikra
SoC. Also since Shikra uses 3 resets, add support for the third reset and
configure Shikra platform data to use 3 resets.

Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://patch.msgid.link/20260712-usb-shikra-phy-v6-v6-4-1b3e51bf1541@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-07-22 13:51:49 +05:30
Krishna Kurapati
346121aed2 phy: qcom-qusb2: Add support for Shikra
Add init sequence and phy configuration for Shikra. Since the init
sequence is same as that of QCS615, reuse the existing init table in
Shikra.

Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://patch.msgid.link/20260712-usb-shikra-phy-v6-v6-3-1b3e51bf1541@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-07-22 13:51:48 +05:30
Krishna Kurapati
49e3105844 dt-bindings: phy: qcs615-qmp-usb3dp: Add support for Shikra SoC
Declare the USB-C QMP PHY present on the Qualcomm Shikra SoC. Shikra uses
3 resets to be programmed before initialising the phy. As per the hardware
documentation, the third reset is PHY_PRIM_SP0_BCR, hence naming it "phy".

Also, add remote endpoints and orientation switch support for getting
Type-C orientation information.

Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://patch.msgid.link/20260712-usb-shikra-phy-v6-v6-2-1b3e51bf1541@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-07-22 13:50:45 +05:30
Krishna Kurapati
8d3f1d5ce0 dt-bindings: phy: qcom,qusb2: Document QUSB2 Phy for Shikra
Update dt-bindings to add Shikra to QUSB2 Phy list. Shikra SoC
has two High Speed QUSB2 Phys.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
Link: https://patch.msgid.link/20260712-usb-shikra-phy-v6-v6-1-1b3e51bf1541@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-07-22 13:50:45 +05:30
Vladimir Oltean
1e0c8d5066 phy: lynx-10g: fix lynx_10g_pccr_val_enabled()
The intention of the code is to extract the PCCR8_SGMIIa_CFG field out
of the "pccr" value, not to create a new value with the PCCR8_SGMIIa_CFG
field set to the "pccr" value.

Since FIELD_GET() is implemented as ((reg) & (mask)) >> __bf_shf(mask)
and FIELD_PREP() as (val) << __bf_shf(mask)) & (mask) and since "mask"
is GENMASK(2, 0), in practice there is no functional difference between
FIELD_GET() and FIELD_PREP(). But FIELD_GET() is logically the correct
helper.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Link: https://patch.msgid.link/20260612125731.133330-1-vladimir.oltean@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-07-22 13:38:07 +05:30
Krishna Chaitanya Chundru
910b828b22 phy: qcom: qmp-pcie: Skip PHY reset if already up
If the bootloader has already powered up the PCIe PHY, performing a
full reset and waiting for the PHY to come up again adds unnecessary
delay during boot.

Extend the existing skip_init handling by introducing a skip_reset
condition. When skip_init is active and the PHY status indicates that
the PHY is already operational, skip asserting and deasserting the
no-csr reset while still enabling the required resources during
power-on.

This allows reusing the bootloader-initialized PHY state and avoids
redundant PHY reinitialization and PCIe link retraining, which can
add hundred's of milliseconds of delay.

This relies on the assumption that when skip_init is enabled and the
PHY is reported as up, the bootloader has already configured the PHY
correctly and the link is in a usable state.

Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Tested-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Link: https://patch.msgid.link/20260709-link_retain-v3-1-81a9d187bb61@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-07-20 16:51:28 +05:30
AngeloGioacchino Del Regno
2ec9c210c1 phy: mediatek: Add support for MT8196 MIPI DSI PHY
Add support for the MIPI DSI PHY found in the MediaTek MT8196 SoC
and its variants.
This PHY has a different register layout and provides support for
more hardware features compared to the previous generation.

This initial driver only adds support for basic functionality that
is necessary to drive MIPI DSI displays as a D-PHY.

Feature additions like lane-swap, DPHY/CPHY switching, dual-port,
and others, may be done in the future.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://patch.msgid.link/20260713103805.23030-3-angelogioacchino.delregno@collabora.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-07-20 16:42:15 +05:30
AngeloGioacchino Del Regno
215cd5def8 dt-bindings: phy: mediatek,dsi-phy: Add support for MT8196
Add support for the MediaTek Kompanio Ultra (MT8196) SoC: this
chip features a DSI PHY that is similar to the one found in the
MT8183 SoC, but is a new (incremental) revision with a different
register layout.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://patch.msgid.link/20260713103805.23030-2-angelogioacchino.delregno@collabora.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-07-20 16:42:14 +05:30
Inochi Amaoto
7a099760ea phy: spacemit: Add USB3/PCIe comb PHY driver for Spacemit K3
The comb PHY on K3 requires to configure a syscon device for the
right mux configuration. And it requires calibration before any
usage.

Add USB3/PCIe comb PHY driver for Spacemit K3.

Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Tested-by: Aurelien Jarno <aurelien@aurel32.net>
Link: https://patch.msgid.link/20260703021024.495433-3-inochiama@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-07-20 16:39:26 +05:30
Inochi Amaoto
013004374b dt-bindings: phy: Add Spacemit K3 USB3/PCIe comb phy support
The USB3/PCIe comb PHY on the K3 is a complex PHY group that
can provide multiple phy for both PCIe and USB controller.
Its mux configuration is controlled by the APMU syscon device.

Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20260703021024.495433-2-inochiama@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-07-20 16:39:26 +05:30
Can Peng
97bed336f6 phy: starfive: Fix runtime PM cleanup in JH7110 DPHY RX probe
stf_dphy_probe() enables runtime PM before registering the PHY provider.
If devm_of_phy_provider_register() fails, probe returns with runtime PM
still enabled.

The driver also has no remove callback, so runtime PM is left enabled
on driver unbind after a successful probe.

Use devm_pm_runtime_enable() so runtime PM is disabled automatically
on later probe failures and on driver unbind.

Fixes: f8aa660841 ("phy: starfive: Add mipi dphy rx support")
Signed-off-by: Can Peng <pengcan@kylinos.cn>
Reviewed-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Link: https://patch.msgid.link/20260718090054.444513-3-pengcan@kylinos.cn
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-07-20 16:25:58 +05:30
Can Peng
f40b0241f3 phy: starfive: Fix runtime PM cleanup in JH7110 DPHY TX probe
stf_dphy_probe() enables runtime PM before getting the clock and
reset controls, creating the PHY and registering the PHY provider. If
any of those steps fails, probe returns with runtime PM still enabled.

The driver also has no remove callback, so runtime PM is left enabled
on driver unbind after a successful probe.

Use devm_pm_runtime_enable() so runtime PM is disabled automatically
on later probe failures and on driver unbind.

Fixes: d3ab795533 ("phy: starfive: Add mipi dphy tx support")
Signed-off-by: Can Peng <pengcan@kylinos.cn>
Reviewed-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Link: https://patch.msgid.link/20260718090054.444513-2-pengcan@kylinos.cn
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-07-20 16:25:58 +05:30
Matthew Leung
9ef4e52091 phy: qcom: qmp-pcie: Add QMP PCIe PHY support for Hawi
Add the QMP PCIe PHY support for the Gen3 x2 and Gen4 x1 PHY found on
the Hawi platform.

Signed-off-by: Matthew Leung <matthew.leung@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://patch.msgid.link/20260707-hawi-phy-pcie-v4-4-8d9cc6324947@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-07-20 16:21:35 +05:30
Matthew Leung
fdfe6417e2 phy: qcom-qmp: Add v10.60 register offsets
Hawi SoC uses v10.60 register definitions for PCIe Gen4 x1. Add the new
register offset headers for all four sub-blocks:

 - QSERDES-COM offsets
 - QSERDES TX/RX offsets
 - PCS offsets
 - PCS PCIe-specific offsets

Signed-off-by: Matthew Leung <matthew.leung@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://patch.msgid.link/20260707-hawi-phy-pcie-v4-3-8d9cc6324947@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-07-20 16:21:35 +05:30
Matthew Leung
0696cc735d phy: qcom-qmp: Add v10 register offsets
Hawi SoC uses v10 register definitions for PCIe Gen3 x2. Add the new
register offset headers for all four sub-blocks:

 - QSERDES-COM offsets
 - QSERDES TX/RX offsets
 - PCS offsets
 - PCS PCIe-specific offsets

Signed-off-by: Matthew Leung <matthew.leung@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://patch.msgid.link/20260707-hawi-phy-pcie-v4-2-8d9cc6324947@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-07-20 16:21:35 +05:30
Matthew Leung
d15224492d dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add Hawi compatibles
Document the compatibles for the Gen3 x2 and Gen4 x1 QMP PCIe PHYs found
on the Hawi platform.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Matthew Leung <matthew.leung@oss.qualcomm.com>
Link: https://patch.msgid.link/20260707-hawi-phy-pcie-v4-1-8d9cc6324947@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-07-20 16:21:35 +05:30
Linus Torvalds
dc59e4fea9 Linux 7.2-rc1 v7.2-rc1 2026-06-28 12:01:31 -07:00
Linus Torvalds
0716f9b933 Merge tag 'ntb-7.2' of https://github.com/jonmason/ntb
Pull NTB updates from Jon Mason:
 "An EPF bug fix to prevent an invalid unmap during device removal,
  along with documentation fixes and minor AMD driver cleanups"

* tag 'ntb-7.2' of https://github.com/jonmason/ntb:
  ntb: amd: Use named initializer for pci_device_id::driver_data
  NTB: fix kernel-doc warnings in ntb.h
  NTB: epf: Avoid pci_iounmap() with offset when PEER_SPAD and CONFIG share BAR
  ntb_hw_amd: Fix incorrect debug message in link disable path
2026-06-28 07:46:12 -07:00
Linus Torvalds
8b69c04758 Merge tag 'input-for-v7.2-rc0-2' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
Pull more input updates from Dmitry Torokhov:

 - Updates to Synaptics RMI4 driver to fix potential OOB accesses in F30
   and F3A keymap handling

 - A workaround in Synaptics RMI4 to tolerate buggy firmware on some
   touchpads (e.g. ThinkPad T14 Gen 1) that report incomplete register
   descriptor structures, preventing probe failures

 - A revert of an incorrect register descriptor address calculation in
   Synaptics RMI4 driver

 - A fix for a regression in HP GSC PS/2 (gscps2) driver where the
   receive buffer write index was not advanced, leaving keyboard and
   mouse unusable.

* tag 'input-for-v7.2-rc0-2' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input:
  Input: gscps2 - advance receive buffer write index
  Input: rmi4 - tolerate short register descriptor structure
  Revert "Input: rmi4 - fix register descriptor address calculation"
  Input: synaptics-rmi4 - bound the F30 keymap to the GPIO/LED count
  Input: synaptics-rmi4 - bound the F3A keymap to the GPIO count
2026-06-28 04:40:05 -07:00
Linus Torvalds
780d569e6c Merge tag 'pwm/for-7.2-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/ukleinek/linux
Pull pwm fixes from Uwe Kleine-König:
 "Two more fixes that I managed to put into the public branch merged
  into next before my first pull request but missed to include them in
  it.

  The first change is a relevant change that fixes misconfigurations due
  to a variable overflow. The second is only cosmetic but very obviously
  an improvement"

* tag 'pwm/for-7.2-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/ukleinek/linux:
  pwm: rzg2l-gpt: Add missing newlines to dev_err_probe() messages
  pwm: rzg2l-gpt: Fix period_ticks type from u32 to u64
2026-06-27 13:48:12 -07:00
Linus Torvalds
f21df87320 Merge tag 'fbdev-for-7.2-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/linux-fbdev
Pull more fbdev updates from Helge Deller:
 "Fixes for generic fbdev & fbcon code for the handling of modelists
  and preventing a potential NULL ptr dereference in the console code.

  Fix missed cleanups in the error path of various fbdev drivers.

  And Uwe Kleine-König contributed a cleanup patch to use named
  initializers in the vga16fb driver"

* tag 'fbdev-for-7.2-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/linux-fbdev:
  fbdev: Fix fb_new_modelist to prevent null-ptr-deref in fb_videomode_to_var
  fbcon: fix NULL pointer dereference for a console without vc_data
  fbdev: fix use-after-free in store_modes()
  fbdev: viafb: return an error when DMA copy times out
  fbdev: goldfishfb: fail pan display on base-update timeout
  fbdev: fbcon: fix out-of-bounds read in err_out of fbcon_do_set_font()
  fbdev: pm2fb: unwind WC setup on probe failure
  fbdev: vga16fb: Drop unused assignment of platform_device_id driver data
2026-06-27 12:52:20 -07:00
Linus Torvalds
14923571e7 Merge tag 'sound-fix-7.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound
Pull sound fixes from Takashi Iwai:
 "A collection of small bug fixes accumulated over the last week.
  Most are device-specific fixes while there are a few core fixes as
  well.

  Here are the highlights:

  ALSA Core:
   - A fix for an uninitialised heap leak in ALSA sequencer core
   - A fix for error handling/resource leak in compress-offload API

  USB-audio:
   - A teardown-ordering fix in USB MIDI 2.0 to prevent use-after-free
   - Bounds and length checks for packet data in Native Instruments
     caiaq / Traktor Kontrol input parsers
   - Avoidance of expensive kobject path lookups in DualSense controller
     matches
   - Robustness/memory leak fixes for Qualcomm USB offload driver
   - Focusrite Control Protocol (FCP) NULL-pointer dereference fix and a
     new device quirk (ISA C8X)
   - Device-specific quirks for Yamaha CDS3000 and SC13A

  HD-Audio:
   - A bunch of quirks and mute/mic-mute LED fixups for various laptops
     (Acer, Clevo, Lenovo, HP)

  ASoC & SoundWire:
   - Avoid failing card registration if the device_link creation fails
   - A workaround for SoundWire randconfig build failures by making
     helper functions static inline
   - Corrected MCLK reference validation for CS530x codecs
   - Clean up of untested, problematic guard() macro replacements in
     Rockchip SAI driver
   - Fix for eDMA maxburst misalignment with channel count in Freescale
     ASRC
   - Miscellaneous hardware-specific fixes (qcom, rt5650, tlv320aic3x,
     tas2781/3)

  Others:
   - Bounds and length checks for packet data in Apple iSight"

* tag 'sound-fix-7.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound: (46 commits)
  ALSA: FCP: Fix NULL pointer dereference in interface lookup
  ALSA: hda/realtek: Update Acer Nitro ANV15-41 quirk to enable mute LED
  ASoC: fsl_asrc_dma: fix eDMA maxburst misalignment with channel count
  ASoC: codecs: pcm512x: only print info once on no sclk
  ASoC: tas2781: Update default register address to TAS2563
  ALSA: firewire: isight: bound the sample count to the packet payload
  ALSA: usb-audio: qcom: Free QMI handle
  ALSA: hda: Add Lenovo Legion 7i 16IAX7 17AA3874 quirk
  ALSA: usb-audio: avoid kobject path lookup in DualSense match
  ALSA: hda/realtek: Add quirk for Acer Nitro ANV15-41
  ASoC: soc-core: Don't fail if device_link could not be created
  ASoC: rockchip: rockchip_sai: #include <linux/platform_device.h> explicitly
  ALSA: seq: Fix uninitialised heap leak in snd_seq_event_dup()
  ASoC: rt5575: Use __le32 for SPI burst write address
  ASoC: tas2783: Update loaded firmware names to linux-firmware 20260519
  ASoC: SDCA: Validate written enum value in ge_put_enum_double()
  ASoC: realtek: Add back local call to sdw_show_ping_status()
  ASoC: ti: Add back local call to sdw_show_ping_status()
  ASoC: max98373: Add back local call to sdw_show_ping_status()
  ASoC: es9356: Add back local call to sdw_show_ping_status()
  ...
2026-06-27 12:15:23 -07:00
Linus Torvalds
4bf54e4752 Merge tag 'i2c-fixes-7.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/andi.shyti/linux
Pull i2c fixes from Andi Shyti:

 - i801: fix error path in smbus transfer

 - mpc: fix timeout calculation

* tag 'i2c-fixes-7.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/andi.shyti/linux:
  i2c: i801: fix hardware state machine corruption in error path
  i2c: mpc: Fix timeout calculations
2026-06-27 11:33:30 -07:00
Linus Torvalds
da7ca04e33 Merge tag 'rtc-7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux
Pull RTC updates from Alexandre Belloni:
 "Most of the work and improvements are for features of the m41t93.

  The ds1307 also gets support for OSF (Oscillator Stop Flag) for
  new variants.

  The pcap driver is being removed as the Motorola EZX support was
  removed a while ago.

  Subsystem:
   - add rtc_read_next_alarm() to read next expiring timer

  Drivers:
   - ds1307: handle OSF for ds1337/ds1339/ds3231, add clock provider for
     ds1307, fix wday for rx8130
   - m41t93: DT support, alarm, clock provider, watchdog support
   - mv: add suspend/resume support for wakeup
   - pcap: remove driver
   - renesas-rtca3: many fixes"

* tag 'rtc-7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux: (36 commits)
  rtc: ds1307: update reference to removed CONFIG_RTC_DRV_DS1307_HWMON
  platform/x86: amd-pmc: Fix S0i3 wakeup with alarmtimer
  rtc: s35390a: fix typo in comment
  rtc: cmos: unregister HPET IRQ handler on probe failure
  rtc: ds1307: Fix off-by-one issue with wday for rx8130
  dt-bindings: rtc: ds1307: Add epson,rx8901
  rtc: bq32000: add delay between RTC reads
  rtc: m41t93: Add watchdog support
  rtc: m41t93: Add square wave clock provider support
  rtc: m41t93: Add alarm support
  rtc: m41t93: migrate to regmap api for register access
  rtc: m41t93: add device tree support
  dt-bindings: rtc: Add ST m41t93
  rtc: ds1307: add support for clock provider in ds1307
  rtc: mv: add suspend/resume support for wakeup
  rtc: aspeed: add AST2700 compatible
  dt-bindings: rtc: add ASPEED AST2700 compatible
  rtc: interface: fix typos in rtc_handle_legacy_irq() documentation
  rtc: msc313: fix NULL deref in shared IRQ handler at probe
  rtc: remove unused pcap driver
  ...
2026-06-27 11:00:18 -07:00
Linus Torvalds
6ca693ea90 Merge tag 'fscrypt-for-linus' of git://git.kernel.org/pub/scm/fs/fscrypt/linux
Pull fscrypt fixes from Eric Biggers:

 - Fix a bug where in a specific edge case, file contents en/decryption
   could be done with the wrong data unit size

 - Fix the data structure used for keeping track of users that have
   added an fscrypt key to be a simple list instead of a 'struct key'
   keyring

   This fixes issues such as a lockdep report found by syzbot and
   possible unintended interactions with the keyctl() system calls

* tag 'fscrypt-for-linus' of git://git.kernel.org/pub/scm/fs/fscrypt/linux:
  fscrypt: Replace mk_users keyring with simple list
  fscrypt: Fix key setup in edge case with multiple data unit sizes
2026-06-27 09:20:16 -07:00
Xu Rao
d86d4f8cbb Input: gscps2 - advance receive buffer write index
Commit 44f9200699 ("Input: gscps2 - use guard notation when
acquiring spinlock") moved the receive loop into gscps2_read_data()
and gscps2_report_data().

While moving the code, it preserved the writes to
buffer[ps2port->append], but omitted the following producer index
update from the original loop:

	ps2port->append = (ps2port->append + 1) & BUFFER_SIZE;

As a result, append never advances. Since gscps2_report_data() only
reports bytes while act != append, the receive buffer always appears
empty and no keyboard or mouse data reaches the serio core.

Restore the omitted index update.

Fixes: 44f9200699 ("Input: gscps2 - use guard notation when acquiring spinlock")
Cc: stable@vger.kernel.org # 6.13+
Signed-off-by: Xu Rao <raoxu@uniontech.com>
Link: https://patch.msgid.link/460B5655BA580C60+20260624094739.850306-1-raoxu@uniontech.com
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2026-06-26 22:42:56 -07:00