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phy: qcom-qmp: Add v10 register offsets

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Hawi SoC uses v10 register definitions for PCIe Gen3 x2. Add the new
register offset headers for all four sub-blocks:

 - QSERDES-COM offsets
 - QSERDES TX/RX offsets
 - PCS offsets
 - PCS PCIe-specific offsets

Signed-off-by: Matthew Leung <matthew.leung@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://patch.msgid.link/20260707-hawi-phy-pcie-v4-2-8d9cc6324947@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Matthew Leung
2026-07-07 20:32:47 +00:00
committed by Vinod Koul
parent d15224492d
commit 0696cc735d
6 changed files with 142 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
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@@ -40,6 +40,7 @@
#include "phy-qcom-qmp-qserdes-com-v8.h"
#include "phy-qcom-qmp-pcs-pcie-v8.h"
#include "phy-qcom-qmp-qserdes-txrx-pcie-v8.h"
#include "phy-qcom-qmp-pcs-pcie-v10.h"
#define PHY_INIT_COMPLETE_TIMEOUT 10000

18
drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v10.h Normal file
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@@ -0,0 +1,18 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#ifndef QCOM_PHY_QMP_PCS_PCIE_V10_H_
#define QCOM_PHY_QMP_PCS_PCIE_V10_H_
/* Only for QMP V10 PHY - PCIE PCS registers */
#define QPHY_PCIE_V10_PCS_POWER_STATE_CONFIG2 0x00c
#define QPHY_PCIE_V10_PCS_POWER_STATE_CONFIG4 0x014
#define QPHY_PCIE_V10_PCS_ENDPOINT_REFCLK_DRIVE 0x020
#define QPHY_PCIE_V10_PCS_OSC_DTCT_ACTIONS 0x094
#define QPHY_PCIE_V10_PCS_EQ_CONFIG1 0x0a4
#define QPHY_PCIE_V10_PCS_RXEQEVAL_TIME 0x0f4
#define QPHY_PCIE_V10_PCS_POWER_STATE_CONFIG6 0x0f8
#endif

22
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v10.h Normal file
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@@ -0,0 +1,22 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#ifndef QCOM_PHY_QMP_PCS_V10_H_
#define QCOM_PHY_QMP_PCS_V10_H_
/* Only for QMP V10 PHY - PCIe PCS registers */
#define QPHY_V10_PCS_SW_RESET 0x000
#define QPHY_V10_PCS_PCS_STATUS1 0x014
#define QPHY_V10_PCS_POWER_DOWN_CONTROL 0x040
#define QPHY_V10_PCS_START_CONTROL 0x044
#define QPHY_V10_PCS_REFGEN_REQ_CONFIG1 0x0dc
#define QPHY_V10_PCS_G12S1_TXDEEMPH_M6DB 0x168
#define QPHY_V10_PCS_G3S2_PRE_GAIN 0x170
#define QPHY_V10_PCS_RX_SIGDET_LVL 0x188
#define QPHY_V10_PCS_RATE_SLEW_CNTRL1 0x198
#define QPHY_V10_PCS_PCS_TX_RX_CONFIG 0x1d0
#define QPHY_V10_PCS_EQ_CONFIG2 0x1e4
#endif

49
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v10.h Normal file
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@@ -0,0 +1,49 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#ifndef QCOM_PHY_QMP_QSERDES_COM_V10_H_
#define QCOM_PHY_QMP_QSERDES_COM_V10_H_
/* Only for QMP V10 PHY - QSERDES COM registers */
#define QSERDES_V10_COM_SSC_STEP_SIZE1_MODE1 0x00
#define QSERDES_V10_COM_SSC_STEP_SIZE2_MODE1 0x04
#define QSERDES_V10_COM_CP_CTRL_MODE1 0x10
#define QSERDES_V10_COM_PLL_RCTRL_MODE1 0x14
#define QSERDES_V10_COM_PLL_CCTRL_MODE1 0x18
#define QSERDES_V10_COM_CORECLK_DIV_MODE1 0x1c
#define QSERDES_V10_COM_LOCK_CMP1_MODE1 0x20
#define QSERDES_V10_COM_LOCK_CMP2_MODE1 0x24
#define QSERDES_V10_COM_DEC_START_MODE1 0x28
#define QSERDES_V10_COM_DIV_FRAC_START1_MODE1 0x30
#define QSERDES_V10_COM_DIV_FRAC_START2_MODE1 0x34
#define QSERDES_V10_COM_DIV_FRAC_START3_MODE1 0x38
#define QSERDES_V10_COM_HSCLK_SEL_1 0x3c
#define QSERDES_V10_COM_SSC_STEP_SIZE1_MODE0 0x60
#define QSERDES_V10_COM_SSC_STEP_SIZE2_MODE0 0x64
#define QSERDES_V10_COM_CP_CTRL_MODE0 0x70
#define QSERDES_V10_COM_PLL_RCTRL_MODE0 0x74
#define QSERDES_V10_COM_PLL_CCTRL_MODE0 0x78
#define QSERDES_V10_COM_LOCK_CMP1_MODE0 0x80
#define QSERDES_V10_COM_LOCK_CMP2_MODE0 0x84
#define QSERDES_V10_COM_DEC_START_MODE0 0x88
#define QSERDES_V10_COM_DIV_FRAC_START1_MODE0 0x90
#define QSERDES_V10_COM_DIV_FRAC_START2_MODE0 0x94
#define QSERDES_V10_COM_DIV_FRAC_START3_MODE0 0x98
#define QSERDES_V10_COM_BG_TIMER 0xbc
#define QSERDES_V10_COM_SSC_EN_CENTER 0xc0
#define QSERDES_V10_COM_SSC_PER1 0xcc
#define QSERDES_V10_COM_SSC_PER2 0xd0
#define QSERDES_V10_COM_CLK_ENABLE1 0xe0
#define QSERDES_V10_COM_SYS_CLK_CTRL 0xe4
#define QSERDES_V10_COM_PLL_IVCO 0xf4
#define QSERDES_V10_COM_SYSCLK_EN_SEL 0x110
#define QSERDES_V10_COM_LOCK_CMP_EN 0x120
#define QSERDES_V10_COM_VCO_TUNE_MAP 0x140
#define QSERDES_V10_COM_CLK_SELECT 0x164
#define QSERDES_V10_COM_CORE_CLK_EN 0x170
#define QSERDES_V10_COM_CMN_CONFIG_1 0x174
#define QSERDES_V10_COM_ADDITIONAL_MISC_3 0x1bc
#endif

47
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v10.h Normal file
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@@ -0,0 +1,47 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V10_H_
#define QCOM_PHY_QMP_QSERDES_TXRX_V10_H_
#define QSERDES_V10_TX_RES_CODE_LANE_OFFSET_TX 0x03c
#define QSERDES_V10_TX_RES_CODE_LANE_OFFSET_RX 0x040
#define QSERDES_V10_TX_LANE_MODE_1 0x084
#define QSERDES_V10_TX_LANE_MODE_3 0x08c
#define QSERDES_V10_TX_LANE_MODE_4 0x090
#define QSERDES_V10_TX_LANE_MODE_5 0x094
#define QSERDES_V10_TX_PI_QEC_CTRL 0x0e4
#define QSERDES_V10_RX_UCDR_FO_GAIN 0x008
#define QSERDES_V10_RX_UCDR_SO_GAIN 0x014
#define QSERDES_V10_RX_UCDR_SB2_THRESH1 0x04c
#define QSERDES_V10_RX_UCDR_SB2_THRESH2 0x050
#define QSERDES_V10_RX_TX_ADAPT_PRE_THRESH1 0x0c4
#define QSERDES_V10_RX_TX_ADAPT_PRE_THRESH2 0x0c8
#define QSERDES_V10_RX_TX_ADAPT_POST_THRESH 0x0cc
#define QSERDES_V10_RX_VGA_CAL_CNTRL2 0x0d8
#define QSERDES_V10_RX_GM_CAL 0x0dc
#define QSERDES_V10_RX_RX_IDAC_TSETTLE_LOW 0x0f8
#define QSERDES_V10_RX_SIGDET_ENABLES 0x118
#define QSERDES_V10_RX_SIGDET_CNTRL 0x11c
#define QSERDES_V10_RX_RX_MODE_00_LOW 0x15c
#define QSERDES_V10_RX_RX_MODE_00_HIGH 0x160
#define QSERDES_V10_RX_RX_MODE_00_HIGH2 0x164
#define QSERDES_V10_RX_RX_MODE_00_HIGH3 0x168
#define QSERDES_V10_RX_RX_MODE_00_HIGH4 0x16c
#define QSERDES_V10_RX_RX_MODE_01_LOW 0x170
#define QSERDES_V10_RX_RX_MODE_01_HIGH 0x174
#define QSERDES_V10_RX_RX_MODE_01_HIGH2 0x178
#define QSERDES_V10_RX_RX_MODE_01_HIGH3 0x17c
#define QSERDES_V10_RX_RX_MODE_01_HIGH4 0x180
#define QSERDES_V10_RX_RX_MODE_10_LOW 0x184
#define QSERDES_V10_RX_RX_MODE_10_HIGH 0x188
#define QSERDES_V10_RX_RX_MODE_10_HIGH2 0x18c
#define QSERDES_V10_RX_RX_MODE_10_HIGH3 0x190
#define QSERDES_V10_RX_RX_MODE_10_HIGH4 0x194
#define QSERDES_V10_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4
#define QSERDES_V10_RX_SIGDET_CAL_TRIM 0x1f8
#endif

5
drivers/phy/qualcomm/phy-qcom-qmp.h
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@@ -36,6 +36,9 @@
#include "phy-qcom-qmp-qserdes-txrx-v8.h"
#include "phy-qcom-qmp-qserdes-lalb-v8.h"
#include "phy-qcom-qmp-qserdes-com-v10.h"
#include "phy-qcom-qmp-qserdes-txrx-v10.h"
#include "phy-qcom-qmp-qserdes-pll.h"
#include "phy-qcom-qmp-pcs-v2.h"
@@ -62,6 +65,8 @@
#include "phy-qcom-qmp-pcs-v8_50.h"
#include "phy-qcom-qmp-pcs-v10.h"
/* QPHY_SW_RESET bit */
#define SW_RESET BIT(0)
/* QPHY_POWER_DOWN_CONTROL */