mirrors/linux
2
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git synced 2026-08-31 15:22:21 -04:00
Code Issues Packages Projects Releases Wiki Activity

phy: qcom-qmp: Add v10.60 register offsets

Browse Source 
Hawi SoC uses v10.60 register definitions for PCIe Gen4 x1. Add the new
register offset headers for all four sub-blocks:

 - QSERDES-COM offsets
 - QSERDES TX/RX offsets
 - PCS offsets
 - PCS PCIe-specific offsets

Signed-off-by: Matthew Leung <matthew.leung@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://patch.msgid.link/20260707-hawi-phy-pcie-v4-3-8d9cc6324947@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Matthew Leung
2026-07-07 20:32:48 +00:00
committed by Vinod Koul
parent 0696cc735d
commit fdfe6417e2
6 changed files with 219 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
View File

@@ -41,6 +41,7 @@
#include "phy-qcom-qmp-pcs-pcie-v8.h"
#include "phy-qcom-qmp-qserdes-txrx-pcie-v8.h"
#include "phy-qcom-qmp-pcs-pcie-v10.h"
#include "phy-qcom-qmp-pcs-pcie-v10_60.h"
#define PHY_INIT_COMPLETE_TIMEOUT 10000

26
drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v10_60.h Normal file
View File

@@ -0,0 +1,26 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#ifndef QCOM_PHY_QMP_PCS_PCIE_V10_60_H_
#define QCOM_PHY_QMP_PCS_PCIE_V10_60_H_
/* Only for QMP V10_60 PHY - PCIE PCS registers */
#define QPHY_PCIE_V10_60_PCS_POWER_STATE_CONFIG2 0x00c
#define QPHY_PCIE_V10_60_PCS_TX_RX_CONFIG 0x018
#define QPHY_PCIE_V10_60_PCS_ENDPOINT_REFCLK_DRIVE 0x01c
#define QPHY_PCIE_V10_60_PCS_OSC_DTCT_ACTIONS 0x090
#define QPHY_PCIE_V10_60_PCS_EQ_CONFIG1 0x0a0
#define QPHY_PCIE_V10_60_PCS_G3_RXEQEVAL_TIME 0x0f0
#define QPHY_PCIE_V10_60_PCS_G4_RXEQEVAL_TIME 0x0f4
#define QPHY_PCIE_V10_60_PCS_G4_EQ_CONFIG5 0x108
#define QPHY_PCIE_V10_60_PCS_G4_PRE_GAIN 0x15c
#define QPHY_PCIE_V10_60_PCS_RX_MARGINING_CONFIG1 0x17c
#define QPHY_PCIE_V10_60_PCS_RX_MARGINING_CONFIG3 0x184
#define QPHY_PCIE_V10_60_PCS_RX_MARGINING_CONFIG5 0x18c
#define QPHY_PCIE_V10_60_PCS_G3_FOM_EQ_CONFIG5 0x1ac
#define QPHY_PCIE_V10_60_PCS_G4_FOM_EQ_CONFIG5 0x1c0
#define QPHY_PCIE_V10_60_PCS_POWER_STATE_CONFIG6 0x1d0
#endif

23
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v10_60.h Normal file
View File

@@ -0,0 +1,23 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#ifndef QCOM_PHY_QMP_PCS_V10_60_H_
#define QCOM_PHY_QMP_PCS_V10_60_H_
/* Only for QMP V10_60 PHY - PCIe PCS registers */
#define QPHY_V10_60_PCS_SW_RESET 0x000
#define QPHY_V10_60_PCS_PCS_STATUS1 0x014
#define QPHY_V10_60_PCS_POWER_DOWN_CONTROL 0x040
#define QPHY_V10_60_PCS_START_CONTROL 0x044
#define QPHY_V10_60_PCS_G12S1_TXDEEMPH_M6DB 0x170
#define QPHY_V10_60_PCS_G3S2_PRE_GAIN 0x178
#define QPHY_V10_60_PCS_RX_SIGDET_LVL 0x190
#define QPHY_V10_60_PCS_ELECIDLE_DLY_SEL 0x1b8
#define QPHY_V10_60_PCS_PCS_TX_RX_CONFIG1 0x1dc
#define QPHY_V10_60_PCS_PCS_TX_RX_CONFIG2 0x1e0
#define QPHY_V10_60_PCS_EQ_CONFIG4 0x1f8
#define QPHY_V10_60_PCS_EQ_CONFIG5 0x1fc
#endif

55
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v10_60.h Normal file
View File

@@ -0,0 +1,55 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#ifndef QCOM_PHY_QMP_QSERDES_COM_V10_60_H_
#define QCOM_PHY_QMP_QSERDES_COM_V10_60_H_
/* Only for QMP V10_60 PHY - QSERDES COM registers */
#define QSERDES_V10_60_COM_SSC_STEP_SIZE1_MODE1 0x00
#define QSERDES_V10_60_COM_SSC_STEP_SIZE2_MODE1 0x04
#define QSERDES_V10_60_COM_CP_CTRL_MODE1 0x10
#define QSERDES_V10_60_COM_PLL_RCTRL_MODE1 0x14
#define QSERDES_V10_60_COM_PLL_CCTRL_MODE1 0x18
#define QSERDES_V10_60_COM_CORECLK_DIV_MODE1 0x1c
#define QSERDES_V10_60_COM_LOCK_CMP1_MODE1 0x20
#define QSERDES_V10_60_COM_LOCK_CMP2_MODE1 0x24
#define QSERDES_V10_60_COM_DEC_START_MODE1 0x28
#define QSERDES_V10_60_COM_DIV_FRAC_START1_MODE1 0x30
#define QSERDES_V10_60_COM_DIV_FRAC_START2_MODE1 0x34
#define QSERDES_V10_60_COM_DIV_FRAC_START3_MODE1 0x38
#define QSERDES_V10_60_COM_HSCLK_SEL_1 0x3c
#define QSERDES_V10_60_COM_SSC_STEP_SIZE1_MODE0 0x60
#define QSERDES_V10_60_COM_SSC_STEP_SIZE2_MODE0 0x64
#define QSERDES_V10_60_COM_CP_CTRL_MODE0 0x70
#define QSERDES_V10_60_COM_PLL_RCTRL_MODE0 0x74
#define QSERDES_V10_60_COM_PLL_CCTRL_MODE0 0x78
#define QSERDES_V10_60_COM_CORECLK_DIV_MODE0 0x7c
#define QSERDES_V10_60_COM_LOCK_CMP1_MODE0 0x80
#define QSERDES_V10_60_COM_LOCK_CMP2_MODE0 0x84
#define QSERDES_V10_60_COM_DEC_START_MODE0 0x88
#define QSERDES_V10_60_COM_DIV_FRAC_START1_MODE0 0x90
#define QSERDES_V10_60_COM_DIV_FRAC_START2_MODE0 0x94
#define QSERDES_V10_60_COM_DIV_FRAC_START3_MODE0 0x98
#define QSERDES_V10_60_COM_HSCLK_HS_SWITCH_SEL_1 0x9c
#define QSERDES_V10_60_COM_BG_TIMER 0xbc
#define QSERDES_V10_60_COM_SSC_PER1 0xcc
#define QSERDES_V10_60_COM_SSC_PER2 0xd0
#define QSERDES_V10_60_COM_BIAS_EN_CLKBUFLR_EN 0xdc
#define QSERDES_V10_60_COM_CLK_ENABLE1 0xe0
#define QSERDES_V10_60_COM_SYS_CLK_CTRL 0xe4
#define QSERDES_V10_60_COM_PLL_IVCO 0xf4
#define QSERDES_V10_60_COM_SYSCLK_EN_SEL 0x110
#define QSERDES_V10_60_COM_LOCK_CMP_EN 0x120
#define QSERDES_V10_60_COM_LOCK_CMP_CFG 0x124
#define QSERDES_V10_60_COM_VCO_TUNE_MAP 0x140
#define QSERDES_V10_60_COM_CLK_SELECT 0x164
#define QSERDES_V10_60_COM_CORE_CLK_EN 0x170
#define QSERDES_V10_60_COM_CMN_CONFIG_1 0x174
#define QSERDES_V10_60_COM_CMN_MISC1 0x184
#define QSERDES_V10_60_COM_CMN_MODE 0x188
#define QSERDES_V10_60_COM_VCO_DC_LEVEL_CTRL 0x198
#define QSERDES_V10_60_COM_PLL_SPARE_FOR_ECO 0x2b4
#endif

109
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v10_60.h Normal file
View File

@@ -0,0 +1,109 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V10_60_H_
#define QCOM_PHY_QMP_QSERDES_TXRX_V10_60_H_
#define QSERDES_V10_60_TXRX_RES_CODE_LANE_OFFSET_TX 0x034
#define QSERDES_V10_60_TXRX_RES_CODE_LANE_OFFSET_RX 0x038
#define QSERDES_V10_60_TXRX_LANE_MODE_1 0x080
#define QSERDES_V10_60_TXRX_LANE_MODE_2 0x084
#define QSERDES_V10_60_TXRX_LANE_MODE_3 0x088
#define QSERDES_V10_60_TXRX_UCDR_FASTLOCK_FO_GAIN_RATE1 0x0c8
#define QSERDES_V10_60_TXRX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x0cc
#define QSERDES_V10_60_TXRX_UCDR_FASTLOCK_FO_GAIN_RATE3 0x0d0
#define QSERDES_V10_60_TXRX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x0d4
#define QSERDES_V10_60_TXRX_UCDR_FASTLOCK_SO_GAIN_RATE1 0x0e0
#define QSERDES_V10_60_TXRX_UCDR_FASTLOCK_SO_GAIN_RATE2 0x0e4
#define QSERDES_V10_60_TXRX_UCDR_FASTLOCK_SO_GAIN_RATE3 0x0e8
#define QSERDES_V10_60_TXRX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x0ec
#define QSERDES_V10_60_TXRX_UCDR_PI_CTRL1 0x12c
#define QSERDES_V10_60_TXRX_UCDR_PI_CTRL2 0x130
#define QSERDES_V10_60_TXRX_UCDR_PI_CTRL3 0x134
#define QSERDES_V10_60_TXRX_UCDR_PI_CTRL4 0x138
#define QSERDES_V10_60_TXRX_SVS_MODE_CTRL 0x19c
#define QSERDES_V10_60_TXRX_RXCLK_DIV2_CTRL 0x1a0
#define QSERDES_V10_60_TXRX_RX_BAND_CTRL0 0x1a4
#define QSERDES_V10_60_TXRX_RX_TERM_BW_CTRL0 0x1ac
#define QSERDES_V10_60_TXRX_RX_TERM_BW_CTRL1 0x1b0
#define QSERDES_V10_60_TXRX_UCDR_FO_GAIN_RATE1 0x1b8
#define QSERDES_V10_60_TXRX_UCDR_FO_GAIN_RATE2 0x1bc
#define QSERDES_V10_60_TXRX_UCDR_FO_GAIN_RATE3 0x1c0
#define QSERDES_V10_60_TXRX_UCDR_FO_GAIN_RATE4 0x1c4
#define QSERDES_V10_60_TXRX_UCDR_SO_GAIN_RATE1 0x1d0
#define QSERDES_V10_60_TXRX_UCDR_SO_GAIN_RATE2 0x1d4
#define QSERDES_V10_60_TXRX_UCDR_SO_GAIN_RATE3 0x1d8
#define QSERDES_V10_60_TXRX_UCDR_SO_GAIN_RATE4 0x1dc
#define QSERDES_V10_60_TXRX_UCDR_PI_CONTROLS 0x1e4
#define QSERDES_V10_60_TXRX_AUXDATA_BIN_RATE3 0x200
#define QSERDES_V10_60_TXRX_AUXDATA_BIN_RATE4 0x204
#define QSERDES_V10_60_TXRX_EOM_MAX_ERR_LIMIT_LSB 0x218
#define QSERDES_V10_60_TXRX_EOM_MAX_ERR_LIMIT_MSB 0x21c
#define QSERDES_V10_60_TXRX_VGA_CAL_CNTRL1 0x280
#define QSERDES_V10_60_TXRX_VGA_CAL_MAN_VAL 0x288
#define QSERDES_V10_60_TXRX_GM_CAL 0x29c
#define QSERDES_V10_60_TXRX_RX_EQU_ADAPTOR_CNTRL6 0x2b8
#define QSERDES_V10_60_TXRX_SIGDET_ENABLES 0x2d4
#define QSERDES_V10_60_TXRX_SIGDET_CNTRL 0x2d8
#define QSERDES_V10_60_TXRX_SIGDET_LVL 0x2dc
#define QSERDES_V10_60_TXRX_SIGDET_DEGLITCH_CNTRL 0x2e0
#define QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B0 0x314
#define QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B1 0x318
#define QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B2 0x31c
#define QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B3 0x320
#define QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B4 0x324
#define QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B5 0x328
#define QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B6 0x32c
#define QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B7 0x330
#define QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B8 0x334
#define QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B9 0x338
#define QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B10 0x33c
#define QSERDES_V10_60_TXRX_RX_MODE_RATE2_B0 0x340
#define QSERDES_V10_60_TXRX_RX_MODE_RATE2_B1 0x344
#define QSERDES_V10_60_TXRX_RX_MODE_RATE2_B2 0x348
#define QSERDES_V10_60_TXRX_RX_MODE_RATE2_B3 0x34c
#define QSERDES_V10_60_TXRX_RX_MODE_RATE2_B4 0x350
#define QSERDES_V10_60_TXRX_RX_MODE_RATE2_B5 0x354
#define QSERDES_V10_60_TXRX_RX_MODE_RATE2_B6 0x358
#define QSERDES_V10_60_TXRX_RX_MODE_RATE2_B7 0x35c
#define QSERDES_V10_60_TXRX_RX_MODE_RATE2_B8 0x360
#define QSERDES_V10_60_TXRX_RX_MODE_RATE2_B9 0x364
#define QSERDES_V10_60_TXRX_RX_MODE_RATE2_B10 0x368
#define QSERDES_V10_60_TXRX_RX_MODE_RATE3_B0 0x36c
#define QSERDES_V10_60_TXRX_RX_MODE_RATE3_B1 0x370
#define QSERDES_V10_60_TXRX_RX_MODE_RATE3_B2 0x374
#define QSERDES_V10_60_TXRX_RX_MODE_RATE3_B3 0x378
#define QSERDES_V10_60_TXRX_RX_MODE_RATE3_B4 0x37c
#define QSERDES_V10_60_TXRX_RX_MODE_RATE3_B5 0x380
#define QSERDES_V10_60_TXRX_RX_MODE_RATE3_B6 0x384
#define QSERDES_V10_60_TXRX_RX_MODE_RATE3_B7 0x388
#define QSERDES_V10_60_TXRX_RX_MODE_RATE3_B8 0x38c
#define QSERDES_V10_60_TXRX_RX_MODE_RATE3_B9 0x390
#define QSERDES_V10_60_TXRX_RX_MODE_RATE3_B10 0x394
#define QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B0 0x398
#define QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B1 0x39c
#define QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B2 0x3a0
#define QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B3 0x3a4
#define QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B4 0x3a8
#define QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B5 0x3ac
#define QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B6 0x3b0
#define QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B7 0x3b4
#define QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B8 0x3b8
#define QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B9 0x3bc
#define QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B10 0x3c0
#define QSERDES_V10_60_TXRX_Q_PI_INTRINSIC_BIAS_RATE32 0x478
#define QSERDES_V10_60_TXRX_Q_PI_INTRINSIC_BIAS_RATE45 0x47c
#define QSERDES_V10_60_TXRX_SIGDET_CAL_CTRL1 0x4c8
#define QSERDES_V10_60_TXRX_SIGDET_CAL_CTRL2 0x4cc
#define QSERDES_V10_60_TXRX_SIGDET_CAL_TRIM 0x4d0
#define QSERDES_V10_60_TXRX_TX_BAND0 0x4e8
#define QSERDES_V10_60_TXRX_TX_BAND1 0x4ec
#define QSERDES_V10_60_TXRX_SEL_10B_8B 0x4f4
#define QSERDES_V10_60_TXRX_SEL_20B_10B 0x4f8
#define QSERDES_V10_60_TXRX_EQ_RCF_CTRL_RATE3 0x53c
#define QSERDES_V10_60_TXRX_EQ_RCF_CTRL_RATE4 0x540
#define QSERDES_V10_60_TXRX_PHPRE_CTRL 0x5e8
#endif

5
drivers/phy/qualcomm/phy-qcom-qmp.h
View File

@@ -39,6 +39,9 @@
#include "phy-qcom-qmp-qserdes-com-v10.h"
#include "phy-qcom-qmp-qserdes-txrx-v10.h"
#include "phy-qcom-qmp-qserdes-com-v10_60.h"
#include "phy-qcom-qmp-qserdes-txrx-v10_60.h"
#include "phy-qcom-qmp-qserdes-pll.h"
#include "phy-qcom-qmp-pcs-v2.h"
@@ -67,6 +70,8 @@
#include "phy-qcom-qmp-pcs-v10.h"
#include "phy-qcom-qmp-pcs-v10_60.h"
/* QPHY_SW_RESET bit */
#define SW_RESET BIT(0)
/* QPHY_POWER_DOWN_CONTROL */