AT91 DT for 4.20
- warning fiwes from Rob
- many updates for the axentia boards
- ADC, I2S and touch screen support for sama5d2
* tag 'at91-4.20-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
arm: dts: sama5d2: Update coresight bindings for hardware ports
ARM: dts: at91: sama5d27_som1_ek: add adc regulators
ARM: dts: atmel: Fix I2C and SPI bus warnings
ARM: dts: at91: sama5d4: add labels to soc dtsi for derivative boards
ARM: dts: at91: tse850: drop three indentation levels
ARM: dts: at91: nattis: drop three indentation levels
ARM: dts: at91: nattis: describe the lvds panel
ARM: dts: at91: nattis: move pinctrls for the lvds chip to the lvds node
ARM: dts: at91: nattis: state the actual lvds-encoder chip
ARM: dts: at91: nattis: make the SD-card slot work
ARM: dts: at91: nattis: set the PRLUD and HIPOW signals low
ARM: dts: at91/trivial: remove old NAND bindings leftover in sama5d2
ARM: dts: at91/trivial: Fix USART1 definition for at91sam9g45
ARM: dts: at91: sama5d2 Xplained: add pin muxing for I2S
ARM: dts: at91: sama5d2: add nodes for I2S controllers
ARM: dts: at91: sama5d2: add I2S clock muxing nodes
ARM: dts: at91: sama5d2: Add resistive touch device
ARM: dts: at91: sama5d2: add channel cells for ADC device
Signed-off-by: Olof Johansson <olof@lixom.net>
Commit a7eb26392b ("arm64: dts: broadcom: Add reference to Compute
Module IO Board V3") adds the bcm2837-rpi-cm3-io3.dts file as a target
in the Makefile, rather than the .dtb name. This will skip the
generation of the .dtb file at compile time and will fail the dtbs_install
target.
Fixes: a7eb26392b ("arm64: dts: broadcom: Add reference to Compute Module IO Board V3")
Signed-off-by: Liviu Dudau <liviu@dudau.co.uk>
Acked-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Samsung mach/soc changes for v4.20
1. Fix imprecise abort during Odroid XU3-family suspend to RAM (but it
is not end of work needed for suspend).
2. Cleanup and fix of SD card write protect on MINI2440.
* tag 'samsung-soc-4.20' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
ARM: s3c24xx: Restore proper usage of pr_info/pr_cont
ARM: s3c24xx: Correct SD card write protect detection on Mini2440
ARM: s3c24xx: Consistently use tab for indenting member assignments
ARM: s3c24xx: formatting cleanup in mach-mini2440.c
ARM: s3c24xx: Remove empty gta02_pmu children probe
ARM: exynos: Fix imprecise abort during Exynos5422 suspend to RAM
ARM: exynos: Store Exynos5420 register state in one variable
Signed-off-by: Olof Johansson <olof@lixom.net>
ARM: DT: Hisilicon ARM32 SoCs updates for 4.20
- Switch to updated coresight bindings for hip04 SoC
* tag 'hisi-arm32-dt-for-4.20' of git://github.com/hisilicon/linux-hisi:
arm: dts: hip04: Update coresight bindings for hardware ports
Signed-off-by: Olof Johansson <olof@lixom.net>
TI AM654 support for v4.20 merge window.
This branch adds changes for the Texas Instruments AM654 SoC. Included
changes are:
- Add uart nodes
- Change address cells and size-cells of interconnect tfrom 1 to 2
- Add secure proxy instance for main domain
- Add DMSC support
* tag 'am654-for-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux:
arm64: dts: ti: k3-am6: Add Device Management Security Controller support
arm64: dts: ti: am654: Add secure proxy instance for main domain
arm64: dts: ti: am654: Add uart nodes
arm64: dts: ti: k3-am65: Change #address-cells and #size-cells of interconnect to 2
Signed-off-by: Olof Johansson <olof@lixom.net>
ARMv8 Juno/Vexpress updates for v4.20
1. Enablement of scatter gather mode for CoreSight TMC-ETR routing
2. Usage of updated coresight graph bindings that eliminates loads of
dtc warnings
* tag 'juno-updates-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
arm64: dts: juno: Enable coresight tmc scatter gather in ETR
arm64: dts: juno: Update entries to match latest coresight bindings
Signed-off-by: Olof Johansson <olof@lixom.net>
This pull request contains Broadcom ARM64-based SoCs Device Tree changes
for 4.20, please pull the following:
- Stefan provides a reference to the Compute Module IO Board V3 such
that we can reference the arm counterpart and still build it for arm64
- Rob fixes I2C and SPI bus warnings which are going to show up with his
update to DTC scheduled for 4.20
* tag 'arm-soc/for-4.20/devicetree-arm64' of https://github.com/Broadcom/stblinux:
arm64: dts: broadcom: Fix I2C and SPI bus warnings
arm64: dts: broadcom: Add reference to Compute Module IO Board V3
Signed-off-by: Olof Johansson <olof@lixom.net>
This pull request contains Broadcom ARM-based SoCs Device Tree changes
for 4.20, please pull the following:
- Rafal updates the Broadcom BCM5301x (Northstar) DTS files to use the
new style partition parser and removes the unsupported/undocumented
linux,part-probe properties that were previously introduced
- Stefan adds supports for the Raspberry Pi Compute Module 3/3Lite, he
also updates the Raspberry Pi 3B+ USB Ethernet adapter to have proper
LED configuration
- Rob fixes a bunch of SPI bus warnings in the Northstar Plus and
Hurricane 2 DTS files
- Florian documents the Broadcom roboswitch Switch Register Access Block
(SRAB) interrupts, adds the switch interrupts to the Northstar Plus
DTS include file and finally updates the BCM958625HR reference board to
have the proper SFP module definition
* tag 'arm-soc/for-4.20/devicetree' of https://github.com/Broadcom/stblinux:
ARM: dts: bcm: Fix SPI bus warnings
ARM: dts: NSP: Wire up switch interrupts
dt-bindings: net: dsa: Document B53 SRAB interrupts and registers
ARM: dts: NSP: Enable SFP on bcm958625hr
ARM: dts: bcm283x-rpi-lan7515: Enable Ethernet LEDs
ARM: dts: BCM5301X: Specify flash partitions
ARM: dts: add Raspberry Pi Compute Module 3 and IO board
dt-bindings: bcm: Add Raspberry Pi CM3 and CM3L
Signed-off-by: Olof Johansson <olof@lixom.net>
New soc support for the px30 quad-core Cortex-A35.
New boards are the px30 eval board and roc-rk3399-pc.
The rk3328 got support for the one gpio controlled via the general
register files and the rk3399 finally got its idle-states defined.
And finally fixes and improvements for firefly-rk3399 (wifi),
roc-rk3328-cc (sdmmc-uhs, io-domains), rk3328-rock64 (gpio-regulator
pin fix) and rk3399-sapphire (gpio-regulator pin fix, pmic pin fix
and type-c port supply).
* tag 'v4.20-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
arm64: dts: rockchip: Add type-c port supply on rk3399-sapphire board
arm64: dts: rockchip: fix vcc_host1_5v pin assign on rk3328-rock64
arm64: dts: rockchip: add WiFi module support for Firefly-RK3399
arm64: dts: rockchip: remove dvs2 pinctrl from pmic on rk3399-sapphire
arm64: dts: rockchip: Fix VCC5V0_HOST_EN on rk3399-sapphire
arm64: dts: rockchip: re-order vcc_sys on rk3399-sapphire
arm64: dts: rockchip: add missing vop properties for px30
arm64: dts: rockchip: Add idle-states to device tree for rk3399
arm64: dts: rockchip: add sdmmc UHS support for roc-rk3328-cc
arm64: dts: rockchip: add GRF GPIO controller to rk3328
arm64: dts: rockchip: add io-domain to roc-rk3328-cc
arm64: dts: rockchip: add PX30 evaluation board devicetree
arm64: dts: rockchip: add core dtsi file for PX30 SoCs
dt-bindings: rockchip: grf: add grf and pmugrf description for px30
arm64: dts: rockchip: add support for ROC-RK3399-PC board
Signed-off-by: Olof Johansson <olof@lixom.net>
We need to distribute out the responsibilities of the PRCMU
registers instead of having one big lump handling everything.
By making it syscon compatible, we can start grabbing the
register map elsewhere when needed.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
SPI controller nodes should be named 'spi' rather than 'ssp'. Fixing the
name enables dtc SPI bus checks.
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
By removing the reference to skeleton.dtsi, defining chosen {}
and proper memory nodes we get warning-free device trees for
the Ux500.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The "lcdaclk_b_1" group is muxed with the function "lcd"
but needs a separate entry to be muxed in with "lcda"
rather than "lcd".
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The unit addresses of the Cortex-A9 SCU device nodes contain too many
zeroes. Remove them.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The unit address of the Cortex-A9 SCU device node contains one zero too
many. Remove it.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Initial introduction of Facebook TiogaPass family equipped with
Aspeed 2500 BMC SoC. TiogaPass is a x86 server development kit
with a ASPEED ast2500 BMC manufactured by Facebook.
Specifically, This adds the TiogaPass platform device tree file
including the flash layout used by the TiogaPass BMC machines.
Signed-off-by: Vijay Khemka <vijaykhemka@fb.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
The HXT StarDragon 4800 REP2 (Reference Evaluation Platform) is
an aarch64 ARMv8 server platform with an ast2520 BMC.
Signed-off-by: Yuan Yao <yao.yuan@linaro.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
To fit with latest rtc driver updates, rtc st,syscfg property must contain
the control register offset of pwrcfg and the mask corresponding to the
DBP (Disable Backup Protection) bit.
Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Fix wrong usage of pr_info introduced by the commit e728e4f201 ("ARM:
s3c24xx: formatting cleanup in mach-mini2440.c").
Since the idea is to print on a single line, pr_cont has to be used.
Signed-off-by: Cedric Roux <sed@free.fr>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
dtc has new checks for I2C and SPI buses. Fix the warnings in node names
and unit-addresses.
arch/arm/boot/dts/at91-dvk_som60.dtb: Warning (i2c_bus_reg): /ahb/apb/i2c@f0018000/eeprom@87: I2C bus unit address format error, expected "57"
arch/arm/boot/dts/at91-dvk_som60.dtb: Warning (i2c_bus_reg): /ahb/apb/i2c@f0018000/ft5426@56: I2C bus unit address format error, expected "38"
arch/arm/boot/dts/at91-vinco.dtb: Warning (i2c_bus_reg): /ahb/apb/i2c@f8024000/rtc@64: I2C bus unit address format error, expected "32"
arch/arm/boot/dts/at91sam9260ek.dtb: Warning (spi_bus_reg): /ahb/apb/spi@fffc8000/mtd_dataflash@0: SPI bus unit address format error, expected "1"
arch/arm/boot/dts/at91sam9g20ek_2mmc.dtb: Warning (spi_bus_reg): /ahb/apb/spi@fffc8000/mtd_dataflash@0: SPI bus unit address format error, expected "1"
arch/arm/boot/dts/at91sam9g20ek.dtb: Warning (spi_bus_reg): /ahb/apb/spi@fffc8000/mtd_dataflash@0: SPI bus unit address format error, expected "1"
arch/arm/boot/dts/at91sam9261ek.dtb: Warning (spi_bus_reg): /ahb/apb/spi@fffc8000/tsc2046@0: SPI bus unit address format error, expected "2"
Signed-off-by: Rob Herring <robh@kernel.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Add devicetree support for HiKey970 development board which
based on Hi3670 SoC and is also one of the 96Boards Consumer
Edition and AI platform.
Only UART6 is enabled which is the default console required
by the 96Boards Consumer Edition Specification.
This patch has been tested on HiKey970 Board.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Add initial devicetree support for Hisilicon Hi3670 SoC which
is similar to Hi3660 SoC with NPU support.
This SoC has Octal core BigLittle CPUs in two clusters(4 * A53 & 4 * A73).
Only UART6 has been added for console support which is
pre configured by the bootloader. A fixed clock is sourcing
the UART6 which will get replaced by the clock driver when available.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
The clocks property should either be present for all the CPUs of a
cluster or none. If these are present only for a subset of CPUs of a
cluster then things will start falling apart as soon as the CPUs are
brought online in a different order. For example, this will happen
because the operating system looks for such properties in the CPU node
it is trying to bring up, so that it can register a cooling device.
Add missing clocks property.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Add TISCI compatible System controller for AM6 SoCs.
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Add secure proxy instance for Main domain
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Add uart nodes for AM654 device tree components.
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
AM65 has two PCIe controllers and each PCIe controller has '2' address
spaces one within the 4GB address space of the SoC and the other above
the 4GB address space of the SoC (cbass_main) in addition to the
register space. The size of the address space above the 4GB SoC address
space is 4GB. These address ranges will be used by CPU/DMA to access
the PCIe address space. In order to represent the address space above
the 4GB SoC address space and to represent the size of this address
space as 4GB, change address-cells and size-cells of interconnect to 2.
Since OSPI has similar need in MCU Domain Memory Map, change
address-cells and size-cells of cbass_mcu interconnect also to 2.
Fixes: ea47eed33a ("arm64: dts: ti: Add Support for AM654 SoC")
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Vignesh R <vigneshr@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
