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Merge tag 'renesas-arm64-dt-for-v4.20' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt

Browse Source 
Renesas ARM64 Based SoC DT Updates for v4.20

* Correct whitespace around assignments

* R-Car Gen-3 SoCs:
  - Enable SDR104 for SD devices
  - Include R-Car product name in DTSI files to ease maintenance
* R-Car Gen-3 SoC based boards: Convert to new LVDS DT bindings
* R-Car Gen 3 Salvator-X and Salvator-XS boards:
  - Override secondary addresses of ADV748x to avoid address conflicts
* R-Car Gen 3 based Salvator-XS board: Enable SATA

* R-Car M3-N (r8a77965) SoC:
  - Add FDP1 device nodes
  - Move arm_cc630p and timer nodes to restore sort-order of file
  - Correct clock/reset for usb2_phy1
  - Correct HS-USB compat string
  - Add OPPs table for cpu devices enabling CPUFreq support
  - Add CAN device placeholder nodes to facilitate adding
    initial device tree for KF daughter board
  - Attach SYS-DMAC to the IPMMU
* R-Car M3-N (r8a77965) based ULCB board:
  - Initial device tree for board and KF daughter board

* R-Car E3 (r8a77990) SoC:
  - Add SYS-DMAC, I2C VIN, CSI-2, MSIOF device nodes
  - Add BRG support to SCIF2 which allows an increase in serial clock accuracy
  - Use CPG/MSSR and SYSC binding definitions
* R-Car E3 (r8a77990) based Ebisu board: Enable PWM

* R-Car D3 (r8a77995) SoC: Attach the SYS-DMAC to the IPMMU
* R-Car D3 (r8a77995) based Draak board: Sort device nodes

* R-Car V3H (r8a77980) based V3HSK board:
  - Move lvds0 node to restore sort-order of file
* R-Car V3H (r8a77980) SoC:
  - Add RWDT, CSI2 and VIN, Cortex-A53 PMU nodes
  - Move IPMMU and CAN clock nodes to restore sort-order of file

* R-Car V3M (r8a77970) SoC:
  - Add MMC nodes
  - Move CAN clock node to restore sort-order of file
* R-Car V3M (r8a77970) based V3MSK board: Add eMMC support
* R-Car V3H (r8a77980) based Condor board: Add PCIe, DU, LVDS and HDMI support

* RZ/G2M (r8a774a1) SoC:
  - Initial device tree
  - Add SYS-DMAC, SCIF, HSCIF, INTC-EX, EtherAVB, RWDT, pinctl, GPIO,
    SDHI, I2C, IIC-DVFS, thermal, IPMMU, MSIOF, Cortex-A53 CPU core,
    PWM, Audio, FCPF, FCPV, USB2.0, USB-DMAC, HSUSB and USB3.0 device nodes

* tag 'renesas-arm64-dt-for-v4.20' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (58 commits)
  arm64: dts: r8a77965: add FDP1 device nodes
  arm64: dts: renesas: draak: Sort device nodes
  arm64: dts: renesas: enable SDR104 on R-Car Gen3
  arm64: dts: renesas: r8a77990: Add SYS-DMAC device nodes
  arm64: dts: renesas: r8a77990: Add I2C device nodes
  arm64: dts: renesas: r8a77990: Add VIN and CSI-2 device nodes
  arm64: dts: renesas: r8a77990: Add all MSIOF nodes
  arm64: dts: renesas: r8a7795: Move arm_cc630p node
  arm64: dts: renesas: r8a77990: Add BRG support to SCIF2
  arm64: dts: renesas: r8a77990: Use CPG/MSSR and SYSC binding definitions
  arm64: dts: renesas: salvator-xs: Improve SATA switch settings comments
  arm64: dts: renesas: r8a77965: Fix clock/reset for usb2_phy1
  arm64: dts: renesas: r8a77965: Fix HS-USB compatible
  arm64: dts: renesas: r8a77965: Move timer node
  arm64: dts: renesas: v3hsk: Move lvds0 node
  arm64: dts: renesas: Fix whitespace around assignments
  arm64: dts: renesas: r8a77965: m3nulcb-kf: Initial device tree
  arm64: dts: renesas: condor: add PCIe support
  arm64: dts: renesas: r8a77980: add PCIe support
  arm64: dts: renesas: r8a774a1: Add USB3.0 device nodes
  ...

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
2018-09-23 06:19:04 -07:00
parent fc48cf437a 450d6079e8
commit 89cb3a4c97
27 changed files with 3476 additions and 377 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm64/boot/dts/renesas/Makefile
View File

@@ -8,6 +8,8 @@ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb r8a7796-m3ulcb.dtb
dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-m3ulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb
dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb r8a77965-salvator-xs.dtb
dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-m3nulcb.dtb
dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-m3nulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb r8a77970-v3msk.dtb
dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb r8a77980-v3hsk.dtb
dtb-$(CONFIG_ARCH_R8A77990) += r8a77990-ebisu.dtb

1664
arch/arm64/boot/dts/renesas/r8a774a1.dtsi Normal file
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File diff suppressed because it is too large Load Diff

3
arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts
View File

@@ -40,12 +40,11 @@ &du {
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
<&cpg CPG_MOD 721>,
<&cpg CPG_MOD 727>,
<&versaclock5 1>,
<&x21_clk>,
<&x22_clk>,
<&versaclock5 2>;
clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0",
clock-names = "du.0", "du.1", "du.2", "du.3",
"dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
};

18
arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the r8a7795 ES1.x SoC
* Device Tree Source for the R-Car H3 (R8A77950) ES1.x SoC
*
* Copyright (C) 2015 Renesas Electronics Corp.
*/
@@ -232,7 +232,7 @@ ports {
port@1 {
vin0csi21: endpoint@1 {
reg = <1>;
remote-endpoint= <&csi21vin0>;
remote-endpoint = <&csi21vin0>;
};
};
};
@@ -243,7 +243,7 @@ ports {
port@1 {
vin1csi21: endpoint@1 {
reg = <1>;
remote-endpoint= <&csi21vin1>;
remote-endpoint = <&csi21vin1>;
};
};
};
@@ -254,7 +254,7 @@ ports {
port@1 {
vin2csi21: endpoint@1 {
reg = <1>;
remote-endpoint= <&csi21vin2>;
remote-endpoint = <&csi21vin2>;
};
};
};
@@ -265,7 +265,7 @@ ports {
port@1 {
vin3csi21: endpoint@1 {
reg = <1>;
remote-endpoint= <&csi21vin3>;
remote-endpoint = <&csi21vin3>;
};
};
};
@@ -276,7 +276,7 @@ ports {
port@1 {
vin4csi21: endpoint@1 {
reg = <1>;
remote-endpoint= <&csi21vin4>;
remote-endpoint = <&csi21vin4>;
};
};
};
@@ -287,7 +287,7 @@ ports {
port@1 {
vin5csi21: endpoint@1 {
reg = <1>;
remote-endpoint= <&csi21vin5>;
remote-endpoint = <&csi21vin5>;
};
};
};
@@ -298,7 +298,7 @@ ports {
port@1 {
vin6csi21: endpoint@1 {
reg = <1>;
remote-endpoint= <&csi21vin6>;
remote-endpoint = <&csi21vin6>;
};
};
};
@@ -309,7 +309,7 @@ ports {
port@1 {
vin7csi21: endpoint@1 {
reg = <1>;
remote-endpoint= <&csi21vin7>;
remote-endpoint = <&csi21vin7>;
};
};
};

3
arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
View File

@@ -41,11 +41,10 @@ &du {
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
<&cpg CPG_MOD 721>,
<&cpg CPG_MOD 727>,
<&versaclock5 1>,
<&versaclock5 3>,
<&versaclock5 4>,
<&versaclock5 2>;
clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0",
clock-names = "du.0", "du.1", "du.2", "du.3",
"dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
};

3
arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
View File

@@ -40,12 +40,11 @@ &du {
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
<&cpg CPG_MOD 721>,
<&cpg CPG_MOD 727>,
<&versaclock5 1>,
<&x21_clk>,
<&x22_clk>,
<&versaclock5 2>;
clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0",
clock-names = "du.0", "du.1", "du.2", "du.3",
"dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
};

17
arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
View File

@@ -40,12 +40,11 @@ &du {
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
<&cpg CPG_MOD 721>,
<&cpg CPG_MOD 727>,
<&versaclock6 1>,
<&x21_clk>,
<&x22_clk>,
<&versaclock6 2>;
clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0",
clock-names = "du.0", "du.1", "du.2", "du.3",
"dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
};
@@ -152,6 +151,15 @@ rsnd_endpoint2: endpoint {
};
};
&pca9654 {
pcie_sata_switch {
gpio-hog;
gpios = <7 GPIO_ACTIVE_HIGH>;
output-low; /* enable SATA by default */
line-name = "PCIE/SATA switch";
};
};
&pfc {
usb2_pins: usb2 {
groups = "usb2";
@@ -176,6 +184,11 @@ usb2_ch3_pins: usb2_ch3 {
};
};
/* SW12-7 must be set 'Off' (MD12 set to 1) which is not the default! */
&sata {
status = "okay";
};
&usb2_phy2 {
pinctrl-0 = <&usb2_pins>;
pinctrl-names = "default";

104
arch/arm64/boot/dts/renesas/r8a7795.dtsi
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the r8a7795 SoC
* Device Tree Source for the R-Car H3 (R8A77950) SoC
*
* Copyright (C) 2015 Renesas Electronics Corp.
*/
@@ -123,7 +123,7 @@ a57_0: cpu@0 {
power-domains = <&sysc R8A7795_PD_CA57_CPU0>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
};
@@ -135,7 +135,7 @@ a57_1: cpu@1 {
power-domains = <&sysc R8A7795_PD_CA57_CPU1>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
};
@@ -147,7 +147,7 @@ a57_2: cpu@2 {
power-domains = <&sysc R8A7795_PD_CA57_CPU2>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
};
@@ -159,7 +159,7 @@ a57_3: cpu@3 {
power-domains = <&sysc R8A7795_PD_CA57_CPU3>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
};
@@ -171,7 +171,7 @@ a53_0: cpu@100 {
power-domains = <&sysc R8A7795_PD_CA53_CPU0>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
};
@@ -182,7 +182,7 @@ a53_1: cpu@101 {
power-domains = <&sysc R8A7795_PD_CA53_CPU1>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
};
@@ -193,7 +193,7 @@ a53_2: cpu@102 {
power-domains = <&sysc R8A7795_PD_CA53_CPU2>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
};
@@ -204,7 +204,7 @@ a53_3: cpu@103 {
power-domains = <&sysc R8A7795_PD_CA53_CPU3>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
};
@@ -525,15 +525,6 @@ i2c2: i2c@e6510000 {
status = "disabled";
};
arm_cc630p: crypto@e6601000 {
compatible = "arm,cryptocell-630p-ree";
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xe6601000 0 0x1000>;
clocks = <&cpg CPG_MOD 229>;
resets = <&cpg 229>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
};
i2c3: i2c@e66d0000 {
#address-cells = <1>;
#size-cells = <0>;
@@ -805,6 +796,15 @@ usb3_phy0: usb-phy@e65ee000 {
status = "disabled";
};
arm_cc630p: crypto@e6601000 {
compatible = "arm,cryptocell-630p-ree";
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xe6601000 0 0x1000>;
clocks = <&cpg CPG_MOD 229>;
resets = <&cpg 229>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
};
dmac0: dma-controller@e6700000 {
compatible = "renesas,dmac-r8a7795",
"renesas,rcar-dmac";
@@ -1425,11 +1425,11 @@ port@1 {
vin0csi20: endpoint@0 {
reg = <0>;
remote-endpoint= <&csi20vin0>;
remote-endpoint = <&csi20vin0>;
};
vin0csi40: endpoint@2 {
reg = <2>;
remote-endpoint= <&csi40vin0>;
remote-endpoint = <&csi40vin0>;
};
};
};
@@ -1457,11 +1457,11 @@ port@1 {
vin1csi20: endpoint@0 {
reg = <0>;
remote-endpoint= <&csi20vin1>;
remote-endpoint = <&csi20vin1>;
};
vin1csi40: endpoint@2 {
reg = <2>;
remote-endpoint= <&csi40vin1>;
remote-endpoint = <&csi40vin1>;
};
};
};
@@ -1489,11 +1489,11 @@ port@1 {
vin2csi20: endpoint@0 {
reg = <0>;
remote-endpoint= <&csi20vin2>;
remote-endpoint = <&csi20vin2>;
};
vin2csi40: endpoint@2 {
reg = <2>;
remote-endpoint= <&csi40vin2>;
remote-endpoint = <&csi40vin2>;
};
};
};
@@ -1521,11 +1521,11 @@ port@1 {
vin3csi20: endpoint@0 {
reg = <0>;
remote-endpoint= <&csi20vin3>;
remote-endpoint = <&csi20vin3>;
};
vin3csi40: endpoint@2 {
reg = <2>;
remote-endpoint= <&csi40vin3>;
remote-endpoint = <&csi40vin3>;
};
};
};
@@ -1553,11 +1553,11 @@ port@1 {
vin4csi20: endpoint@0 {
reg = <0>;
remote-endpoint= <&csi20vin4>;
remote-endpoint = <&csi20vin4>;
};
vin4csi41: endpoint@3 {
reg = <3>;
remote-endpoint= <&csi41vin4>;
remote-endpoint = <&csi41vin4>;
};
};
};
@@ -1585,11 +1585,11 @@ port@1 {
vin5csi20: endpoint@0 {
reg = <0>;
remote-endpoint= <&csi20vin5>;
remote-endpoint = <&csi20vin5>;
};
vin5csi41: endpoint@3 {
reg = <3>;
remote-endpoint= <&csi41vin5>;
remote-endpoint = <&csi41vin5>;
};
};
};
@@ -1617,11 +1617,11 @@ port@1 {
vin6csi20: endpoint@0 {
reg = <0>;
remote-endpoint= <&csi20vin6>;
remote-endpoint = <&csi20vin6>;
};
vin6csi41: endpoint@3 {
reg = <3>;
remote-endpoint= <&csi41vin6>;
remote-endpoint = <&csi41vin6>;
};
};
};
@@ -1649,11 +1649,11 @@ port@1 {
vin7csi20: endpoint@0 {
reg = <0>;
remote-endpoint= <&csi20vin7>;
remote-endpoint = <&csi20vin7>;
};
vin7csi41: endpoint@3 {
reg = <3>;
remote-endpoint= <&csi41vin7>;
remote-endpoint = <&csi41vin7>;
};
};
};
@@ -2782,9 +2782,7 @@ port@2 {
du: display@feb00000 {
compatible = "renesas,du-r8a7795";
reg = <0 0xfeb00000 0 0x80000>,
<0 0xfeb90000 0 0x14>;
reg-names = "du", "lvds.0";
reg = <0 0xfeb00000 0 0x80000>;
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
@@ -2792,9 +2790,8 @@ du: display@feb00000 {
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
<&cpg CPG_MOD 721>,
<&cpg CPG_MOD 727>;
clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0";
<&cpg CPG_MOD 721>;
clock-names = "du.0", "du.1", "du.2", "du.3";
vsps = <&vspd0 0 &vspd1 0 &vspd2 0 &vspd0 1>;
status = "disabled";
@@ -2822,6 +2819,33 @@ du_out_hdmi1: endpoint {
port@3 {
reg = <3>;
du_out_lvds0: endpoint {
remote-endpoint = <&lvds0_in>;
};
};
};
};
lvds0: lvds@feb90000 {
compatible = "renesas,r8a7795-lvds";
reg = <0 0xfeb90000 0 0x14>;
clocks = <&cpg CPG_MOD 727>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 727>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
lvds0_in: endpoint {
remote-endpoint = <&du_out_lvds0>;
};
};
port@1 {
reg = <1>;
lvds0_out: endpoint {
};
};
};

3
arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
View File

@@ -30,10 +30,9 @@ &du {
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
<&cpg CPG_MOD 727>,
<&versaclock5 1>,
<&versaclock5 3>,
<&versaclock5 2>;
clock-names = "du.0", "du.1", "du.2", "lvds.0",
clock-names = "du.0", "du.1", "du.2",
"dclkin.0", "dclkin.1", "dclkin.2";
};

3
arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
View File

@@ -29,11 +29,10 @@ &du {
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
<&cpg CPG_MOD 727>,
<&versaclock5 1>,
<&x21_clk>,
<&versaclock5 2>;
clock-names = "du.0", "du.1", "du.2", "lvds.0",
clock-names = "du.0", "du.1", "du.2",
"dclkin.0", "dclkin.1", "dclkin.2";
};

86
arch/arm64/boot/dts/renesas/r8a7796.dtsi
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the r8a7796 SoC
* Device Tree Source for the R-Car M3-W (R8A77960) SoC
*
* Copyright (C) 2016-2017 Renesas Electronics Corp.
*/
@@ -134,7 +134,7 @@ a57_0: cpu@0 {
power-domains = <&sysc R8A7796_PD_CA57_CPU0>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
clocks =<&cpg CPG_CORE R8A7796_CLK_Z>;
clocks = <&cpg CPG_CORE R8A7796_CLK_Z>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
};
@@ -146,7 +146,7 @@ a57_1: cpu@1 {
power-domains = <&sysc R8A7796_PD_CA57_CPU1>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
clocks =<&cpg CPG_CORE R8A7796_CLK_Z>;
clocks = <&cpg CPG_CORE R8A7796_CLK_Z>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
};
@@ -158,7 +158,7 @@ a53_0: cpu@100 {
power-domains = <&sysc R8A7796_PD_CA53_CPU0>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
};
@@ -169,7 +169,7 @@ a53_1: cpu@101 {
power-domains = <&sysc R8A7796_PD_CA53_CPU1>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
};
@@ -180,7 +180,7 @@ a53_2: cpu@102 {
power-domains = <&sysc R8A7796_PD_CA53_CPU2>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
};
@@ -191,7 +191,7 @@ a53_3: cpu@103 {
power-domains = <&sysc R8A7796_PD_CA53_CPU3>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
};
@@ -1299,11 +1299,11 @@ port@1 {
vin0csi20: endpoint@0 {
reg = <0>;
remote-endpoint= <&csi20vin0>;
remote-endpoint = <&csi20vin0>;
};
vin0csi40: endpoint@2 {
reg = <2>;
remote-endpoint= <&csi40vin0>;
remote-endpoint = <&csi40vin0>;
};
};
};
@@ -1331,11 +1331,11 @@ port@1 {
vin1csi20: endpoint@0 {
reg = <0>;
remote-endpoint= <&csi20vin1>;
remote-endpoint = <&csi20vin1>;
};
vin1csi40: endpoint@2 {
reg = <2>;
remote-endpoint= <&csi40vin1>;
remote-endpoint = <&csi40vin1>;
};
};
};
@@ -1363,11 +1363,11 @@ port@1 {
vin2csi20: endpoint@0 {
reg = <0>;
remote-endpoint= <&csi20vin2>;
remote-endpoint = <&csi20vin2>;
};
vin2csi40: endpoint@2 {
reg = <2>;
remote-endpoint= <&csi40vin2>;
remote-endpoint = <&csi40vin2>;
};
};
};
@@ -1395,11 +1395,11 @@ port@1 {
vin3csi20: endpoint@0 {
reg = <0>;
remote-endpoint= <&csi20vin3>;
remote-endpoint = <&csi20vin3>;
};
vin3csi40: endpoint@2 {
reg = <2>;
remote-endpoint= <&csi40vin3>;
remote-endpoint = <&csi40vin3>;
};
};
};
@@ -1427,11 +1427,11 @@ port@1 {
vin4csi20: endpoint@0 {
reg = <0>;
remote-endpoint= <&csi20vin4>;
remote-endpoint = <&csi20vin4>;
};
vin4csi40: endpoint@2 {
reg = <2>;
remote-endpoint= <&csi40vin4>;
remote-endpoint = <&csi40vin4>;
};
};
};
@@ -1459,11 +1459,11 @@ port@1 {
vin5csi20: endpoint@0 {
reg = <0>;
remote-endpoint= <&csi20vin5>;
remote-endpoint = <&csi20vin5>;
};
vin5csi40: endpoint@2 {
reg = <2>;
remote-endpoint= <&csi40vin5>;
remote-endpoint = <&csi40vin5>;
};
};
};
@@ -1491,11 +1491,11 @@ port@1 {
vin6csi20: endpoint@0 {
reg = <0>;
remote-endpoint= <&csi20vin6>;
remote-endpoint = <&csi20vin6>;
};
vin6csi40: endpoint@2 {
reg = <2>;
remote-endpoint= <&csi40vin6>;
remote-endpoint = <&csi40vin6>;
};
};
};
@@ -1523,11 +1523,11 @@ port@1 {
vin7csi20: endpoint@0 {
reg = <0>;
remote-endpoint= <&csi20vin7>;
remote-endpoint = <&csi20vin7>;
};
vin7csi40: endpoint@2 {
reg = <2>;
remote-endpoint= <&csi40vin7>;
remote-endpoint = <&csi40vin7>;
};
};
};
@@ -1997,7 +1997,7 @@ ehci0: usb@ee080100 {
clocks = <&cpg CPG_MOD 703>;
phys = <&usb2_phy0>;
phy-names = "usb";
companion= <&ohci0>;
companion = <&ohci0>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 703>;
status = "disabled";
@@ -2010,7 +2010,7 @@ ehci1: usb@ee0a0100 {
clocks = <&cpg CPG_MOD 702>;
phys = <&usb2_phy1>;
phy-names = "usb";
companion= <&ohci1>;
companion = <&ohci1>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 702>;
status = "disabled";
@@ -2437,17 +2437,14 @@ port@2 {
du: display@feb00000 {
compatible = "renesas,du-r8a7796";
reg = <0 0xfeb00000 0 0x70000>,
<0 0xfeb90000 0 0x14>;
reg-names = "du", "lvds.0";
reg = <0 0xfeb00000 0 0x70000>;
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
<&cpg CPG_MOD 727>;
clock-names = "du.0", "du.1", "du.2", "lvds.0";
<&cpg CPG_MOD 722>;
clock-names = "du.0", "du.1", "du.2";
status = "disabled";
vsps = <&vspd0 &vspd1 &vspd2>;
@@ -2470,6 +2467,33 @@ du_out_hdmi0: endpoint {
port@2 {
reg = <2>;
du_out_lvds0: endpoint {
remote-endpoint = <&lvds0_in>;
};
};
};
};
lvds0: lvds@feb90000 {
compatible = "renesas,r8a7796-lvds";
reg = <0 0xfeb90000 0 0x14>;
clocks = <&cpg CPG_MOD 727>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 727>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
lvds0_in: endpoint {
remote-endpoint = <&du_out_lvds0>;
};
};
port@1 {
reg = <1>;
lvds0_out: endpoint {
};
};
};

16
arch/arm64/boot/dts/renesas/r8a77965-m3nulcb-kf.dts Normal file
View File

@@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the M3NULCB Kingfisher board
*
* Copyright (C) 2018 Renesas Electronics Corp.
* Copyright (C) 2018 Cogent Embedded, Inc.
*/
#include "r8a77965-m3nulcb.dts"
#include "ulcb-kf.dtsi"
/ {
model = "Renesas M3NULCB Kingfisher board based on r8a77965";
compatible = "shimafuji,kingfisher", "renesas,m3nulcb",
"renesas,r8a77965";
};

33
arch/arm64/boot/dts/renesas/r8a77965-m3nulcb.dts Normal file
View File

@@ -0,0 +1,33 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the M3NULCB (R-Car Starter Kit Pro) board
*
* Copyright (C) 2018 Renesas Electronics Corp.
* Copyright (C) 2018 Cogent Embedded, Inc.
*/
/dts-v1/;
#include "r8a77965.dtsi"
#include "ulcb.dtsi"
/ {
model = "Renesas M3NULCB board based on r8a77965";
compatible = "renesas,m3nulcb", "renesas,r8a77965";
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
};
&du {
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 721>,
<&versaclock5 1>,
<&versaclock5 3>,
<&versaclock5 2>;
clock-names = "du.0", "du.1", "du.3",
"dclkin.0", "dclkin.1", "dclkin.3";
};

14
arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts
View File

@@ -47,3 +47,17 @@ rcar_dw_hdmi0_out: endpoint {
&hdmi0_con {
remote-endpoint = <&rcar_dw_hdmi0_out>;
};
&pca9654 {
pcie_sata_switch {
gpio-hog;
gpios = <7 GPIO_ACTIVE_HIGH>;
output-low; /* enable SATA by default */
line-name = "PCIE/SATA switch";
};
};
/* SW12-7 must be set 'Off' (MD12 set to 1) which is not the default! */
&sata {
status = "okay";
};

155
arch/arm64/boot/dts/renesas/r8a77965.dtsi
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the r8a77965 SoC
* Device Tree Source for the R-Car M3-N (R8A77965) SoC
*
* Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
*
@@ -60,6 +60,46 @@ can_clk: can {
clock-frequency = <0>;
};
cluster0_opp: opp_table0 {
compatible = "operating-points-v2";
opp-shared;
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <830000>;
clock-latency-ns = <300000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <830000>;
clock-latency-ns = <300000>;
};
opp-1500000000 {
opp-hz = /bits/ 64 <1500000000>;
opp-microvolt = <830000>;
clock-latency-ns = <300000>;
opp-suspend;
};
opp-1600000000 {
opp-hz = /bits/ 64 <1600000000>;
opp-microvolt = <900000>;
clock-latency-ns = <300000>;
turbo-mode;
};
opp-1700000000 {
opp-hz = /bits/ 64 <1700000000>;
opp-microvolt = <900000>;
clock-latency-ns = <300000>;
turbo-mode;
};
opp-1800000000 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <960000>;
clock-latency-ns = <300000>;
turbo-mode;
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -71,6 +111,8 @@ a57_0: cpu@0 {
power-domains = <&sysc R8A77965_PD_CA57_CPU0>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R8A77965_CLK_Z>;
operating-points-v2 = <&cluster0_opp>;
};
a57_1: cpu@1 {
@@ -80,6 +122,8 @@ a57_1: cpu@1 {
power-domains = <&sysc R8A77965_PD_CA57_CPU1>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R8A77965_CLK_Z>;
operating-points-v2 = <&cluster0_opp>;
};
L2_CA57: cache-controller-0 {
@@ -545,7 +589,7 @@ hscif4: serial@e66b0000 {
};
hsusb: usb@e6590000 {
compatible = "renesas,usbhs-r8a7796",
compatible = "renesas,usbhs-r8a77965",
"renesas,rcar-gen3-usbhs";
reg = <0 0xe6590000 0 0x100>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
@@ -634,6 +678,14 @@ GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
resets = <&cpg 219>;
#dma-cells = <1>;
dma-channels = <16>;
iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
<&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
<&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
<&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
<&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
<&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
<&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
<&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
};
dmac1: dma-controller@e7300000 {
@@ -668,6 +720,14 @@ GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
resets = <&cpg 218>;
#dma-cells = <1>;
dma-channels = <16>;
iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
<&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
<&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
<&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
<&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
<&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
<&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
<&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
};
dmac2: dma-controller@e7310000 {
@@ -702,6 +762,14 @@ GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH
resets = <&cpg 217>;
#dma-cells = <1>;
dma-channels = <16>;
iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
<&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
<&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
<&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
<&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
<&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
<&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
<&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
};
ipmmu_ds0: mmu@e6740000 {
@@ -838,6 +906,16 @@ avb: ethernet@e6800000 {
status = "disabled";
};
can0: can@e6c30000 {
reg = <0 0xe6c30000 0 0x1000>;
/* placeholder */
};
can1: can@e6c38000 {
reg = <0 0xe6c38000 0 0x1000>;
/* placeholder */
};
pwm0: pwm@e6e30000 {
compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
reg = <0 0xe6e30000 0 8>;
@@ -1089,11 +1167,11 @@ port@1 {
vin0csi20: endpoint@0 {
reg = <0>;
remote-endpoint= <&csi20vin0>;
remote-endpoint = <&csi20vin0>;
};
vin0csi40: endpoint@2 {
reg = <2>;
remote-endpoint= <&csi40vin0>;
remote-endpoint = <&csi40vin0>;
};
};
};
@@ -1121,11 +1199,11 @@ port@1 {
vin1csi20: endpoint@0 {
reg = <0>;
remote-endpoint= <&csi20vin1>;
remote-endpoint = <&csi20vin1>;
};
vin1csi40: endpoint@2 {
reg = <2>;
remote-endpoint= <&csi40vin1>;
remote-endpoint = <&csi40vin1>;
};
};
};
@@ -1153,11 +1231,11 @@ port@1 {
vin2csi20: endpoint@0 {
reg = <0>;
remote-endpoint= <&csi20vin2>;
remote-endpoint = <&csi20vin2>;
};
vin2csi40: endpoint@2 {
reg = <2>;
remote-endpoint= <&csi40vin2>;
remote-endpoint = <&csi40vin2>;
};
};
};
@@ -1185,11 +1263,11 @@ port@1 {
vin3csi20: endpoint@0 {
reg = <0>;
remote-endpoint= <&csi20vin3>;
remote-endpoint = <&csi20vin3>;
};
vin3csi40: endpoint@2 {
reg = <2>;
remote-endpoint= <&csi40vin3>;
remote-endpoint = <&csi40vin3>;
};
};
};
@@ -1217,11 +1295,11 @@ port@1 {
vin4csi20: endpoint@0 {
reg = <0>;
remote-endpoint= <&csi20vin4>;
remote-endpoint = <&csi20vin4>;
};
vin4csi40: endpoint@2 {
reg = <2>;
remote-endpoint= <&csi40vin4>;
remote-endpoint = <&csi40vin4>;
};
};
};
@@ -1249,11 +1327,11 @@ port@1 {
vin5csi20: endpoint@0 {
reg = <0>;
remote-endpoint= <&csi20vin5>;
remote-endpoint = <&csi20vin5>;
};
vin5csi40: endpoint@2 {
reg = <2>;
remote-endpoint= <&csi40vin5>;
remote-endpoint = <&csi40vin5>;
};
};
};
@@ -1281,11 +1359,11 @@ port@1 {
vin6csi20: endpoint@0 {
reg = <0>;
remote-endpoint= <&csi20vin6>;
remote-endpoint = <&csi20vin6>;
};
vin6csi40: endpoint@2 {
reg = <2>;
remote-endpoint= <&csi40vin6>;
remote-endpoint = <&csi40vin6>;
};
};
};
@@ -1313,11 +1391,11 @@ port@1 {
vin7csi20: endpoint@0 {
reg = <0>;
remote-endpoint= <&csi20vin7>;
remote-endpoint = <&csi20vin7>;
};
vin7csi40: endpoint@2 {
reg = <2>;
remote-endpoint= <&csi40vin7>;
remote-endpoint = <&csi40vin7>;
};
};
};
@@ -1452,9 +1530,9 @@ usb2_phy1: usb-phy@ee0a0200 {
compatible = "renesas,usb2-phy-r8a77965",
"renesas,rcar-gen3-usb2-phy";
reg = <0 0xee0a0200 0 0x700>;
clocks = <&cpg CPG_MOD 703>;
clocks = <&cpg CPG_MOD 702>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 703>;
resets = <&cpg 702>;
#phy-cells = <0>;
status = "disabled";
};
@@ -1507,6 +1585,17 @@ sdhi3: sd@ee160000 {
status = "disabled";
};
sata: sata@ee300000 {
compatible = "renesas,sata-r8a77965",
"renesas,rcar-gen3-sata";
reg = <0 0xee300000 0 0x200000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 815>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 815>;
status = "disabled";
};
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
@@ -1578,6 +1667,16 @@ pciec1: pcie@ee800000 {
status = "disabled";
};
fdp1@fe940000 {
compatible = "renesas,fdp1";
reg = <0 0xfe940000 0 0x2400>;
interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 119>;
power-domains = <&sysc R8A77965_PD_A3VP>;
resets = <&cpg 119>;
renesas,fcp = <&fcpf0>;
};
fcpf0: fcp@fe950000 {
compatible = "renesas,fcpf";
reg = <0 0xfe950000 0 0x200>;
@@ -1843,14 +1942,6 @@ prr: chipid@fff00044 {
};
};
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
};
thermal-zones {
sensor_thermal1: sensor-thermal1 {
polling-delay-passive = <250>;
@@ -1895,6 +1986,14 @@ sensor3_crit: sensor3-crit {
};
};
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
};
/* External USB clocks - can be overridden by the board */
usb3s0_clk: usb3s0 {
compatible = "fixed-clock";

26
arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
View File

@@ -51,6 +51,15 @@ vcc_d3_3v: regulator-1 {
regulator-always-on;
};
vcc_vddq_vin0: regulator-2 {
compatible = "regulator-fixed";
regulator-name = "VCC_VDDQ_VIN0";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
lvds-decoder {
compatible = "thine,thc63lvd1024";
vcc-supply = <&vcc_d3_3v>;
@@ -128,6 +137,12 @@ i2c0_pins: i2c0 {
function = "i2c0";
};
mmc_pins: mmc_3_3v {
groups = "mmc_data8", "mmc_ctrl";
function = "mmc";
power-source = <3300>;
};
scif0_pins: scif0 {
groups = "scif0_data";
function = "scif0";
@@ -192,6 +207,17 @@ lvds0_out: endpoint {
};
};
&mmc0 {
pinctrl-0 = <&mmc_pins>;
pinctrl-names = "default";
vmmc-supply = <&vcc_d3_3v>;
vqmmc-supply = <&vcc_vddq_vin0>;
bus-width = <8>;
non-removable;
status = "okay";
};
&scif0 {
pinctrl-0 = <&scif0_pins>;
pinctrl-names = "default";

36
arch/arm64/boot/dts/renesas/r8a77970.dtsi
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the r8a77970 SoC
* Device Tree Source for the R-Car V3M (R8A77970) SoC
*
* Copyright (C) 2016-2017 Renesas Electronics Corp.
* Copyright (C) 2017 Cogent Embedded, Inc.
@@ -24,6 +24,13 @@ aliases {
i2c4 = &i2c4;
};
/* External CAN clock - to be overridden by boards that provide it */
can_clk: can {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -82,13 +89,6 @@ psci {
method = "smc";
};
/* External CAN clock - to be overridden by boards that provide it */
can_clk: can {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
/* External SCIF clock - to be overridden by boards that provide it */
scif_clk: scif {
compatible = "fixed-clock";
@@ -567,7 +567,7 @@ port@1 {
vin0csi40: endpoint@2 {
reg = <2>;
remote-endpoint= <&csi40vin0>;
remote-endpoint = <&csi40vin0>;
};
};
};
@@ -595,7 +595,7 @@ port@1 {
vin1csi40: endpoint@2 {
reg = <2>;
remote-endpoint= <&csi40vin1>;
remote-endpoint = <&csi40vin1>;
};
};
};
@@ -623,7 +623,7 @@ port@1 {
vin2csi40: endpoint@2 {
reg = <2>;
remote-endpoint= <&csi40vin2>;
remote-endpoint = <&csi40vin2>;
};
};
};
@@ -651,7 +651,7 @@ port@1 {
vin3csi40: endpoint@2 {
reg = <2>;
remote-endpoint= <&csi40vin3>;
remote-endpoint = <&csi40vin3>;
};
};
};
@@ -754,6 +754,18 @@ ipmmu_vi0: mmu@febd0000 {
#iommu-cells = <1>;
};
mmc0: mmc@ee140000 {
compatible = "renesas,sdhi-r8a77970",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee140000 0 0x2000>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 314>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 314>;
max-frequency = <200000000>;
status = "disabled";
};
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;

123
arch/arm64/boot/dts/renesas/r8a77980-condor.dts
View File

@@ -45,6 +45,56 @@ vddq_vin01: regulator-1 {
regulator-boot-on;
regulator-always-on;
};
d1_8v: regulator-2 {
compatible = "regulator-fixed";
regulator-name = "D1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
hdmi-out {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con: endpoint {
remote-endpoint = <&adv7511_out>;
};
};
};
lvds-decoder {
compatible = "thine,thc63lvd1024";
vcc-supply = <&d3_3v>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
thc63lvd1024_in: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
port@2 {
reg = <2>;
thc63lvd1024_out: endpoint {
remote-endpoint = <&adv7511_in>;
};
};
};
};
x1_clk: x1-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <148500000>;
};
};
&avb {
@@ -74,6 +124,13 @@ channel0 {
};
};
&du {
clocks = <&cpg CPG_MOD 724>,
<&x1_clk>;
clock-names = "du.0", "dclkin.0";
status = "okay";
};
&extal_clk {
clock-frequency = <16666666>;
};
@@ -102,6 +159,55 @@ io_expander1: gpio@21 {
gpio-controller;
#gpio-cells = <2>;
};
hdmi@39 {
compatible = "adi,adv7511w";
reg = <0x39>;
interrupt-parent = <&gpio1>;
interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
avdd-supply = <&d1_8v>;
dvdd-supply = <&d1_8v>;
pvdd-supply = <&d1_8v>;
bgvdd-supply = <&d1_8v>;
dvdd-3v-supply = <&d3_3v>;
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
adi,input-style = <1>;
adi,input-justification = "evenly";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7511_in: endpoint {
remote-endpoint = <&thc63lvd1024_out>;
};
};
port@1 {
reg = <1>;
adv7511_out: endpoint {
remote-endpoint = <&hdmi_con>;
};
};
};
};
};
&lvds0 {
status = "okay";
ports {
port@1 {
lvds0_out: endpoint {
remote-endpoint = <&thc63lvd1024_in>;
};
};
};
};
&mmc0 {
@@ -117,6 +223,18 @@ &mmc0 {
status = "okay";
};
&pciec {
status = "okay";
};
&pcie_bus_clk {
clock-frequency = <100000000>;
};
&pcie_phy {
status = "okay";
};
&pfc {
avb_pins: avb {
groups = "avb_mdio", "avb_rgmii";
@@ -156,6 +274,11 @@ scif_clk_pins: scif_clk {
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&scif0 {
pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
pinctrl-names = "default";

134
arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts
View File

@@ -27,6 +27,72 @@ memory@48000000 {
/* first 128MB is reserved for secure area. */
reg = <0 0x48000000 0 0x78000000>;
};
hdmi-out {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con: endpoint {
remote-endpoint = <&adv7511_out>;
};
};
};
lvds-decoder {
compatible = "thine,thc63lvd1024";
vcc-supply = <&vcc3v3_d5>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
thc63lvd1024_in: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
port@2 {
reg = <2>;
thc63lvd1024_out: endpoint {
remote-endpoint = <&adv7511_in>;
};
};
};
};
osc1_clk: osc1-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <148500000>;
};
vcc1v8_d4: regulator-0 {
compatible = "regulator-fixed";
regulator-name = "VCC1V8_D4";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
vcc3v3_d5: regulator-1 {
compatible = "regulator-fixed";
regulator-name = "VCC3V3_D5";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
&du {
clocks = <&cpg CPG_MOD 724>,
<&osc1_clk>;
clock-names = "du.0", "dclkin.0";
status = "okay";
};
&extal_clk {
@@ -53,6 +119,64 @@ phy0: ethernet-phy@0 {
};
};
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
hdmi@39 {
compatible = "adi,adv7511w";
#sound-dai-cells = <0>;
reg = <0x39>;
interrupt-parent = <&gpio1>;
interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
avdd-supply = <&vcc1v8_d4>;
dvdd-supply = <&vcc1v8_d4>;
pvdd-supply = <&vcc1v8_d4>;
bgvdd-supply = <&vcc1v8_d4>;
dvdd-3v-supply = <&vcc3v3_d5>;
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
adi,input-style = <1>;
adi,input-justification = "evenly";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7511_in: endpoint {
remote-endpoint = <&thc63lvd1024_out>;
};
};
port@1 {
reg = <1>;
adv7511_out: endpoint {
remote-endpoint = <&hdmi_con>;
};
};
};
};
};
&lvds0 {
status = "okay";
ports {
port@1 {
lvds0_out: endpoint {
remote-endpoint = <&thc63lvd1024_in>;
};
};
};
};
&pfc {
gether_pins: gether {
groups = "gether_mdio_a", "gether_rgmii",
@@ -60,6 +184,11 @@ gether_pins: gether {
function = "gether";
};
i2c0_pins: i2c0 {
groups = "i2c0";
function = "i2c0";
};
scif0_pins: scif0 {
groups = "scif0_data";
function = "scif0";
@@ -71,6 +200,11 @@ scif_clk_pins: scif_clk {
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&scif0 {
pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
pinctrl-names = "default";

584
arch/arm64/boot/dts/renesas/r8a77980.dtsi
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the r8a77980 SoC
* Device Tree Source for the R-Car V3H (R8A77980) SoC
*
* Copyright (C) 2018 Renesas Electronics Corp.
* Copyright (C) 2018 Cogent Embedded, Inc.
@@ -25,6 +25,13 @@ aliases {
i2c5 = &i2c5;
};
/* External CAN clock - to be overridden by boards that provide it */
can_clk: can {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -77,13 +84,6 @@ L2_CA53: cache-controller {
};
};
/* External CAN clock - to be overridden by boards that provide it */
can_clk: can {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
extal_clk: extal {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -98,6 +98,22 @@ extalr_clk: extalr {
clock-frequency = <0>;
};
/* External PCIe clock - can be overridden by the board */
pcie_bus_clk: pcie_bus {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
pmu_a53 {
compatible = "arm,cortex-a53-pmu";
interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
};
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
@@ -118,6 +134,16 @@ soc {
#size-cells = <2>;
ranges;
rwdt: watchdog@e6020000 {
compatible = "renesas,r8a77980-wdt",
"renesas,rcar-gen3-wdt";
reg = <0 0xe6020000 0 0x0c>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 402>;
status = "disabled";
};
gpio0: gpio@e6050000 {
compatible = "renesas,gpio-r8a77980",
"renesas,rcar-gen3-gpio";
@@ -418,6 +444,16 @@ hscif3: serial@e66a0000 {
status = "disabled";
};
pcie_phy: pcie-phy@e65d0000 {
compatible = "renesas,r8a77980-pcie-phy";
reg = <0 0xe65d0000 0 0x8000>;
#phy-cells = <0>;
clocks = <&cpg CPG_MOD 319>;
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 319>;
status = "disabled";
};
canfd: can@e66c0000 {
compatible = "renesas,r8a77980-canfd",
"renesas,rcar-gen3-canfd";
@@ -443,69 +479,6 @@ channel1 {
};
};
ipmmu_ds1: mmu@e7740000 {
compatible = "renesas,ipmmu-r8a77980";
reg = <0 0xe7740000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 0>;
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_vip0: mmu@e7b00000 {
compatible = "renesas,ipmmu-r8a77980";
reg = <0 0xe7b00000 0 0x1000>;
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_vip1: mmu@e7960000 {
compatible = "renesas,ipmmu-r8a77980";
reg = <0 0xe7960000 0 0x1000>;
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_ir: mmu@ff8b0000 {
compatible = "renesas,ipmmu-r8a77980";
reg = <0 0xff8b0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 3>;
power-domains = <&sysc R8A77980_PD_A3IR>;
#iommu-cells = <1>;
};
ipmmu_mm: mmu@e67b0000 {
compatible = "renesas,ipmmu-r8a77980";
reg = <0 0xe67b0000 0 0x1000>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_rt: mmu@ffc80000 {
compatible = "renesas,ipmmu-r8a77980";
reg = <0 0xffc80000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 10>;
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_vc0: mmu@fe6b0000 {
compatible = "renesas,ipmmu-r8a77980";
reg = <0 0xfe6b0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 12>;
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_vi0: mmu@febd0000 {
compatible = "renesas,ipmmu-r8a77980";
reg = <0 0xfebd0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 14>;
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
avb: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a77980",
"renesas,etheravb-rcar-gen3";
@@ -623,6 +596,302 @@ scif4: serial@e6c40000 {
status = "disabled";
};
vin0: video@e6ef0000 {
compatible = "renesas,vin-r8a77980";
reg = <0 0xe6ef0000 0 0x1000>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 811>;
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 811>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
vin0csi40: endpoint@2 {
reg = <2>;
remote-endpoint = <&csi40vin0>;
};
};
};
};
vin1: video@e6ef1000 {
compatible = "renesas,vin-r8a77980";
reg = <0 0xe6ef1000 0 0x1000>;
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 810>;
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
status = "disabled";
resets = <&cpg 810>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
vin1csi40: endpoint@2 {
reg = <2>;
remote-endpoint = <&csi40vin1>;
};
};
};
};
vin2: video@e6ef2000 {
compatible = "renesas,vin-r8a77980";
reg = <0 0xe6ef2000 0 0x1000>;
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 809>;
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 809>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
vin2csi40: endpoint@2 {
reg = <2>;
remote-endpoint = <&csi40vin2>;
};
};
};
};
vin3: video@e6ef3000 {
compatible = "renesas,vin-r8a77980";
reg = <0 0xe6ef3000 0 0x1000>;
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 808>;
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 808>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
vin3csi40: endpoint@2 {
reg = <2>;
remote-endpoint = <&csi40vin3>;
};
};
};
};
vin4: video@e6ef4000 {
compatible = "renesas,vin-r8a77980";
reg = <0 0xe6ef4000 0 0x1000>;
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 807>;
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 807>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
vin4csi41: endpoint@2 {
reg = <2>;
remote-endpoint = <&csi41vin4>;
};
};
};
};
vin5: video@e6ef5000 {
compatible = "renesas,vin-r8a77980";
reg = <0 0xe6ef5000 0 0x1000>;
interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 806>;
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 806>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
vin5csi41: endpoint@2 {
reg = <2>;
remote-endpoint = <&csi41vin5>;
};
};
};
};
vin6: video@e6ef6000 {
compatible = "renesas,vin-r8a77980";
reg = <0 0xe6ef6000 0 0x1000>;
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 805>;
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 805>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
vin6csi41: endpoint@2 {
reg = <2>;
remote-endpoint = <&csi41vin6>;
};
};
};
};
vin7: video@e6ef7000 {
compatible = "renesas,vin-r8a77980";
reg = <0 0xe6ef7000 0 0x1000>;
interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 804>;
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 804>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
vin7csi41: endpoint@2 {
reg = <2>;
remote-endpoint = <&csi41vin7>;
};
};
};
};
vin8: video@e6ef8000 {
compatible = "renesas,vin-r8a77980";
reg = <0 0xe6ef8000 0 0x1000>;
interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 628>;
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 628>;
status = "disabled";
};
vin9: video@e6ef9000 {
compatible = "renesas,vin-r8a77980";
reg = <0 0xe6ef9000 0 0x1000>;
interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 627>;
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 627>;
status = "disabled";
};
vin10: video@e6efa000 {
compatible = "renesas,vin-r8a77980";
reg = <0 0xe6efa000 0 0x1000>;
interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 625>;
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 625>;
status = "disabled";
};
vin11: video@e6efb000 {
compatible = "renesas,vin-r8a77980";
reg = <0 0xe6efb000 0 0x1000>;
interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 618>;
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 618>;
status = "disabled";
};
vin12: video@e6efc000 {
compatible = "renesas,vin-r8a77980";
reg = <0 0xe6efc000 0 0x1000>;
interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 612>;
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 612>;
status = "disabled";
};
vin13: video@e6efd000 {
compatible = "renesas,vin-r8a77980";
reg = <0 0xe6efd000 0 0x1000>;
interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 608>;
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 608>;
status = "disabled";
};
vin14: video@e6efe000 {
compatible = "renesas,vin-r8a77980";
reg = <0 0xe6efe000 0 0x1000>;
interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 605>;
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 605>;
status = "disabled";
};
vin15: video@e6eff000 {
compatible = "renesas,vin-r8a77980";
reg = <0 0xe6eff000 0 0x1000>;
interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 604>;
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 604>;
status = "disabled";
};
dmac1: dma-controller@e7300000 {
compatible = "renesas,dmac-r8a77980",
"renesas,rcar-dmac";
@@ -703,6 +972,69 @@ gether: ethernet@e7400000 {
status = "disabled";
};
ipmmu_ds1: mmu@e7740000 {
compatible = "renesas,ipmmu-r8a77980";
reg = <0 0xe7740000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 0>;
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_ir: mmu@ff8b0000 {
compatible = "renesas,ipmmu-r8a77980";
reg = <0 0xff8b0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 3>;
power-domains = <&sysc R8A77980_PD_A3IR>;
#iommu-cells = <1>;
};
ipmmu_mm: mmu@e67b0000 {
compatible = "renesas,ipmmu-r8a77980";
reg = <0 0xe67b0000 0 0x1000>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_rt: mmu@ffc80000 {
compatible = "renesas,ipmmu-r8a77980";
reg = <0 0xffc80000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 10>;
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_vc0: mmu@fe6b0000 {
compatible = "renesas,ipmmu-r8a77980";
reg = <0 0xfe6b0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 12>;
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_vi0: mmu@febd0000 {
compatible = "renesas,ipmmu-r8a77980";
reg = <0 0xfebd0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 14>;
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_vip0: mmu@e7b00000 {
compatible = "renesas,ipmmu-r8a77980";
reg = <0 0xe7b00000 0 0x1000>;
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_vip1: mmu@e7960000 {
compatible = "renesas,ipmmu-r8a77980";
reg = <0 0xe7960000 0 0x1000>;
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
mmc0: mmc@ee140000 {
compatible = "renesas,sdhi-r8a77980",
"renesas,rcar-gen3-sdhi";
@@ -732,6 +1064,38 @@ gic: interrupt-controller@f1010000 {
resets = <&cpg 408>;
};
pciec: pcie@fe000000 {
compatible = "renesas,pcie-r8a77980",
"renesas,pcie-rcar-gen3";
reg = <0 0xfe000000 0 0x80000>;
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x00 0xff>;
device_type = "pci";
ranges = <
0x01000000 0 0x00000000 0 0xfe100000 0 0x0100000
0x02000000 0 0xfe200000 0 0xfe200000 0 0x0200000
0x02000000 0 0x30000000 0 0x30000000 0 0x8000000
0x42000000 0 0x38000000 0 0x38000000 0 0x8000000
>;
dma-ranges = <0x42000000 0 0x40000000 0 0x40000000
0 0x80000000>;
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 148
IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
clock-names = "pcie", "pcie_bus";
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 319>;
phys = <&pcie_phy>;
phy-names = "pcie";
status = "disabled";
};
vspd0: vsp@fea20000 {
compatible = "renesas,vsp2";
reg = <0 0xfea20000 0 0x5000>;
@@ -750,6 +1114,84 @@ fcpvd0: fcp@fea27000 {
resets = <&cpg 603>;
};
csi40: csi2@feaa0000 {
compatible = "renesas,r8a77980-csi2";
reg = <0 0xfeaa0000 0 0x10000>;
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 716>;
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 716>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
csi40vin0: endpoint@0 {
reg = <0>;
remote-endpoint = <&vin0csi40>;
};
csi40vin1: endpoint@1 {
reg = <1>;
remote-endpoint = <&vin1csi40>;
};
csi40vin2: endpoint@2 {
reg = <2>;
remote-endpoint = <&vin2csi40>;
};
csi40vin3: endpoint@3 {
reg = <3>;
remote-endpoint = <&vin3csi40>;
};
};
};
};
csi41: csi2@feab0000 {
compatible = "renesas,r8a77980-csi2";
reg = <0 0xfeab0000 0 0x10000>;
interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 715>;
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 715>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
csi41vin4: endpoint@0 {
reg = <0>;
remote-endpoint = <&vin4csi41>;
};
csi41vin5: endpoint@1 {
reg = <1>;
remote-endpoint = <&vin5csi41>;
};
csi41vin6: endpoint@2 {
reg = <2>;
remote-endpoint = <&vin6csi41>;
};
csi41vin7: endpoint@3 {
reg = <3>;
remote-endpoint = <&vin7csi41>;
};
};
};
};
du: display@feb00000 {
compatible = "renesas,du-r8a77980",
"renesas,du-r8a77970";

24
arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
View File

@@ -67,6 +67,16 @@ mux {
};
};
pwm3_pins: pwm3 {
groups = "pwm3_b";
function = "pwm3";
};
pwm5_pins: pwm5 {
groups = "pwm5_a";
function = "pwm5";
};
usb0_pins: usb {
groups = "usb0_b";
function = "usb0";
@@ -78,6 +88,20 @@ usb30_pins: usb30 {
};
};
&pwm3 {
pinctrl-0 = <&pwm3_pins>;
pinctrl-names = "default";
status = "okay";
};
&pwm5 {
pinctrl-0 = <&pwm5_pins>;
pinctrl-names = "default";
status = "okay";
};
&rwdt {
timeout-sec = <60>;
status = "okay";

478
arch/arm64/boot/dts/renesas/r8a77990.dtsi
View File

@@ -1,11 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Device Tree Source for the r8a77990 SoC
* Device Tree Source for the R-Car E3 (R8A77990) SoC
*
* Copyright (C) 2018 Renesas Electronics Corp.
*/
#include <dt-bindings/clock/renesas-cpg-mssr.h>
#include <dt-bindings/clock/r8a77990-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/r8a77990-sysc.h>
@@ -14,6 +14,17 @@ / {
#address-cells = <2>;
#size-cells = <2>;
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
i2c7 = &i2c7;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -22,7 +33,7 @@ a53_0: cpu@0 {
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0>;
device_type = "cpu";
power-domains = <&sysc 5>;
power-domains = <&sysc R8A77990_PD_CA53_CPU0>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
};
@@ -31,14 +42,14 @@ a53_1: cpu@1 {
compatible = "arm,cortex-a53", "arm,armv8";
reg = <1>;
device_type = "cpu";
power-domains = <&sysc 6>;
power-domains = <&sysc R8A77990_PD_CA53_CPU1>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
};
L2_CA53: cache-controller-0 {
compatible = "cache";
power-domains = <&sysc 21>;
power-domains = <&sysc R8A77990_PD_CA53_SCU>;
cache-unified;
cache-level = <2>;
};
@@ -63,6 +74,13 @@ psci {
method = "smc";
};
/* External SCIF clock - to be overridden by boards that provide it */
scif_clk: scif {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
soc: soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
@@ -75,7 +93,7 @@ rwdt: watchdog@e6020000 {
"renesas,rcar-gen3-wdt";
reg = <0 0xe6020000 0 0x0c>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc 32>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 402>;
status = "disabled";
};
@@ -91,7 +109,7 @@ gpio0: gpio@e6050000 {
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 912>;
power-domains = <&sysc 32>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 912>;
};
@@ -106,7 +124,7 @@ gpio1: gpio@e6051000 {
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 911>;
power-domains = <&sysc 32>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 911>;
};
@@ -121,7 +139,7 @@ gpio2: gpio@e6052000 {
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 910>;
power-domains = <&sysc 32>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 910>;
};
@@ -136,7 +154,7 @@ gpio3: gpio@e6053000 {
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 909>;
power-domains = <&sysc 32>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 909>;
};
@@ -151,7 +169,7 @@ gpio4: gpio@e6054000 {
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 908>;
power-domains = <&sysc 32>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 908>;
};
@@ -166,7 +184,7 @@ gpio5: gpio@e6055000 {
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 907>;
power-domains = <&sysc 32>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 907>;
};
@@ -181,10 +199,122 @@ gpio6: gpio@e6055400 {
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 906>;
power-domains = <&sysc 32>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 906>;
};
i2c0: i2c@e6500000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a77990",
"renesas,rcar-gen3-i2c";
reg = <0 0xe6500000 0 0x40>;
interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 931>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 931>;
i2c-scl-internal-delay-ns = <110>;
status = "disabled";
};
i2c1: i2c@e6508000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a77990",
"renesas,rcar-gen3-i2c";
reg = <0 0xe6508000 0 0x40>;
interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 930>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 930>;
i2c-scl-internal-delay-ns = <6>;
status = "disabled";
};
i2c2: i2c@e6510000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a77990",
"renesas,rcar-gen3-i2c";
reg = <0 0xe6510000 0 0x40>;
interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 929>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 929>;
i2c-scl-internal-delay-ns = <6>;
status = "disabled";
};
i2c3: i2c@e66d0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a77990",
"renesas,rcar-gen3-i2c";
reg = <0 0xe66d0000 0 0x40>;
interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 928>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 928>;
i2c-scl-internal-delay-ns = <110>;
status = "disabled";
};
i2c4: i2c@e66d8000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a77990",
"renesas,rcar-gen3-i2c";
reg = <0 0xe66d8000 0 0x40>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 927>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 927>;
i2c-scl-internal-delay-ns = <6>;
status = "disabled";
};
i2c5: i2c@e66e0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a77990",
"renesas,rcar-gen3-i2c";
reg = <0 0xe66e0000 0 0x40>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 919>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 919>;
i2c-scl-internal-delay-ns = <6>;
status = "disabled";
};
i2c6: i2c@e66e8000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a77990",
"renesas,rcar-gen3-i2c";
reg = <0 0xe66e8000 0 0x40>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 918>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 918>;
i2c-scl-internal-delay-ns = <6>;
status = "disabled";
};
i2c7: i2c@e6690000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a77990",
"renesas,rcar-gen3-i2c";
reg = <0 0xe6690000 0 0x40>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 1003>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 1003>;
i2c-scl-internal-delay-ns = <6>;
status = "disabled";
};
pfc: pin-controller@e6060000 {
compatible = "renesas,pfc-r8a77990";
reg = <0 0xe6060000 0 0x508>;
@@ -211,6 +341,108 @@ sysc: system-controller@e6180000 {
#power-domain-cells = <1>;
};
dmac0: dma-controller@e6700000 {
compatible = "renesas,dmac-r8a77990",
"renesas,rcar-dmac";
reg = <0 0xe6700000 0 0x10000>;
interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD 219>;
clock-names = "fck";
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 219>;
#dma-cells = <1>;
dma-channels = <16>;
};
dmac1: dma-controller@e7300000 {
compatible = "renesas,dmac-r8a77990",
"renesas,rcar-dmac";
reg = <0 0xe7300000 0 0x10000>;
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD 218>;
clock-names = "fck";
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 218>;
#dma-cells = <1>;
dma-channels = <16>;
};
dmac2: dma-controller@e7310000 {
compatible = "renesas,dmac-r8a77990",
"renesas,rcar-dmac";
reg = <0 0xe7310000 0 0x10000>;
interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD 217>;
clock-names = "fck";
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 217>;
#dma-cells = <1>;
dma-channels = <16>;
};
ipmmu_ds0: mmu@e6740000 {
compatible = "renesas,ipmmu-r8a77990";
reg = <0 0xe6740000 0 0x1000>;
@@ -329,7 +561,7 @@ avb: ethernet@e6800000 {
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
power-domains = <&sysc 32>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
#address-cells = <1>;
@@ -337,18 +569,191 @@ avb: ethernet@e6800000 {
status = "disabled";
};
pwm0: pwm@e6e30000 {
compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
reg = <0 0xe6e30000 0 0x8>;
clocks = <&cpg CPG_MOD 523>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 523>;
#pwm-cells = <2>;
status = "disabled";
};
pwm1: pwm@e6e31000 {
compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
reg = <0 0xe6e31000 0 0x8>;
clocks = <&cpg CPG_MOD 523>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 523>;
#pwm-cells = <2>;
status = "disabled";
};
pwm2: pwm@e6e32000 {
compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
reg = <0 0xe6e32000 0 0x8>;
clocks = <&cpg CPG_MOD 523>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 523>;
#pwm-cells = <2>;
status = "disabled";
};
pwm3: pwm@e6e33000 {
compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
reg = <0 0xe6e33000 0 0x8>;
clocks = <&cpg CPG_MOD 523>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 523>;
#pwm-cells = <2>;
status = "disabled";
};
pwm4: pwm@e6e34000 {
compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
reg = <0 0xe6e34000 0 0x8>;
clocks = <&cpg CPG_MOD 523>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 523>;
#pwm-cells = <2>;
status = "disabled";
};
pwm5: pwm@e6e35000 {
compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
reg = <0 0xe6e35000 0 0x8>;
clocks = <&cpg CPG_MOD 523>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 523>;
#pwm-cells = <2>;
status = "disabled";
};
pwm6: pwm@e6e36000 {
compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
reg = <0 0xe6e36000 0 0x8>;
clocks = <&cpg CPG_MOD 523>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 523>;
#pwm-cells = <2>;
status = "disabled";
};
scif2: serial@e6e88000 {
compatible = "renesas,scif-r8a77990",
"renesas,rcar-gen3-scif", "renesas,scif";
reg = <0 0xe6e88000 0 64>;
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 310>;
clock-names = "fck";
power-domains = <&sysc 32>;
clocks = <&cpg CPG_MOD 310>,
<&cpg CPG_CORE R8A77990_CLK_S3D1C>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 310>;
status = "disabled";
};
msiof0: spi@e6e90000 {
compatible = "renesas,msiof-r8a77990",
"renesas,rcar-gen3-msiof";
reg = <0 0xe6e90000 0 0x0064>;
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 211>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 211>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
msiof1: spi@e6ea0000 {
compatible = "renesas,msiof-r8a77990",
"renesas,rcar-gen3-msiof";
reg = <0 0xe6ea0000 0 0x0064>;
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 210>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 210>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
msiof2: spi@e6c00000 {
compatible = "renesas,msiof-r8a77990",
"renesas,rcar-gen3-msiof";
reg = <0 0xe6c00000 0 0x0064>;
interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 209>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 209>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
msiof3: spi@e6c10000 {
compatible = "renesas,msiof-r8a77990",
"renesas,rcar-gen3-msiof";
reg = <0 0xe6c10000 0 0x0064>;
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 208>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 208>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
vin4: video@e6ef4000 {
compatible = "renesas,vin-r8a77990";
reg = <0 0xe6ef4000 0 0x1000>;
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 807>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 807>;
renesas,id = <4>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
vin4csi40: endpoint {
remote-endpoint= <&csi40vin4>;
};
};
};
};
vin5: video@e6ef5000 {
compatible = "renesas,vin-r8a77990";
reg = <0 0xe6ef5000 0 0x1000>;
interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 806>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 806>;
renesas,id = <5>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
vin5csi40: endpoint {
remote-endpoint= <&csi40vin5>;
};
};
};
};
xhci0: usb@ee000000 {
compatible = "renesas,xhci-r8a77990",
"renesas,rcar-gen3-xhci";
@@ -367,7 +772,7 @@ ohci0: usb@ee080000 {
clocks = <&cpg CPG_MOD 703>;
phys = <&usb2_phy0>;
phy-names = "usb";
power-domains = <&sysc 32>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 703>;
status = "disabled";
};
@@ -380,7 +785,7 @@ ehci0: usb@ee080100 {
phys = <&usb2_phy0>;
phy-names = "usb";
companion = <&ohci0>;
power-domains = <&sysc 32>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 703>;
status = "disabled";
};
@@ -391,7 +796,7 @@ usb2_phy0: usb-phy@ee080200 {
reg = <0 0xee080200 0 0x700>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 703>;
power-domains = <&sysc 32>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 703>;
#phy-cells = <0>;
status = "disabled";
@@ -410,10 +815,41 @@ gic: interrupt-controller@f1010000 {
(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD 408>;
clock-names = "clk";
power-domains = <&sysc 32>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 408>;
};
csi40: csi2@feaa0000 {
compatible = "renesas,r8a77990-csi2", "renesas,rcar-gen3-csi2";
reg = <0 0xfeaa0000 0 0x10000>;
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 716>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 716>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
csi40vin4: endpoint@0 {
reg = <0>;
remote-endpoint = <&vin4csi40>;
};
csi40vin5: endpoint@1 {
reg = <1>;
remote-endpoint = <&vin5csi40>;
};
};
};
};
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;

300
arch/arm64/boot/dts/renesas/r8a77995-draak.dts
View File

@@ -24,38 +24,6 @@ chosen {
stdout-path = "serial0:115200n8";
};
vga {
compatible = "vga-connector";
port {
vga_in: endpoint {
remote-endpoint = <&adv7123_out>;
};
};
};
vga-encoder {
compatible = "adi,adv7123";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7123_in: endpoint {
remote-endpoint = <&du_out_rgb>;
};
};
port@1 {
reg = <1>;
adv7123_out: endpoint {
remote-endpoint = <&vga_in>;
};
};
};
};
composite-in {
compatible = "composite-video-connector";
@@ -101,6 +69,38 @@ reg_3p3v: regulator1 {
regulator-always-on;
};
vga {
compatible = "vga-connector";
port {
vga_in: endpoint {
remote-endpoint = <&adv7123_out>;
};
};
};
vga-encoder {
compatible = "adi,adv7123";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7123_in: endpoint {
remote-endpoint = <&du_out_rgb>;
};
};
port@1 {
reg = <1>;
adv7123_out: endpoint {
remote-endpoint = <&vga_in>;
};
};
};
};
x12_clk: x12 {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -108,69 +108,47 @@ x12_clk: x12 {
};
};
&extal_clk {
clock-frequency = <48000000>;
&avb {
pinctrl-0 = <&avb0_pins>;
pinctrl-names = "default";
renesas,no-ether-link;
phy-handle = <&phy0>;
phy-mode = "rgmii-txid";
status = "okay";
phy0: ethernet-phy@0 {
rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <&gpio5>;
interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
};
};
&pfc {
avb0_pins: avb {
mux {
groups = "avb0_link", "avb0_mdio", "avb0_mii";
function = "avb0";
&du {
pinctrl-0 = <&du_pins>;
pinctrl-names = "default";
status = "okay";
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&x12_clk>;
clock-names = "du.0", "du.1", "dclkin.0";
ports {
port@0 {
endpoint {
remote-endpoint = <&adv7123_in>;
};
};
};
};
du_pins: du {
groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
function = "du";
};
&ehci0 {
status = "okay";
};
i2c0_pins: i2c0 {
groups = "i2c0";
function = "i2c0";
};
i2c1_pins: i2c1 {
groups = "i2c1";
function = "i2c1";
};
pwm0_pins: pwm0 {
groups = "pwm0_c";
function = "pwm0";
};
pwm1_pins: pwm1 {
groups = "pwm1_c";
function = "pwm1";
};
scif2_pins: scif2 {
groups = "scif2_data";
function = "scif2";
};
sdhi2_pins: sd2 {
groups = "mmc_data8", "mmc_ctrl";
function = "mmc";
power-source = <1800>;
};
sdhi2_pins_uhs: sd2_uhs {
groups = "mmc_data8", "mmc_ctrl";
function = "mmc";
power-source = <1800>;
};
usb0_pins: usb0 {
groups = "usb0";
function = "usb0";
};
vin4_pins_cvbs: vin4 {
groups = "vin4_data8", "vin4_sync", "vin4_clk";
function = "vin4";
};
&extal_clk {
clock-frequency = <48000000>;
};
&i2c0 {
@@ -178,12 +156,6 @@ &i2c0 {
pinctrl-names = "default";
status = "okay";
eeprom@50 {
compatible = "rohm,br24t01", "atmel,24c01";
reg = <0x50>;
pagesize = <8>;
};
composite-in@20 {
compatible = "adi,adv7180cp";
reg = <0x20>;
@@ -254,6 +226,12 @@ adv7612_out: endpoint {
};
};
};
eeprom@50 {
compatible = "rohm,br24t01", "atmel,24c01";
reg = <0x50>;
pagesize = <8>;
};
};
&i2c1 {
@@ -262,47 +240,88 @@ &i2c1 {
status = "okay";
};
&du {
pinctrl-0 = <&du_pins>;
pinctrl-names = "default";
status = "okay";
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&x12_clk>;
clock-names = "du.0", "du.1", "dclkin.0";
ports {
port@0 {
endpoint {
remote-endpoint = <&adv7123_in>;
};
};
};
};
&ehci0 {
status = "okay";
};
&ohci0 {
status = "okay";
};
&avb {
pinctrl-0 = <&avb0_pins>;
pinctrl-names = "default";
renesas,no-ether-link;
phy-handle = <&phy0>;
phy-mode = "rgmii-txid";
status = "okay";
phy0: ethernet-phy@0 {
rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <&gpio5>;
interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
&pfc {
avb0_pins: avb {
mux {
groups = "avb0_link", "avb0_mdio", "avb0_mii";
function = "avb0";
};
};
du_pins: du {
groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
function = "du";
};
i2c0_pins: i2c0 {
groups = "i2c0";
function = "i2c0";
};
i2c1_pins: i2c1 {
groups = "i2c1";
function = "i2c1";
};
pwm0_pins: pwm0 {
groups = "pwm0_c";
function = "pwm0";
};
pwm1_pins: pwm1 {
groups = "pwm1_c";
function = "pwm1";
};
scif2_pins: scif2 {
groups = "scif2_data";
function = "scif2";
};
sdhi2_pins: sd2 {
groups = "mmc_data8", "mmc_ctrl";
function = "mmc";
power-source = <1800>;
};
sdhi2_pins_uhs: sd2_uhs {
groups = "mmc_data8", "mmc_ctrl";
function = "mmc";
power-source = <1800>;
};
usb0_pins: usb0 {
groups = "usb0";
function = "usb0";
};
vin4_pins_cvbs: vin4 {
groups = "vin4_data8", "vin4_sync", "vin4_clk";
function = "vin4";
};
};
&pwm0 {
pinctrl-0 = <&pwm0_pins>;
pinctrl-names = "default";
status = "okay";
};
&pwm1 {
pinctrl-0 = <&pwm1_pins>;
pinctrl-names = "default";
status = "okay";
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&scif2 {
@@ -333,25 +352,6 @@ &usb2_phy0 {
status = "okay";
};
&pwm0 {
pinctrl-0 = <&pwm0_pins>;
pinctrl-names = "default";
status = "okay";
};
&pwm1 {
pinctrl-0 = <&pwm1_pins>;
pinctrl-names = "default";
status = "okay";
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&vin4 {
pinctrl-0 = <&vin4_pins_cvbs>;
pinctrl-names = "default";

14
arch/arm64/boot/dts/renesas/r8a77995.dtsi
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the r8a77995 SoC
* Device Tree Source for the R-Car D3 (R8A77995) SoC
*
* Copyright (C) 2016 Renesas Electronics Corp.
* Copyright (C) 2017 Glider bvba
@@ -391,6 +391,10 @@ GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
resets = <&cpg 219>;
#dma-cells = <1>;
dma-channels = <8>;
iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
<&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
<&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
<&ipmmu_ds0 6>, <&ipmmu_ds0 7>;
};
dmac1: dma-controller@e7300000 {
@@ -415,6 +419,10 @@ GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
resets = <&cpg 218>;
#dma-cells = <1>;
dma-channels = <8>;
iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
<&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
<&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
<&ipmmu_ds1 6>, <&ipmmu_ds1 7>;
};
dmac2: dma-controller@e7310000 {
@@ -439,6 +447,10 @@ GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
resets = <&cpg 217>;
#dma-cells = <1>;
dma-channels = <8>;
iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
<&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
<&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
<&ipmmu_ds1 22>, <&ipmmu_ds1 23>;
};
ipmmu_ds0: mmu@e6740000 {

7
arch/arm64/boot/dts/renesas/salvator-common.dtsi
View File

@@ -420,7 +420,10 @@ csa_dvfs: adc@7f {
video-receiver@70 {
compatible = "adi,adv7482";
reg = <0x70>;
reg = <0x70 0x71 0x72 0x73 0x74 0x75
0x60 0x61 0x62 0x63 0x64 0x65>;
reg-names = "main", "dpll", "cp", "hdmi", "edid", "repeater",
"infoframe", "cbus", "cec", "sdp", "txa", "txb" ;
#address-cells = <1>;
#size-cells = <0>;
@@ -748,6 +751,7 @@ &sdhi0 {
wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
bus-width = <4>;
sd-uhs-sdr50;
sd-uhs-sdr104;
status = "okay";
};
@@ -777,6 +781,7 @@ &sdhi3 {
wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
bus-width = <4>;
sd-uhs-sdr50;
sd-uhs-sdr104;
status = "okay";
};

2
arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
View File

@@ -127,7 +127,7 @@ i2cswitch4: i2c-switch@71 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x71>;
reset-gpios= <&gpio3 15 GPIO_ACTIVE_LOW>;
reset-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>;
};
};

1
arch/arm64/boot/dts/renesas/ulcb.dtsi
View File

@@ -416,6 +416,7 @@ &sdhi0 {
cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
bus-width = <4>;
sd-uhs-sdr50;
sd-uhs-sdr104;
status = "okay";
};