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Author SHA1 Message Date
Kathiravan T
0360f0ea8c arm64: dts: qcom: add IPQ5332 SoC and MI01.2 board support 
Add initial device tree support for the Qualcomm IPQ5332 SoC and
MI01.2 board.

Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230307062232.4889-9-quic_kathirav@quicinc.com
 2023-03-15 16:23:06 -07:00
Krzysztof Kozlowski
5ff9e238a1 arm64: dts: qcom: msm8996-oneplus: do not enable incomplete nodes 
status=okay should appear in final place where all required properties
are provided, because that makes the code the easiest to read.  Move the
status from common OnePlus DTSI to board DTS.  No functional changes.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230308125906.236885-11-krzysztof.kozlowski@linaro.org
 2023-03-15 15:42:03 -07:00
Krzysztof Kozlowski
a369c74243 arm64: dts: qcom: sc7280: fix EUD port properties 
Nodes with unit addresses must have also 'reg' property:

  sc7280-herobrine-crd.dtb: eud@88e0000: ports:port@0: 'reg' is a required property

Fixes: 0b05997909 ("arm64: dts: qcom: sc7280: Add EUD dt node and dwc3 connector")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Souradeep Chowdhury <quic_schowdhu@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230308125906.236885-10-krzysztof.kozlowski@linaro.org
 2023-03-15 15:42:02 -07:00
Krzysztof Kozlowski
e96d20585c arm64: dts: qcom: msm8994: correct RPMCC node name 
The bindings expect RPM clock controller subnode to be named
'clock-controller':

  apq8094-sony-xperia-kitakami-karin_windy.dtb: smd: rpm:rpm-requests: 'rpmcc' does not match any of the regexes: '^regulators(-[01])?$', 'pinctrl-[0-9]+'

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230308125906.236885-9-krzysztof.kozlowski@linaro.org
 2023-03-15 15:42:02 -07:00
Krzysztof Kozlowski
9bc3dc3c9d arm64: dts: qcom: msm8953: drop clocks from RPMPD 
The RPM power domain controller does not take XO clock as input
(according to bindings and Linux driver):

  msm8953-xiaomi-vince.dtb: rpm-requests: power-controller: 'clock-names', 'clocks' do not match any of the regexes: 'pinctrl-[0-9]+'

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230308125906.236885-8-krzysztof.kozlowski@linaro.org
 2023-03-15 15:42:02 -07:00
Krzysztof Kozlowski
35343312a4 arm64: dts: qcom: msm8953: correct RPMCC node name 
The bindings expect RPM clock controller subnode to be named
'clock-controller':

  msm8953-motorola-potter.dtb: smd: rpm:rpm-requests: 'rpmcc' does not match any of the regexes: '^regulators(-[01])?$', 'pinctrl-[0-9]+'

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230308125906.236885-7-krzysztof.kozlowski@linaro.org
 2023-03-15 15:42:02 -07:00
Krzysztof Kozlowski
afa8eb675f arm64: dts: qcom: ipq6018-cp01-c1: drop SPI cs-select 
The SPI controller nodes do not use/allow cs-select property:

  ipq6018-cp01-c1.dtb: spi@78b5000: Unevaluated properties are not allowed ('cs-select' was unexpected)

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230308125906.236885-6-krzysztof.kozlowski@linaro.org
 2023-03-15 15:42:02 -07:00
Krzysztof Kozlowski
9b0ff841f0 arm64: dts: qcom: apq8096-db820c: drop SPI label 
The SPI controller nodes do not use/allow label property:

  apq8096-db820c.dtb: spi@7575000: Unevaluated properties are not allowed ('label' was unexpected)

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230308125906.236885-5-krzysztof.kozlowski@linaro.org
 2023-03-15 15:42:02 -07:00
Krzysztof Kozlowski
9135ab4a53 arm64: dts: qcom: sdm845-db845c: drop SPI label 
The SPI controller nodes do not use/allow label property:

  sdm845-db845c.dtb: spi@888000: Unevaluated properties are not allowed ('label' was unexpected)

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230308125906.236885-4-krzysztof.kozlowski@linaro.org
 2023-03-15 15:42:02 -07:00
Krzysztof Kozlowski
9b8bfc4433 arm64: dts: qcom: qdu1000: drop incorrect serial properties 
The serial node does not use/allow address/size cells:

  qdu1000-idp.dtb: geniqup@9c0000: serial@99c000: Unevaluated properties are not allowed ('#address-cells', '#size-cells' were unexpected)

Fixes: 6bd20c54b5 ("arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230308125906.236885-3-krzysztof.kozlowski@linaro.org
 2023-03-15 15:42:02 -07:00
Krzysztof Kozlowski
d24539a6a9 arm64: dts: qcom: sm8250: drop incorrect Coresight funnel properties 
There is only one output port, thus out-ports should not have
'address/size-cells' and unit addresses.  'reg-names' are also not
allowed by bindings.

  qrb5165-rb5.dtb: funnel@6042000: out-ports: '#address-cells', '#size-cells', 'port@0' do not match any of the regexes: 'pinctrl-[0-9]+'
  qrb5165-rb5.dtb: funnel@6b04000: Unevaluated properties are not allowed ('reg-names' was unexpected)

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230308125906.236885-2-krzysztof.kozlowski@linaro.org
 2023-03-15 15:42:02 -07:00
Krzysztof Kozlowski
d882778eb4 arm64: dts: qcom: drop incorrect cell-index from SPMI 
The SPMI controller (PMIC Arbiter)) does not use nor allow 'cell-index'
property:

  sm8150-microsoft-surface-duo.dtb: spmi@c440000: Unevaluated properties are not allowed ('cell-index' was unexpected)

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230308125906.236885-1-krzysztof.kozlowski@linaro.org
 2023-03-15 15:41:53 -07:00
Bartosz Golaszewski
9ebaa4a8cd arm64: dts: qcom: sm8150: fix the uart9 label 
There's a typo in the @<address> part of the uart9 label. Fix it.

Fixes: 10d900a834 ("arm64: dts: sm8150: add the QUPv3 high-speed UART node")
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230315202751.1518543-1-brgl@bgdev.pl
 2023-03-15 15:31:46 -07:00
Manivannan Sadhasivam
65d9975e5d arm64: dts: qcom: sm6350: Fix the base addresses of LLCC banks 
The LLCC block has several banks each with a different base address
and holes in between. So it is not a correct approach to cover these
banks with a single offset/size. Instead, the individual bank's base
address needs to be specified in devicetree with the exact size.

On SM6350, there is only one LLCC bank available. So let's just pass that
as "llcc0_base".

Reported-by: Parikshit Pareek <quic_ppareek@quicinc.com>
Tested-by: Luca Weiss <luca.weiss@fairphone.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230314080443.64635-12-manivannan.sadhasivam@linaro.org
 2023-03-15 15:17:22 -07:00
Manivannan Sadhasivam
413c8ecd48 arm64: dts: qcom: sm8450: Fix the base addresses of LLCC banks 
The LLCC block has several banks each with a different base address
and holes in between. So it is not a correct approach to cover these
banks with a single offset/size. Instead, the individual bank's base
address needs to be specified in devicetree with the exact size.

Reported-by: Parikshit Pareek <quic_ppareek@quicinc.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230314080443.64635-11-manivannan.sadhasivam@linaro.org
 2023-03-15 15:17:22 -07:00
Manivannan Sadhasivam
7ae317cba6 arm64: dts: qcom: sm8350: Fix the base addresses of LLCC banks 
The LLCC block has several banks each with a different base address
and holes in between. So it is not a correct approach to cover these
banks with a single offset/size. Instead, the individual bank's base
address needs to be specified in devicetree with the exact size.

Reported-by: Parikshit Pareek <quic_ppareek@quicinc.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230314080443.64635-10-manivannan.sadhasivam@linaro.org
 2023-03-15 15:17:22 -07:00
Manivannan Sadhasivam
42c9b15782 arm64: dts: qcom: sm8250: Fix the base addresses of LLCC banks 
The LLCC block has several banks each with a different base address
and holes in between. So it is not a correct approach to cover these
banks with a single offset/size. Instead, the individual bank's base
address needs to be specified in devicetree with the exact size.

Reported-by: Parikshit Pareek <quic_ppareek@quicinc.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230314080443.64635-9-manivannan.sadhasivam@linaro.org
 2023-03-15 15:17:21 -07:00
Manivannan Sadhasivam
c5ccf8d33f arm64: dts: qcom: sm8150: Fix the base addresses of LLCC banks 
The LLCC block has several banks each with a different base address
and holes in between. So it is not a correct approach to cover these
banks with a single offset/size. Instead, the individual bank's base
address needs to be specified in devicetree with the exact size.

Reported-by: Parikshit Pareek <quic_ppareek@quicinc.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230314080443.64635-8-manivannan.sadhasivam@linaro.org
 2023-03-15 15:17:21 -07:00
Manivannan Sadhasivam
0fe0955a79 arm64: dts: qcom: sc8280xp: Fix the base addresses of LLCC banks 
The LLCC block has several banks each with a different base address
and holes in between. So it is not a correct approach to cover these
banks with a single offset/size. Instead, the individual bank's base
address needs to be specified in devicetree with the exact size.

Reported-by: Parikshit Pareek <quic_ppareek@quicinc.com>
Tested-by: Steev Klimaszewski <steev@kali.org> # Thinkpad X13s
Tested-by: Andrew Halaney <ahalaney@redhat.com> # sa8540p-ride
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230314080443.64635-7-manivannan.sadhasivam@linaro.org
 2023-03-15 15:17:21 -07:00
Manivannan Sadhasivam
62e5ee9db9 arm64: dts: qcom: sc7280: Fix the base addresses of LLCC banks 
The LLCC block has several banks each with a different base address
and holes in between. So it is not a correct approach to cover these
banks with a single offset/size. Instead, the individual bank's base
address needs to be specified in devicetree with the exact size.

While at it, let's also fix the size of the llcc_broadcast_base to cover
the whole region.

Reported-by: Parikshit Pareek <quic_ppareek@quicinc.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230314080443.64635-6-manivannan.sadhasivam@linaro.org
 2023-03-15 15:17:21 -07:00
Manivannan Sadhasivam
116a932bbc arm64: dts: qcom: sc7180: Fix the base addresses of LLCC banks 
The LLCC block has several banks each with a different base address
and holes in between. So it is not a correct approach to cover these
banks with a single offset/size. Instead, the individual bank's base
address needs to be specified in devicetree with the exact size.

On SC7180, there is only one LLCC bank available. So let's just pass that
as "llcc0_base".

Reported-by: Parikshit Pareek <quic_ppareek@quicinc.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230314080443.64635-5-manivannan.sadhasivam@linaro.org
 2023-03-15 15:17:21 -07:00
Manivannan Sadhasivam
bfe088bde3 arm64: dts: qcom: sdm845: Fix the base addresses of LLCC banks 
The LLCC block has several banks each with a different base address
and holes in between. So it is not a correct approach to cover these
banks with a single offset/size. Instead, the individual bank's base
address needs to be specified in devicetree with the exact size.

On SDM845, the size of the LLCC bank 0 needs to be reduced to 0x4500 as
there are LLCC BWMON registers located after this range.

Reported-by: Parikshit Pareek <quic_ppareek@quicinc.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230314080443.64635-4-manivannan.sadhasivam@linaro.org
 2023-03-15 15:17:21 -07:00
Konrad Dybcio
d0af0537e2 arm64: dts: qcom: msm8996: Add missing DWC3 quirks 
Add missing dwc3 quirks from msm-3.18. Unfortunately, none of them
make `dwc3-qcom 6af8800.usb: HS-PHY not in L2` go away.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230302011849.1873056-1-konrad.dybcio@linaro.org
 2023-03-14 19:30:48 -07:00
Mukesh Ojha
d39469f5ce arm64: dts: qcom: sm8450: Add IMEM and PIL info region 
Add a simple-mfd representing IMEM on SM8450 and define the PIL
relocation info region, so that post mortem tools will be able
to locate the loaded remoteprocs.

Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/1677079845-17650-1-git-send-email-quic_mojha@quicinc.com
 2023-03-14 19:30:48 -07:00
Bartosz Golaszewski
5d793ff406 arm64: dts: qcom: sa8775p: add cpufreq node 
Add a node for the cpufreq engine and specify the frequency domains for
all CPUs.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230221150543.283487-3-brgl@bgdev.pl
 2023-03-14 19:30:48 -07:00
Krzysztof Kozlowski
aec576821e arm64: dts: qcom: apq8096-db820c: fix indentation 
Correct indentation.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230220094339.47370-2-krzysztof.kozlowski@linaro.org
 2023-03-14 19:30:48 -07:00
Krzysztof Kozlowski
5a1816cc2d arm64: dts: qcom: msm8996: move WCD9335 audio codec to boards 
The WCD9335 audio codec on Slimbus is a property of a board, not SoC,
thus it should not be present in MSM8996 DTSI.  Keep it in specific
boards, so it won't appear incomplete in the boards not having it.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230220094339.47370-1-krzysztof.kozlowski@linaro.org
 2023-03-14 19:30:47 -07:00
Konrad Dybcio
78c61b6b2c arm64: dts: qcom: sm8350: Add qcom,smmu-500 to Adreno SMMU 
Add the fallback Qualcomm SMMU500 compatible to the Adreno SMMU.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230216145646.4095336-5-konrad.dybcio@linaro.org
 2023-03-14 19:30:47 -07:00
Konrad Dybcio
8347b12e90 arm64: dts: qcom: sm8250: Add qcom,smmu-500 to Adreno SMMU 
Add the fallback Qualcomm SMMU500 compatible to the Adreno SMMU.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230216145646.4095336-4-konrad.dybcio@linaro.org
 2023-03-14 19:30:47 -07:00
Konrad Dybcio
3e5c002568 arm64: dts: qcom: sm8150: Add qcom,smmu-500 to Adreno SMMU 
Add the fallback Qualcomm SMMU500 compatible to the Adreno SMMU.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230216145646.4095336-3-konrad.dybcio@linaro.org
 2023-03-14 19:30:47 -07:00
Konrad Dybcio
c564b69984 arm64: dts: qcom: sc7280: Add qcom,smmu-500 to Adreno SMMU 
Add the fallback Qualcomm SMMU500 compatible to the Adreno SMMU.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230216145646.4095336-2-konrad.dybcio@linaro.org
 2023-03-14 19:30:47 -07:00
Manivannan Sadhasivam
0e6538e2d9 arm64: dts: qcom: sm6115: Supply clock from cpufreq node to CPUs 
Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks
to the CPU cores. But this relationship is not represented in DTS so far.

So let's make cpufreq node as the clock provider and CPU nodes as the
consumers. The clock index for each CPU node is based on the frequency
domain index.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230215070400.5901-13-manivannan.sadhasivam@linaro.org
 2023-03-14 19:30:47 -07:00
Manivannan Sadhasivam
d9ab57eec3 arm64: dts: qcom: sm6375: Supply clock from cpufreq node to CPUs 
Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks
to the CPU cores. But this relationship is not represented in DTS so far.

So let's make cpufreq node as the clock provider and CPU nodes as the
consumers. The clock index for each CPU node is based on the frequency
domain index.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230215070400.5901-12-manivannan.sadhasivam@linaro.org
 2023-03-14 19:30:47 -07:00
Manivannan Sadhasivam
2051f735b3 arm64: dts: qcom: sc8280xp: Supply clock from cpufreq node to CPUs 
Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks
to the CPU cores. But this relationship is not represented in DTS so far.

So let's make cpufreq node as the clock provider and CPU nodes as the
consumers. The clock index for each CPU node is based on the frequency
domain index.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230215070400.5901-11-manivannan.sadhasivam@linaro.org
 2023-03-14 19:30:47 -07:00
Manivannan Sadhasivam
c2a18730f0 arm64: dts: qcom: sm8350: Supply clock from cpufreq node to CPUs 
Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks
to the CPU cores. But this relationship is not represented in DTS so far.

So let's make cpufreq node as the clock provider and CPU nodes as the
consumers. The clock index for each CPU node is based on the frequency
domain index.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230215070400.5901-10-manivannan.sadhasivam@linaro.org
 2023-03-14 19:30:47 -07:00
Manivannan Sadhasivam
fc7258948c arm64: dts: qcom: sm8150: Supply clock from cpufreq node to CPUs 
Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks
to the CPU cores. But this relationship is not represented in DTS so far.

So let's make cpufreq node as the clock provider and CPU nodes as the
consumers. The clock index for each CPU node is based on the frequency
domain index.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230215070400.5901-9-manivannan.sadhasivam@linaro.org
 2023-03-14 19:30:47 -07:00
Manivannan Sadhasivam
7b39c98ff7 arm64: dts: qcom: sc7180: Supply clock from cpufreq node to CPUs 
Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks
to the CPU cores. But this relationship is not represented in DTS so far.

So let's make cpufreq node as the clock provider and CPU nodes as the
consumers. The clock index for each CPU node is based on the frequency
domain index.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230215070400.5901-8-manivannan.sadhasivam@linaro.org
 2023-03-14 19:30:47 -07:00
Manivannan Sadhasivam
fcca74d893 arm64: dts: qcom: qdu1000: Supply clock from cpufreq node to CPUs 
Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks
to the CPU cores. But this relationship is not represented in DTS so far.

So let's make cpufreq node as the clock provider and CPU nodes as the
consumers. The clock index for each CPU node is based on the frequency
domain index.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230215070400.5901-7-manivannan.sadhasivam@linaro.org
 2023-03-14 19:30:47 -07:00
Manivannan Sadhasivam
d78cb07dbc arm64: dts: qcom: sm8250: Supply clock from cpufreq node to CPUs 
Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks
to the CPU cores. But this relationship is not represented in DTS so far.

So let's make cpufreq node as the clock provider and CPU nodes as the
consumers. The clock index for each CPU node is based on the frequency
domain index.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230215070400.5901-6-manivannan.sadhasivam@linaro.org
 2023-03-14 19:30:47 -07:00
Manivannan Sadhasivam
1b0911fe3e arm64: dts: qcom: sm8550: Supply clock from cpufreq node to CPUs 
Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks
to the CPU cores. But this relationship is not represented in DTS so far.

So let's make cpufreq node as the clock provider and CPU nodes as the
consumers. The clock index for each CPU node is based on the frequency
domain index.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230215070400.5901-5-manivannan.sadhasivam@linaro.org
 2023-03-14 19:30:47 -07:00
Manivannan Sadhasivam
afa34380d9 arm64: dts: qcom: sm6350: Supply clock from cpufreq node to CPUs 
Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks
to the CPU cores. But this relationship is not represented in DTS so far.

So let's make cpufreq node as the clock provider and CPU nodes as the
consumers. The clock index for each CPU node is based on the frequency
domain index.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230215070400.5901-4-manivannan.sadhasivam@linaro.org
 2023-03-14 19:30:47 -07:00
Manivannan Sadhasivam
667d8a2039 arm64: dts: qcom: sc7280: Supply clock from cpufreq node to CPUs 
Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks
to the CPU cores. But this relationship is not represented in DTS so far.

So let's make cpufreq node as the clock provider and CPU nodes as the
consumers. The clock index for each CPU node is based on the frequency
domain index.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230215070400.5901-3-manivannan.sadhasivam@linaro.org
 2023-03-14 19:30:47 -07:00
Manivannan Sadhasivam
2af2ef08c0 arm64: dts: qcom: sdm845: Supply clock from cpufreq node to CPUs 
Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks
to the CPU cores. But this relationship is not represented in DTS so far.

So let's make cpufreq node as the clock provider and CPU nodes as the
consumers. The clock index for each CPU node is based on the frequency
domain index.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230215070400.5901-2-manivannan.sadhasivam@linaro.org
 2023-03-14 19:30:46 -07:00
Bartosz Golaszewski
603f96d4c9 arm64: dts: qcom: add initial support for qcom sa8775p-ride 
This adds basic support for the Qualcomm sa8775p platform and the
reference board: sa8775p-ride. The dt files describe the basics of the
SoC and enable booting to shell.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230214092713.211054-3-brgl@bgdev.pl
 2023-03-14 19:30:46 -07:00
Konrad Dybcio
0d589dc92f arm64: dts: qcom: pm8998: Add a specific compatible for coincell chg 
Add a PM8998-specific compatible to the coincell charger and keep the
PM8941 one as fallback.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230214090849.2186370-3-konrad.dybcio@linaro.org
 2023-03-14 19:30:46 -07:00
Konrad Dybcio
b5d08f0837 arm64: dts: qcom: msm8998: Fix stm-stimulus-base reg name 
The name stm-data-base comes from ancient (msm-3.10 or older)
downstream kernels. Upstream uses stm-stimulus-base instead. Fix it.

Fixes: 783abfa224 ("arm64: dts: qcom: msm8998: Add Coresight support")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230213210331.2106877-1-konrad.dybcio@linaro.org
 2023-03-14 19:30:46 -07:00
Konrad Dybcio
5a0c6d4349 arm64: dts: qcom: sm6375: Add RMTFS 
Add a node for RMTFS on SM6375.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230213175928.1979637-1-konrad.dybcio@linaro.org
 2023-03-14 19:30:46 -07:00
Krzysztof Kozlowski
d228efe884 arm64: dts: qcom: sm8550-qrd: add QRD8550 
Add a minimal DTS for the new QRD8550 board - a mobile-like development
board with SM8550.  Serial, UFS and USB should be working.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230210163844.765074-2-krzysztof.kozlowski@linaro.org
 2023-03-14 19:30:46 -07:00
Abel Vesa
749078e38e arm64: dts: qcom: sm8550-mtp: Add eUSB2 repeater node 
Add the PMIC eUSB2 repeater node and add the usb-repeater
property to the eUSB2 PHY to allow it to be controlled by the
PHY driver.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230208190200.2966723-8-abel.vesa@linaro.org
 2023-03-14 19:30:46 -07:00
Neil Armstrong
fdaa922585 arm64: dts: qcom: pm8550b: Add eUSB2 repeater node 
Add nodes for the eUSB2 repeater found on the pm8550b SPMI PMIC.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230208190200.2966723-7-abel.vesa@linaro.org
 2023-03-14 19:30:46 -07:00