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Brian Masney
fa5573edd0 arm64: dts: qcom: sc8280xp: add rng device tree node 
Add the necessary device tree node for qcom,prng-ee so we can use the
hardware random number generator. This functionality was tested on a
SA8540p automotive development board using kcapi-rng from libkcapi.

Signed-off-by: Brian Masney <bmasney@redhat.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230103182229.37169-11-bmasney@redhat.com
 2023-01-18 18:03:15 -06:00
Brian Masney
1db9c1d127 arm64: dts: qcom: sc8280xp: add aliases for i2c4 and i2c21 
Add aliases for i2c4 and i2c21 to the crd and x13s DTS files so that
what's exposed to userspace doesn't change in the future if additional
i2c buses are enabled on these platforms.

Signed-off-by: Brian Masney <bmasney@redhat.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230103182229.37169-10-bmasney@redhat.com
 2023-01-18 18:03:14 -06:00
Brian Masney
e073899ec3 arm64: dts: qcom: sa8540p-ride: add i2c nodes 
Add the necessary nodes in order to get i2c0, i2c1, i2c12, i2c15, and
i2c18 functioning on the automotive board and exposed to userspace.

This work was derived from various patches that Qualcomm delivered
to Red Hat in a downstream kernel. This change was validated by using
i2c-tools 4.3.3 on CentOS Stream 9:

[root@localhost ~]# i2cdetect -l
i2c-0  i2c             Geni-I2C                                I2C adapter
i2c-1  i2c             Geni-I2C                                I2C adapter
i2c-12 i2c             Geni-I2C                                I2C adapter
i2c-15 i2c             Geni-I2C                                I2C adapter
i2c-18 i2c             Geni-I2C                                I2C adapter

[root@localhost ~]# i2cdetect -a -y 15
Warning: Can't use SMBus Quick Write command, will skip some addresses
     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f
00:
10:
20:
30: -- -- -- -- -- -- -- --
40:
50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
60:
70:

Signed-off-by: Brian Masney <bmasney@redhat.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Shazad Hussain <quic_shazhuss@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230103182229.37169-9-bmasney@redhat.com
 2023-01-18 18:02:51 -06:00
Brian Masney
3d256a90b3 arm64: dts: qcom: sc8280xp: add missing spi nodes 
Add the missing nodes for the spi buses that's present on this SoC.

This work was derived from various patches that Qualcomm delivered
to Red Hat in a downstream kernel.

Signed-off-by: Brian Masney <bmasney@redhat.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230103182229.37169-8-bmasney@redhat.com
 2023-01-18 18:02:51 -06:00
Brian Masney
645aaf0a38 arm64: dts: qcom: sc8280xp: add missing i2c nodes 
Add the missing nodes for the i2c buses that's present on this SoC.

This work was derived from various patches that Qualcomm delivered
to Red Hat in a downstream kernel.

Signed-off-by: Brian Masney <bmasney@redhat.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230103182229.37169-7-bmasney@redhat.com
 2023-01-18 18:02:51 -06:00
Brian Masney
31e62e862a arm64: dts: qcom: sc8280xp: rename qup0_i2c4 to i2c4 
In preparation for adding the missing SPI and I2C nodes to
sc8280xp.dtsi, it was decided to rename all of the existing qupX_
uart, spi, and i2c nodes to drop the qupX_ prefix. Let's go ahead
and rename qup0_i2c4 to i2c4.

Note that some nodes are moved in the file by this patch to preserve
the expected sort order in the file. Additionally, the properties
within the pinctrl state node are sorted to match the expected order
that's typically done in other DTs.

Signed-off-by: Brian Masney <bmasney@redhat.com>
Link: https://lore.kernel.org/lkml/20221212182314.1902632-1-bmasney@redhat.com/
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Tested-by: Steev Klimaszewski <steev@kali.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230103182229.37169-6-bmasney@redhat.com
 2023-01-18 18:02:51 -06:00
Brian Masney
6e1569ddfa arm64: dts: qcom: sc8280xp: rename qup2_i2c5 to i2c21 
In preparation for adding the missing SPI and I2C nodes to
sc8280xp.dtsi, it was decided to rename all of the existing qupX_
uart, spi, and i2c nodes to drop the qupX_ prefix. Let's go ahead
and rename qup2_i2c5 to i2c21. Under the old name, this was the 5th
index under qup2, which starts at index 16.

Note that some nodes are moved in the file by this patch to preserve
the expected sort order in the file. Additionally, the properties
within the pinctrl state node are sorted to match the expected order
that's typically done in other DTs.

Signed-off-by: Brian Masney <bmasney@redhat.com>
Link: https://lore.kernel.org/lkml/20221212182314.1902632-1-bmasney@redhat.com/
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Tested-by: Steev Klimaszewski <steev@kali.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230103182229.37169-5-bmasney@redhat.com
 2023-01-18 18:02:27 -06:00
Brian Masney
71bc1b4284 arm64: dts: qcom: sc8280xp: rename qup2_uart17 to uart17 
In preparation for adding the missing SPI and I2C nodes to
sc8280xp.dtsi, it was decided to rename all of the existing qupX_
uart, spi, and i2c nodes to drop the qupX_ prefix. Let's go ahead
and rename qup2_uart17 to uart17. Note that some nodes are moved in the
file by this patch to preserve the expected sort order in the file.

Signed-off-by: Brian Masney <bmasney@redhat.com>
Link: https://lore.kernel.org/lkml/20221212182314.1902632-1-bmasney@redhat.com/
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230103182229.37169-4-bmasney@redhat.com
 2023-01-18 18:01:33 -06:00
Konrad Dybcio
1d09705a64 arm64: dts: qcom: sm6115: Pad addresses to 8 hex digits 
Some addresses were 7-hex-digits long, or less. Fix that.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230102094642.74254-18-konrad.dybcio@linaro.org
 2023-01-18 17:59:02 -06:00
Konrad Dybcio
690e8993cc arm64: dts: qcom: msm8994-kitakami: Pad addresses to 8 hex digits 
Some addresses were 7-hex-digits long, or less. Fix that.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230102094642.74254-17-konrad.dybcio@linaro.org
 2023-01-18 17:58:27 -06:00
Konrad Dybcio
a58cde4d66 arm64: dts: qcom: sm8450: Pad addresses to 8 hex digits 
Some addresses were 7-hex-digits long, or less. Fix that.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230102094642.74254-16-konrad.dybcio@linaro.org
 2023-01-18 17:58:27 -06:00
Konrad Dybcio
426900a959 arm64: dts: qcom: msm8994-octagon: Pad addresses to 8 hex digits 
Some addresses were 7-hex-digits long, or less. Fix that.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230102094642.74254-15-konrad.dybcio@linaro.org
 2023-01-18 17:58:10 -06:00
Konrad Dybcio
94ca994d7e arm64: dts: qcom: sc7280: Pad addresses to 8 hex digits 
Some addresses were 7-hex-digits long, or less. Fix that.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230102094642.74254-14-konrad.dybcio@linaro.org
 2023-01-18 17:58:10 -06:00
Konrad Dybcio
26c471991d arm64: dts: qcom: sc7180: Pad addresses to 8 hex digits 
Some addresses were 7-hex-digits long, or less. Fix that.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230102094642.74254-13-konrad.dybcio@linaro.org
 2023-01-18 17:58:10 -06:00
Konrad Dybcio
f3c08ae6fe arm64: dts: qcom: sm8350: Pad addresses to 8 hex digits 
Some addresses were 7-hex-digits long, or less. Fix that.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230102094642.74254-12-konrad.dybcio@linaro.org
 2023-01-18 17:58:10 -06:00
Konrad Dybcio
81f43efce4 arm64: dts: qcom: sm8250: Pad addresses to 8 hex digits 
Some addresses were 7-hex-digits long, or less. Fix that.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230102094642.74254-11-konrad.dybcio@linaro.org
 2023-01-18 17:58:10 -06:00
Konrad Dybcio
524ac48fcc arm64: dts: qcom: sdm845: Pad addresses to 8 hex digits 
Some addresses were 7-hex-digits long, or less. Fix that.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230102094642.74254-10-konrad.dybcio@linaro.org
 2023-01-18 17:58:10 -06:00
Konrad Dybcio
f48dbb34e4 arm64: dts: qcom: sm6350: Pad addresses to 8 hex digits 
Some addresses were 7-hex-digits long, or less. Fix that.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230102094642.74254-9-konrad.dybcio@linaro.org
 2023-01-18 17:58:10 -06:00
Konrad Dybcio
f69732296a arm64: dts: qcom: sm8150: Pad addresses to 8 hex digits 
Some addresses were 7-hex-digits long, or less. Fix that.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230102094642.74254-8-konrad.dybcio@linaro.org
 2023-01-18 17:58:10 -06:00
Konrad Dybcio
8d5bf0b2dc arm64: dts: qcom: sc8280xp: Pad addresses to 8 hex digits 
Some addresses were 7-hex-digits long, or less. Fix that.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230102094642.74254-7-konrad.dybcio@linaro.org
 2023-01-18 17:58:10 -06:00
Konrad Dybcio
7356ae3e10 arm64: dts: qcom: ipq6018: Use lowercase hex 
One value escaped my previous lowercase hexification. Take care of it.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230102094642.74254-6-konrad.dybcio@linaro.org
 2023-01-18 17:58:10 -06:00
Konrad Dybcio
6db9ed9a12 arm64: dts: qcom: ipq6018: Add/remove some newlines 
Some lines were broken very aggresively, presumably to fit under 80 chars
and some places could have used a newline, particularly between subsequent
nodes. Address all that and remove redundant comments near PCIe ranges
while at it so as not to exceed 100 chars needlessly.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230102094642.74254-5-konrad.dybcio@linaro.org
 2023-01-18 17:58:10 -06:00
Konrad Dybcio
2c6e322a41 arm64: dts: qcom: ipq6018: Sort nodes properly 
Order nodes by unit address if one exists and alphabetically otherwise.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230102094642.74254-4-konrad.dybcio@linaro.org
 2023-01-18 17:58:09 -06:00
Konrad Dybcio
c2596b717e arm64: dts: qcom: ipq6018: Fix up indentation 
The dwc3 subnode was indented using spaces for some reason and other
properties were not exactly properly indented. Fix it.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230102094642.74254-3-konrad.dybcio@linaro.org
 2023-01-18 17:58:09 -06:00
Konrad Dybcio
647380e415 arm64: dts: qcom: ipq6018: Pad addresses to 8 hex digits 
Some addresses were 7-hex-digits long, or less. Fix that.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230102094642.74254-2-konrad.dybcio@linaro.org
 2023-01-18 17:58:09 -06:00
Abel Vesa
1eeef306b5 arm64: dts: qcom: sm8550-mtp: Add PCIe PHYs and controllers nodes 
Enable PCIe controllers and PHYs nodes on SM8550 MTP board.

Co-developed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230118230526.1499328-3-abel.vesa@linaro.org
 2023-01-18 17:54:04 -06:00
Abel Vesa
7d1158c984 arm64: dts: qcom: sm8550: Add PCIe PHYs and controllers nodes 
Add PCIe controllers and PHY nodes.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230118230526.1499328-2-abel.vesa@linaro.org
 2023-01-18 17:54:04 -06:00
Neil Armstrong
6c409f633f arm64: dts: qcom: sm8550-mtp: enable adsp, cdsp & mdss 
Add the aDSP, cDSP and MPSS firmware and "Devicetree" firmware paths
for the SM8550 MTP platform.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221115-topic-sm8550-upstream-dts-remoteproc-v3-3-815a1753de34@linaro.org
 2023-01-18 17:54:04 -06:00
Neil Armstrong
d0c061e366 arm64: dts: qcom: sm8550: add adsp, cdsp & mdss nodes 
This adds support for the aDSP, cDSP and MPSS Subsystems found in
the SM8550 SoC.

The aDSP, cDSP and MPSS needs:
- smp2p nodes to get event back from the subsystems
- remoteproc nodes with glink-edge subnodes providing all needed
  resources to start and run the subsystems

In addition, the MPSS Subsystem needs a rmtfs_mem dedicated
memory zone.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221115-topic-sm8550-upstream-dts-remoteproc-v3-2-815a1753de34@linaro.org
 2023-01-18 17:54:04 -06:00
Abel Vesa
2e3790de9b arm64: dts: qcom: sm8550: Add interconnect path to SCM node 
Add the interconnect path to SCM dts node.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221115-topic-sm8550-upstream-dts-remoteproc-v3-1-815a1753de34@linaro.org
 2023-01-18 17:54:04 -06:00
Neil Armstrong
a74c41f6dd arm64: dts: qcom: sm8550-mtp: add DSI panel 
Add nodes for the Visionox VTDR6130 found on the SM8550-MTP
device.

TLMM states are also added for the Panel reset GPIO and
Tearing Effect signal for when the panel is running in
DSI Command mode.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230104-topic-sm8550-upstream-dts-display-v4-3-1729cfc0e5db@linaro.org
 2023-01-18 17:54:04 -06:00
Neil Armstrong
69e6a5e29b arm64: dts: qcom: sm8550-mtp: enable display hardware 
Enable MDSS/DPU/DSI0 on SM8550-MTP device.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230104-topic-sm8550-upstream-dts-display-v4-2-1729cfc0e5db@linaro.org
 2023-01-18 17:54:04 -06:00
Neil Armstrong
d7da51db5b arm64: dts: qcom: sm8550: add display hardware devices 
Add devices tree nodes describing display hardware on SM8550:
- Display Clock Controller
- MDSS
- MDP
- two DSI controllers and DSI PHYs

This does not provide support for DP controllers present on the SM8550.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230104-topic-sm8550-upstream-dts-display-v4-1-1729cfc0e5db@linaro.org
 2023-01-18 17:54:04 -06:00
Bjorn Andersson
411f657db2 Merge branch '20230103-topic-sm8550-upstream-dispcc-v3-1-8a03d348c572@linaro.org' into HEAD 
Merge the DT binding in order to get the dispcc include file.
 2023-01-18 17:35:55 -06:00
Neil Armstrong
553f9bd455 dt-bindings: clock: document SM8550 DISPCC clock controller 
Document device tree bindings for display clock controller for
Qualcomm SM8550 SoC.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230103-topic-sm8550-upstream-dispcc-v3-1-8a03d348c572@linaro.org
 2023-01-18 17:34:47 -06:00
Pavankumar Kondeti
6612981205 arm64: dts: qcom: sm8550: fix xo clock source in cpufreq-hw node 
Currently, available frequencies for all CPUs are appearing as 2x
of the actual frequencies. Use xo clock source as bi_tcxo in the
cpufreq-hw node to fix this.

Signed-off-by: Pavankumar Kondeti <quic_pkondeti@quicinc.com>
Tested-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230117093533.3710000-1-quic_pkondeti@quicinc.com
 2023-01-18 17:33:10 -06:00
Markuss Broks
83a54e61b2 arm64: dts: qcom: msm8916-samsung-j5-common: Add MUIC support 
The MUIC installed is a part of SM5703 MFD, and it seems to work
the same as the SM5502 MUIC unit.

Signed-off-by: Markuss Broks <markuss.broks@gmail.com>
[Apply for msm8916-samsung-j5x]
Signed-off-by: Lin, Meng-Bo <linmengbo0689@protonmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230106143051.547302-1-linmengbo0689@protonmail.com
 2023-01-18 17:33:10 -06:00
Lin, Meng-Bo
027523b77c arm64: dts: qcom: msm8916-samsung-j5-common: Add Hall sensor 
Samsung Galaxy J5 2015 and 2016 have a Hall sensor on GPIO pin 52.
Add GPIO Hall sensor for them.

Signed-off-by: Lin, Meng-Bo <linmengbo0689@protonmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230106143037.547248-1-linmengbo0689@protonmail.com
 2023-01-18 17:33:10 -06:00
Lin, Meng-Bo
4414bdf9c5 arm64: dts: qcom: msm8916-samsung-j5-common: Add new device trees 
After moving msm8916-samsung-j5.dts to msm8916-samsung-j5-common.dtsi,
Add new J5 2016 device tree.

[Add j5x device tree]

Co-developed-by: Josef W Menad <JosefWMenad@protonmail.ch>
Signed-off-by: Josef W Menad <JosefWMenad@protonmail.ch>
[Use &pm8916_usbin as USB extcon and add chassis-type for j5x]
Co-developed-by: Stephan Gerhold <stephan@gerhold.net>
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
[Use common init device tree]
Signed-off-by: Lin, Meng-Bo <linmengbo0689@protonmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230106143024.547194-1-linmengbo0689@protonmail.com
 2023-01-18 17:33:10 -06:00
Lin, Meng-Bo
66e9ba516b arm64: dts: qcom: msm8916-samsung-j5-common: Add initial common device tree 
The smartphones below are using the MSM8916 SoC,
which are released in 2015-2016:

Samsung Galaxy J5 2015 (SM-J500*)
Samsung Galaxy J5 2016 (SM-J510*)

Move msm8916-samsung-j5.dts to msm8916-samsung-j5-common.dtsi, and add
a common device tree for with initial support for:

- GPIO keys
- SDHCI (internal and external storage)
- USB Device Mode
- UART (on USB connector via the SM5703 MUIC)
- WCNSS (WiFi/BT)
- Regulators

The two devices (all other variants of J5 released in 2015 and J5X
released in 2016) are very similar, with some differences in display and
GPIO pins. The common parts are shared in msm8916-samsung-j5-common.dtsi
to reduce duplication.

This patch rewrites J5 2015 devices, later patches will add support for
other models.

Signed-off-by: Lin, Meng-Bo <linmengbo0689@protonmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230106143010.547140-1-linmengbo0689@protonmail.com
 2023-01-18 17:33:10 -06:00
Luca Weiss
60bf874087 arm64: dts: qcom: sm7225-fairphone-fp4: enable IPA 
IPA is used for mobile data. Enable it.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230104193759.3286014-3-elder@linaro.org
 2023-01-18 17:33:10 -06:00
Luca Weiss
aed7154a30 arm64: dts: qcom: sm6350: add IPA node 
IPA is used for mobile data. Add a node describing it.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230104193759.3286014-2-elder@linaro.org
 2023-01-18 17:33:10 -06:00
Konrad Dybcio
bba952275b arm64: dts: qcom: sm6350: Set up DDR & L3 scaling 
Add the CPU OPP tables including core frequency and L3 bus frequency.
The L3 throughput values were chosen by studying the frequencies
available in HW LUT and picking the highest one that's less than the
CPU frequency. DDR clock rates come from the vendor kernel.

Available values from the HW LUT:
300000000
556800000
652800000
806400000
844800000
940800000
1132800000
1209600000
1286400000
1401600000
1459200000

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230104171643.1004054-3-konrad.dybcio@linaro.org
 2023-01-18 17:33:10 -06:00
Konrad Dybcio
e17a806571 arm64: dts: qcom: sm6350: Add OSM L3 node 
Enable the OSM block responsible for scaling the L3 cache.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230104171643.1004054-2-konrad.dybcio@linaro.org
 2023-01-18 17:33:10 -06:00
Dmitry Baryshkov
306ccdf078 arm64: dts: qcom: qcs404: specify per-sensor calibration cells 
Specify pre-parsed per-sensor calibration nvmem cells in the tsens
device node rather than parsing the whole data blob in the driver.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230101194034.831222-19-dmitry.baryshkov@linaro.org
 2023-01-18 17:33:10 -06:00
Dmitry Baryshkov
4d403f7a90 arm64: dts: qcom: msm8976: specify per-sensor calibration cells 
Specify pre-parsed per-sensor calibration nvmem cells in the tsens
device node rather than parsing the whole data blob in the driver.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230101194034.831222-18-dmitry.baryshkov@linaro.org
 2023-01-18 17:33:10 -06:00
Dmitry Baryshkov
24aafd041f arm64: dts: qcom: msm8916: specify per-sensor calibration cells 
Specify pre-parsed per-sensor calibration nvmem cells in the tsens
device node rather than parsing the whole data blob in the driver.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230101194034.831222-17-dmitry.baryshkov@linaro.org
 2023-01-18 17:33:10 -06:00
Dmitry Baryshkov
0b3aa9aa62 arm64: dts: qcom: msm8956: use SoC-specific compat for tsens 
The slope values used during tsens calibration differ between msm8976
and msm8956 SoCs. Use SoC-specific compat value for the msm8956 SoC.

Fixes: 0484d3ce09 ("arm64: dts: qcom: Add DTS for MSM8976 and MSM8956 SoCs")
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230101194034.831222-16-dmitry.baryshkov@linaro.org
 2023-01-18 17:33:10 -06:00
Alex Elder
a9a9e85731 arm64: dts: qcom: use qcom,gsi-loader for IPA 
Depending on the platform, either the modem or the AP must load GSI
firmware for IPA before it can be used.  To date, this has been
indicated by the presence or absence of a "modem-init" property.

That mechanism has been deprecated.  Instead, we indicate how GSI
firmware should be loaded by the value of the "qcom,gsi-loader"
property.

Update all arm64 platforms that use IPA to use the "qcom,gsi-loader"
property to specify how the GSI firmware is loaded.

Update the affected nodes so the status property is last.

Signed-off-by: Alex Elder <elder@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
[bjorn: Moved sc7280 change herobrine-lte-sku]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221231002716.2367375-3-elder@linaro.org
 2023-01-18 17:33:10 -06:00
Krzysztof Kozlowski
bf37b5bc72 arm64: dts: qcom: sc7280-idp: add amp pin config function 
Bindings expect each pin config to come with a "function" property:

  sc7280-crd-r3.dtb: pinctrl@f100000: amp-en-state: 'oneOf' conditional failed, one must be fixed:
    'function' is a required property
    'bias-pull-down', 'drive-strength', 'pins' do not match any of the regexes: '-pins$', 'pinctrl-[0-9]+'

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221230135645.56401-9-krzysztof.kozlowski@linaro.org
 2023-01-18 17:08:56 -06:00