Add flexspi node, flexspi has a special memory region mapped to
0x60000000~0x6fffffff. This region is for AHB usage. So add this region
to SoC ranges.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add cpuidle node and enable cpuidle for dual cores. The HW mode in
Arm Trusted Firmware is SoC Application Power Domain Sleep mode.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add thermal node. Cooling map is not added, because frequency runtime
changing not supported for now.
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Set default clock rate and parents for SDHC[0,1,2].
The PLL3 PFD2 maximum frequency is 332Mhz, we can't set it to 389Mhz
as USDHC clock parent. Because PLL3 PFD0 is used for NIC, PFD1 is used
for audio, the only choice is PFD3 which can reach to 400Mhz.
USDHC1 and USDHC2 maximum PCC clock rate is 200Mhz in Over Drive mode,
and 100Mhz in Nominal/Low Drive mode, when PTE or PTF is used.
The patch adjusts clock parent to PLL3 PFD3 DIV1 for USDHC0, PLL3
PFD3 DIV2 for USDHC1 and USDHC2. And set the max rate to meet
restrictions.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
There is no "vselect-en" property, neither in the bindings nor in the
Linux driver:
imx8mm-phyboard-polis-rdk.dtb: pmic@8: regulators:ldo2: Unevaluated properties are not allowed ('vselect-en' was unexpected)
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Yannic Moog <y.moog@phytec.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Cadence USB3 bindings specify a specific reg order. Adjust DT entries
to match the bindings.
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Alias names use dashes instead of underscores, fix this. Silences also
dtbs_check warning:
imx8qxp-tqma8xqp-mba8xx.dtb: aliases: 'vpu_core0', 'vpu_core1', 'vpu_core2'
do not match any of the regexes: '^[a-z][a-z0-9\\-]*$', 'pinctrl-[0-9]+'
from schema $id: http://devicetree.org/schemas/aliases.yaml#
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The Gateworks imx8mp-venice-gw73xx-2x consists of a SOM + baseboard.
The GW702x SOM contains the following:
- i.MX8M Plus SoC
- LPDDR4 memory
- eMMC Boot device
- Gateworks System Controller (GSC) with integrated EEPROM, button
controller, and ADC's
- PMIC
- SOM connector providing:
- eQoS GbE MII
- 1x SPI
- 2x I2C
- 4x UART
- 2x USB 3.0
- 1x PCI
- 1x SDIO (4-bit 3.3V)
- 1x SDIO (4-bit 3.3V/1.8V)
- GPIO
The GW73xx Baseboard contains the following:
- GPS
- microSD
- off-board I/O connector with SPI
- off-board I/O connector with I2C, and GPIO
- off-board I/O connector with MIPI DSI, MIPI CSI, I2C, and GPIO
- off-board I/O connector with RS232 and RS485
- EERPOM
- USB 3.0 HUB
- USB 3.0 TypeA socket
- USB 2.0 Micro-B OTG socket
- Accelerometer
- 1x GbE (eQoS)
- 1x GbE (PCI)
- PCIe clock generator
- PCIe switch
- 2x full-length miniPCIe socket with PCI and USB2.0
- 1x full-length miniPCIe socket with PCI/USB3 (via mux) SIM, and USB2.0
- 1x half-length miniPCIe socket with USB2.0 and USB3.0
- USB Type-C with USB PD Sink capability and peripheral support
- USB Type-C with USB 3.0 host support
- on-board 802.11abgnac with Bluetooth 5.2
- Wide range DC input supply
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The Gateworks imx8mp-venice-gw72xx-2x consists of a SOM + baseboard.
The GW702x SOM contains the following:
- i.MX8M Plus SoC
- LPDDR4 memory
- eMMC Boot device
- Gateworks System Controller (GSC) with integrated EEPROM, button
controller, and ADC's
- PMIC
- SOM connector providing:
- eQoS GbE MII
- 1x SPI
- 2x I2C
- 4x UART
- 2x USB 3.0
- 1x PCI
- 1x SDIO (4-bit 3.3V)
- 1x SDIO (4-bit 3.3V/1.8V)
- GPIO
The GW72xx Baseboard contains the following:
- GPS
- microSD
- off-board I/O connector with SPI
- off-board I/O connector with I2C, and GPIO
- off-board I/O connector with MIPI DSI, MIPI CSI, I2C, and GPIO
- off-board I/O connector with RS232 and RS485
- EERPOM
- USB 3.0 HUB
- USB 3.0 TypeA socket
- USB 2.0 Micro-B OTG socket
- Accelerometer
- 1x GbE (eQoS)
- 1x GbE (PCI)
- PCIe clock generator
- PCIe switch
- 1x full-length miniPCIe socket with PCI and USB2.0
- 1x full-length miniPCIe socket with PCI/USB3 (via mux) SIM, and USB2.0
- 1x half-length miniPCIe socket with USB2.0 and USB3.0
- USB Type-C with USB PD Sink capability and peripheral support
- USB Type-C with USB 3.0 host support
- Wide range DC input supply
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The Gateworks imx8mm-venice-gw7905-0x consists of a SOM + baseboard.
The GW700x SOM contains the following:
- i.MX8M Mini SoC
- LPDDR4 memory
- eMMC Boot device
- Gateworks System Controller (GSC) with integrated EEPROM, button
controller, and ADC's
- PMIC
- SOM connector providing:
- FEC GbE MII
- 1x SPI
- 2x I2C
- 4x UART
- 2x USB 2.0
- 1x PCI
- 1x SDIO (4-bit 3.3V)
- 1x SDIO (4-bit 3.3V/1.8V)
- GPIO
The GW7905 Baseboard contains the following:
- GPS
- microSD
- off-board I/O connector with I2C, SPI, GPIO
- EERPOM
- PCIe clock generator
- 1x full-length miniPCIe socket with PCI/USB3 (via mux) and USB2.0
- 1x half-length miniPCIe socket with USB2.0 and USB3.0
- USB 3.0 HUB
- USB Type-C with USB PD Sink capability and peripheral support
- USB Type-C with USB 3.0 host support
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add support for the following Raspberry Pi displays:
- DFROBOT DRF0678 7in 800x480 TFT DSI capacitive touch
- DFROBOT DRF0550 5in 800x480 TFT DSI capacitive touch
Both have the following hardware:
- FocalTech FT5406 10pt touch controller (with no interrupt)
- Powertip PH800480T013-IDF02 compatible panel
- Toshiba TC358762 compatible DSI to DBI bridge
- ATTINY based regulator used for backlight controller and panel enable
Support is added via a device-tree overlay. The touch controller is not
yet supported as polling mode is needed.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
USB OTG is currently not working for new versions of the Variscite
Symphony EVK and imx8mn nano SOM (versions >= 1.4a).
The PTN5150 circuitry on newer versions of the Symphony EVK board has
a non-standard configuration in which the PTN5150 IRQ pin is left
unconnected, and the PTN5150 ID pin is connected to GPIO1_IO11. This
requires changes to the ptn5150 driver to support this new mode.
Variscite have indicated their intention to submit those changes
upstream.
In the meantime, import device tree changes from linux-5.15 branch of
varigit repos to at least make the USB OTG port operate correctly in
host mode.
Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This appears to be enough for both Redpine and SparkLAN cards.
Waiting for too long makes us waste time in resume from system
suspend, so let's keep it as short as possible.
Signed-off-by: Sebastian Krzyszkowiak <sebastian.krzyszkowiak@puri.sm>
Signed-off-by: Martin Kepplinger <martin.kepplinger@puri.sm>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Unfortunately the codec can't be switched off on it's own. It would ground
the whole bus it's connected to (because of it's built-in diodes to VDD on
i2c pins), making all the other devices on the same bus inaccessible:
[ 0.237154] lm3692x 2-0036: Cannot read/clear faults: -11
[ 0.242628] lm3692x 2-0036: Fail writing initialization values
[ 0.286462] [drm:drm_bridge_attach] *ERROR* failed to attach bridge /soc@0/bus@30800000/mipi-dsi@30a00000 to encoder None-34: -517
Work around this hardware limitation by keeping audio-1v8 enabled.
Signed-off-by: Martin Kepplinger <martin.kepplinger@puri.sm>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add the missing usdhc2 root clock to 200MHz to be able to support
SDR104 mode for SD-Card on phyBOARD-Pollux-i.MX8MP.
Signed-off-by: Jonas Kuenstler <j.kuenstler@phytec.de>
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Set the regulator voltages to the min and max values the i.MX8MP
requires and not what the PMIC provides.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
We do not touch LDO2 and LDO4 in linux as they are bypassed.
So remove them completely from device tree.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Do not set reserved bits 0 and 3 in pad configuration.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Rearrange properties in order:
- compatible
- reg
- other generic properties
- device specific properties
- vendor specific properties
- status
And use alphabetical order inside a group.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
In some occasions the ethernet phy IRQ can not be detected correctly
by the SoC. This leads to a non detected link in Linux. The problem is
caused by the buffer that adjusts the voltage between ethernet phy
and SoC. To workaround this, remove the IRQ support for the ethernet
phy and use polling instead.
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This adds support for TQMa93xx module and MBa93xxLA SBC board.
TQMa93xx is a SOM using i.MX93 SOC. The SOM features PMIC, RAM, e-MMC and
some optional peripherals like SPI-NOR, RTC, EEPROM, gyroscope and
secure element.
TQMa93xxLA is a solder on type SOM and can be used directly on MBa93XXLA.
TQMa93xxCA is a feature compatible, socketable type SOM.
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
imx8mn-evk has a MIPI DSI port that can be used with a ADV7535 MIPI
DSI to HDMI bridge.
Add support for it.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The A72 nodes have been deleted in this DTB. Removes the corresponding
thermal zone to ensure a successful build.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Dtschema of the leds sub-node names expects "led-1" instead of led1.
So, the sub-node names are corrected according to the regexes.
Signed-off-by: Yashwanth Varakala <y.varakala@phytec.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add support for the following Raspberry Pi displays:
- DFROBOT DRF0678 7in 800x480 TFT DSI capacitive touch
- DFROBOT DRF0550 5in 800x480 TFT DSI capacitive touch
Both have the following hardware:
- FocalTech FT5406 10pt touch controller (with no interrupt)
- Powertip PH800480T013-IDF02 compatible panel
- Toshiba TC358762 compatible DSI to DBI bridge
- ATTINY based regulator used for backlight controller and panel enable
Support is added via a device-tree overlay. The touch controller is not
yet supported as polling mode is needed.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add support for the following Raspberry Pi displays:
- DFROBOT DRF0678 7in 800x480 TFT DSI capacitive touch
- DFROBOT DRF0550 5in 800x480 TFT DSI capacitive touch
Both have the following hardware:
- FocalTech FT5406 10pt touch controller (with no interrupt)
- Powertip PH800480T013-IDF02 compatible panel
- Toshiba TC358762 compatible DSI to DBI bridge
- ATTINY based regulator used for backlight controller and panel enable
Support is added via a device-tree overlay. The touch controller is not
yet supported as polling mode is needed.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The reg size of etm nodes is incorrectly set to 64k instead of 4k. This
leads to a crash when calling amba_read_periphid(). After corrected reg
size, amba_read_periphid() retrieve the correct periphid.
arm,primecell-periphid were removed from the etm nodes.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
i.MX93 and i.MX8ULP lpuart add some new featurs based on i.MX7ULP, for
example, i.MX93 and i.MX8ULP can support EOP(end-of-packet) function
while i.MX7ULP doesn't support, so add "fsl,imx8ulp-lpuart" compatible
string for i.MX93 to support those new features.
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Drop the i.MX8DXL backwards compatibility with i.MX7ULP since they
differ from clocks handling point of view.
dtbs_check has the following warnings:
linux-next/arch/arm64/boot/dts/freescale/imx8dxl-evk.dtb: serial@5a060000: compatible: 'oneOf' conditional failed, one must be fixed:
['fsl,imx8qxp-lpuart', 'fsl,imx7ulp-lpuart'] is too long
'fsl,imx93-lpuart' was expected
'fsl,imx8qxp-lpuart' is not one of ['fsl,imx8qm-lpuart', 'fsl,imx8dxl-lpuart']
'fsl,imxrt1050-lpuart' was expected
'fsl,imx8ulp-lpuart' was expected
'fsl,imx8qxp-lpuart' was expected
'fsl,imxrt1170-lpuart' was expected
From schema: linux-next/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add reserved memory node for rpmsg
Enable CM33 node with mailbox property included for doorbell.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
scl-gpios and sda-gpios need GPIO_OPEN_DRAIN flag, otherwise the
following run-time warning is seen:
gpio-144 (scl): enforced open drain please flag it properly in DT/ACPI DSDT/board file
gpio-146 (scl): enforced open drain please flag it properly in DT/ACPI DSDT/board file
Signed-off-by: Fabio Estevam <festevam@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Now that it is finally possible to get the MAC addresses from the OTP
memory, use it to set the addresses of the network devices.
There are 8 reserved MAC addresses in total per board. Distribute them
as follows:
+----------+------+------+------+------+------+
| | var1 | var2 | var3 | var4 | kbox |
+----------+------+------+------+------+------+
| enetc #0 | +0 | | | +0 | +0 |
| enetc #1 | | | +0 | +1 | +1 |
| enetc #2 | | +2 | | | +2 |
| enetc #3 | | +3 | | | +3 |
| felix p0 | | +0 | | | +4 |
| felix p1 | | +1 | | | +5 |
| felix p2 | | | | | +6 |
| felix p3 | | | | | +7 |
| felix p4 | | | | | |
| felix p5 | | | | | |
+----------+------+------+------+------+------+
An empty cell means, the port is not available and thus doesn't need an
ethernet address.
Signed-off-by: Michael Walle <mwalle@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
