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Johan Hovold
eb24bd3c59 arm64: dts: qcom: sc8280xp-x13s: enable USB MP and fingerprint reader 
Enable the multiport USB controller to which the fingerprint reader in
the X13s power button is connected.

Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20240501065641.965-1-johan+linaro@kernel.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-05-01 13:31:32 -05:00
Krishna Kurapati
3170a2c906 arm64: dts: qcom: sc8280xp: Add USB DWC3 Multiport controller 
Add USB and DWC3 node for tertiary port of SC8280 along with
Multiport interrupts and PHYs.

Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Tested-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20240429162048.2133512-2-quic_kriskura@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-05-01 13:30:44 -05:00
Connor Abbott
0d80ac75cb arm64: dts: qcom: sm8650: Fix GPU cx_mem size 
This is doubled compared to previous GPUs. We can't access the new
SW_FUSE_VALUE register without this.

Fixes: db33633b05 ("arm64: dts: qcom: sm8650: add GPU nodes")
Signed-off-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240426-a750-raytracing-v2-1-562ac9866d63@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-04-29 12:35:42 -05:00
Rong Zhang
873d845a35 dt-bindings: arm: qcom: Add Samsung Galaxy S5 China (kltechn) 
Document Samsung Galaxy S5 China (kltechn) as a klte variant based on
msm8974pro. Also including "samsung,klte" in the compatible chain as
kltechn works fine with the klte DTB except for LEDs and WiFi missing.

Signed-off-by: Rong Zhang <i@rong.moe>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240213110137.122737-4-i@rong.moe
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-04-23 08:00:06 -05:00
Dmitry Baryshkov
673b174b5b arm64: dts: qcom: qrb4210-rb1: add firmware-name qualifier to WiFi node 
Add firmware-name property to the WiFi device tree node to specify
board-specific lookup directory.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240306-wcn3990-firmware-path-v2-4-f89e98e71a57@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-04-22 08:11:58 -05:00
Dmitry Baryshkov
57ce4b27a1 arm64: dts: qcom: qrb2210-rb1: add firmware-name qualifier to WiFi node 
Add firmware-name property to the WiFi device tree node to specify
board-specific lookup directory.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240306-wcn3990-firmware-path-v2-3-f89e98e71a57@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-04-22 08:11:58 -05:00
Manivannan Sadhasivam
52358c6493 arm64: dts: qcom: ipq6018: Add PCIe bridge node 
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-16-1eb790c53e43@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-04-21 12:31:42 -05:00
Manivannan Sadhasivam
ed3893f6f9 arm64: dts: qcom: ipq8074: Add PCIe bridge node 
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-15-1eb790c53e43@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-04-21 12:31:42 -05:00
Manivannan Sadhasivam
71756c44f1 arm64: dts: qcom: msm8996: Add PCIe bridge node 
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-14-1eb790c53e43@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-04-21 12:31:42 -05:00
Manivannan Sadhasivam
a92af45c40 arm64: dts: qcom: sc8180x: Add PCIe bridge node 
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-13-1eb790c53e43@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-04-21 12:31:42 -05:00
Manivannan Sadhasivam
ed2f87cf51 arm64: dts: qcom: qcs404: Add PCIe bridge node 
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-12-1eb790c53e43@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-04-21 12:31:41 -05:00
Manivannan Sadhasivam
df307c906c arm64: dts: qcom: sc7280: Add PCIe bridge node 
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-11-1eb790c53e43@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-04-21 12:31:41 -05:00
Manivannan Sadhasivam
b328bf2595 arm64: dts: qcom: msm8998: Add PCIe bridge node 
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-10-1eb790c53e43@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-04-21 12:31:41 -05:00
Manivannan Sadhasivam
e6bbf39055 arm64: dts: qcom: sc8280xp: Add PCIe bridge node 
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.

While at it, let's remove the bridge properties from board dts as they are
now redundant.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-9-1eb790c53e43@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-04-21 12:31:41 -05:00
Manivannan Sadhasivam
3c3abb944d arm64: dts: qcom: sa8775p: Add PCIe bridge node 
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-8-1eb790c53e43@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-04-21 12:31:41 -05:00
Manivannan Sadhasivam
cf3e010d7f arm64: dts: qcom: sm8650: Add PCIe bridge node 
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-7-1eb790c53e43@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-04-21 12:31:41 -05:00
Manivannan Sadhasivam
cc2ad77882 arm64: dts: qcom: sm8550: Add PCIe bridge node 
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-6-1eb790c53e43@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-04-21 12:31:41 -05:00
Manivannan Sadhasivam
4261fd5358 arm64: dts: qcom: sm8450: Add PCIe bridge node 
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-5-1eb790c53e43@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-04-21 12:31:41 -05:00
Manivannan Sadhasivam
3b743d532e arm64: dts: qcom: sm8350: Add PCIe bridge node 
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-4-1eb790c53e43@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-04-21 12:31:41 -05:00
Manivannan Sadhasivam
8e0a95add7 arm64: dts: qcom: sm8150: Add PCIe bridge node 
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-3-1eb790c53e43@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-04-21 12:31:41 -05:00
Manivannan Sadhasivam
b8347ba382 arm64: dts: qcom: sdm845: Add PCIe bridge node 
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-2-1eb790c53e43@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-04-21 12:31:41 -05:00
Manivannan Sadhasivam
83d2a0a1e2 arm64: dts: qcom: sm8250: Add PCIe bridge node 
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-1-1eb790c53e43@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-04-21 12:31:41 -05:00
Caleb Connolly
d73ed58d7f arm64: dts: qcom: sdm845-db845c: make pcie0_3p3v_dual always-on 
This regulator is responsible not just for the PCIe 3.3v rail, but also
for 5v VBUS on the left USB port. There is currently no way to correctly
model this dependency on the USB controller, as a result when the PCIe
driver is not available (for example when in the initramfs) USB is
non-functional.

Until support is added for modelling this property (likely by
referencing it as a supply under a usb-connector node), let's just make
it always on. We don't target any power constrained usecases and this
regulator is required for USB to function correctly.

Fixes: 3f72e2d3e6 ("arm64: dts: qcom: Add Dragonboard 845c")
Suggested-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240320122515.3243711-1-caleb.connolly@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-04-21 12:31:34 -05:00
Udipto Goswami
17a188d927 arm64: dts: qcom: sm8450: Update SNPS Phy parameters for QRD platform 
Update SNPS Phy tuning parameters for sm8450 QRD platform to fix
electrical compliance failures.

Signed-off-by: Udipto Goswami <quic_ugoswami@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240321062834.21510-1-quic_ugoswami@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-04-21 12:27:09 -05:00
Konrad Dybcio
365e19c466 arm64: dts: qcom: sc8280xp: Fill in EAS properties 
Replace the bogus capacity-dmips-mhz values and add the measured
dynamic-power-coefficient values.

The power numbers were measured by matters much more precise than the
laggy and cache-y pmic_glink battery data, though the reported values
were only accurate to 10mA. But that shouldn't be an issue, especially
for the fat and power-hungry X1Cs and given that *each SoC unit* has
somewhat different frequency-voltage maps.

X1C cluster:
940 kHz, 596 mV, 434 mW, 663 Cx
1056 kHz, 612 mV, 463 mW, 565 Cx
1171 kHz, 628 mV, 502 mW, 574 Cx
1286 kHz, 644 mV, 534 mW, 540 Cx
1401 kHz, 660 mV, 580 mW, 550 Cx
1516 kHz, 688 mV, 630 mW, 529 Cx
1632 kHz, 712 mV, 690 mW, 533 Cx
1747 kHz, 728 mV, 722 mW, 503 Cx
1862 kHz, 752 mV, 787 mW, 504 Cx
1977 kHz, 776 mV, 855 mW, 503 Cx
2073 kHz, 792 mV, 913 mW, 504 Cx
2169 kHz, 812 mV, 989 mW, 514 Cx
2284 kHz, 856 mV, 1250 mW, 611 Cx
2400 kHz, 900 mV, 1441 mW, 626 Cx
2496 kHz, 932 mV, 1600 mW, 636 Cx
2592 kHz, 964 mV, 1790 mW, 653 Cx
2688 kHz, 1000 mV, 2020 mW, 673 Cx
2803 kHz, 1040 mV, 2292 mW, 687 Cx
2899 kHz, 1076 mV, 2572 mW, 706 Cx
2995 kHz, 1108 mV, 2850 mW, 721 Cx

A78C cluster:
403 kHz, 576 mV, 180 mW, 584 Cx
499 kHz, 576 mV, 200 mW, 605 Cx
595 kHz, 576 mV, 220 mW, 612 Cx
691 kHz, 576 mV, 230 mW, 541 Cx
806 kHz, 600 mV, 250 mW, 471 Cx
902 kHz, 620 mV, 270 mW, 444 Cx
1017 kHz, 640 mV, 290 mW, 409 Cx
1113 kHz, 652 mV, 310 mW, 401 Cx
1209 kHz, 668 mV, 320 mW, 363 Cx
1324 kHz, 700 mV, 490 mW, 600 Cx
1440 kHz, 724 mV, 523 mW, 554 Cx
1555 kHz, 800 mV, 660 mW, 558 Cx
1670 kHz, 800 mV, 780 mW, 639 Cx
1785 kHz, 804 mV, 910 mW, 711 Cx
1881 kHz, 824 mV, 941 mW, 663 Cx
1996 kHz, 856 mV, 980 mW, 601 Cx
2112 kHz, 880 mV, 1020 mW, 559 Cx
2227 kHz, 908 mV, 1090 mW, 535 Cx
2342 kHz, 932 mV, 1230 mW, 552 Cx
2438 kHz, 956 mV, 1351 mW, 559 Cx

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240319-topic-8280_eas-v1-1-c605b4ea063d@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-04-21 12:20:22 -05:00
Ling Xu
dae8cdb0a9 arm64: dts: qcom: sm8650: Add three missing fastrpc-compute-cb nodes 
Add three missing cDSP fastrpc compute-cb nodes for the SM8650 SoC.

Signed-off-by: Ling Xu <quic_lxu5@quicinc.com>
Link: https://lore.kernel.org/r/20240319032816.27070-1-quic_lxu5@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-04-21 12:19:59 -05:00
Neil Armstrong
b8cf87ca78 arm64: dts: qcom: sm8650-qrd: enable GPU 
Add path of the GPU firmware for the SM8650-QRD board

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Jun Nie <jun.nie@linaro.org>
Link: https://lore.kernel.org/r/20240318-topic-sm8650-gpu-v4-2-206eb0d31694@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-04-21 12:18:55 -05:00
Neil Armstrong
db33633b05 arm64: dts: qcom: sm8650: add GPU nodes 
Add GPU nodes for the SM8650 platform.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Acked-by: Jun Nie <jun.nie@linaro.org>
Link: https://lore.kernel.org/r/20240318-topic-sm8650-gpu-v4-1-206eb0d31694@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-04-21 12:18:55 -05:00
Danila Tikhonov
11525960fc arm64: dts: qcom: pm6150l: add Light Pulse Generator device node 
Add device node defining LPG/PWM block on PM6150L PMIC chip.

Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240306172710.59780-3-danila@jiaxyga.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-04-21 12:15:06 -05:00
Raymond Hackley
7c4b3191b3 arm64: dts: qcom: msm8916/39-samsung-a2015: Add connector for MUIC 
Add subnode usb_con: extcon for SM5502 / SM5504 MUIC, which will be used
for RT5033 charger.

Signed-off-by: Raymond Hackley <raymondhackley@protonmail.com>
Link: https://lore.kernel.org/r/20240215122605.3817-1-raymondhackley@protonmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-04-21 12:12:09 -05:00
Jianhua Lu
0a8ab4a834 arm64: dts: qcom: sm8250-xiaomi-elish: set pm8150b_vbus regulator-min-microamp and regulator-max-microamp 
Fix the dtb check warnings:
  sm8250-xiaomi-elish-boe.dtb: usb-vbus-regulator@1100: 'regulator-min-microamp' is a required property
  sm8250-xiaomi-elish-boe.dtb: usb-vbus-regulator@1100: 'regulator-max-microamp' is a required property

Fixes: 6965278727 ("arm64: dts: qcom: sm8250-xiaomi-elish: Add pm8150b type-c node and enable usb otg")
Signed-off-by: Jianhua Lu <lujianhua000@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240323100443.2478-1-lujianhua000@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-04-21 12:04:37 -05:00
Neil Armstrong
6aeeb94569 arm64: dts: qcom: sm8650: remove useless enablement of mdss_mdp 
The MDP/DPU device is not disabled by default, so there is not point in
enabling it in the board DTS file.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240325-topic-sm8x50-upstream-leave-mdss-enabled-by-default-v1-1-f1b380132075@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-04-21 12:04:29 -05:00
Krzysztof Kozlowski
6754fecd3b arm64: dts: qcom: sdx75: add unit address to soc node 
Soc node has ranges, thus it must have an unit address. This fixes W=1
dtc warning:

  sdx75.dtsi:399.11-736.4: Warning (unit_address_vs_reg): /soc: node has a reg or ranges property, but no unit name

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240325102924.26820-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-04-21 12:03:58 -05:00
Luca Weiss
62f87a3cac arm64: dts: qcom: sm6350: Add DisplayPort controller 
Add the node for the DisplayPort controller found on the SM6350 SoC.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240329-sm6350-dp-v2-3-e46dceb32ef5@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-04-21 12:01:22 -05:00
Komal Bajaj
ac6d35b9b7 arm64: dts: qcom: qcs6490-rb3gen2: Enable various remoteprocs 
Enable the ADSP, CDSP and WPSS that are found on qcs6490-rb3gen2.

Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240417120928.32344-3-quic_kbajaj@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-04-21 11:21:51 -05:00
Komal Bajaj
99a1c9eedf arm64: dts: qcom: qcm6490-idp: Enable various remoteprocs 
Enable the ADSP, CDSP, MPSS and WPSS that are found on the SoC.

Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
Link: https://lore.kernel.org/r/20240417120928.32344-2-quic_kbajaj@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-04-21 11:21:51 -05:00
Dmitry Baryshkov
d2dbb1047e arm64: dts: qcom: sc8180x-lenovo-flex-5g: add USB-C orientation GPIOs 
Define the USB-C orientation GPIOs so that the USB-C ports orientation
is known without having to resort to the altmode notifications.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240409-hdk-orientation-gpios-v2-5-658efd993987@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-04-20 13:00:20 -05:00
Dmitry Baryshkov
e34d83d968 arm64: dts: qcom: sc8280xp-lenovo-thinkpad-x13s: add USB-C orientation GPIOs 
Define the USB-C orientation GPIOs so that the USB-C ports orientation
is known without having to resort to the altmode notifications.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240409-hdk-orientation-gpios-v2-4-658efd993987@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-04-20 13:00:20 -05:00
Dmitry Baryshkov
70b47e7b76 arm64: dts: qcom: sm8450-hdk: add USB-C orientation GPIO 
Define the USB-C orientation GPIO so that the USB-C port orientation is
known without having to resort to the altmode notifications.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240409-hdk-orientation-gpios-v2-3-658efd993987@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-04-20 13:00:20 -05:00
Dmitry Baryshkov
defac2c098 arm64: dts: qcom: sm8350-hdk: add USB-C orientation GPIO 
Define the USB-C orientation GPIO so that the USB-C port orientation is
known without having to resort to the altmode notifications.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240409-hdk-orientation-gpios-v2-2-658efd993987@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-04-20 13:00:20 -05:00
Dmitry Baryshkov
254c101efd dt-bindings: soc: qcom: pmic-glink: allow orientation-gpios 
The orientation GPIOs are not limited to sm8450/sm8550/x1e8000
platforms. Allow corresponding property to be used on all Qualcom
platforms.

Fixes: 65682407f8 ("dt-bindings: soc: qcom: qcom,pmic-glink: add a gpio used to determine the Type-C port plug orientation")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240409-hdk-orientation-gpios-v2-1-658efd993987@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-04-20 13:00:20 -05:00
Luca Weiss
e788ef2bda arm64: dts: qcom: qcm6490-fairphone-fp5: Add USB-C orientation GPIO 
Define the USB-C orientation GPIOs so that the USB-C ports orientation
is known without having to resort to the altmode notifications.

On PCB level this is the signal from PM7250B (pin CC_OUT) which is
called USB_PHY_PS.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20240411-fp5-usb-c-gpio-v1-1-78f11deb940a@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-04-20 12:59:38 -05:00
Umang Chheda
776c5f3c9c arm64: dts: qcom: qcm6490-idp: Name the regulators 
Without explicitly specifying names for the regulators they are named
based on the DeviceTree node name. This results in multiple regulators
with the same name, making it impossible to reason debug prints and
regulator_summary.

Signed-off-by: Umang Chheda <quic_uchheda@quicinc.com>
Link: https://lore.kernel.org/r/20240412123237.2633000-1-quic_uchheda@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-04-20 12:59:02 -05:00
Volodymyr Babchuk
5927bc586a arm64: dts: qcom: sa8155p-adp: lower min volt for L13C regulator 
Voltage regulator L13C is used by SD card IO interface. In order to
support UHS modes, IO interface voltage needs to be set to 1.8V. This
patch extends minimum voltage range of L13C regulator to allow this.

Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Fixes: 0deb2624e2 ("arm64: dts: qcom: sa8155p-adp: Add support for uSD card")
Suggested-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20240412190310.1647893-2-volodymyr_babchuk@epam.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-04-20 12:58:45 -05:00
Abel Vesa
78a4407ca8 arm64: dts: qcom: x1e80100-qcp: Add data-lanes and link-frequencies to DP3 
The data-lanes are a property of the out remote endpoint, so move them
from mdss_dp3 to the mdss_dp3_out. Also add the link-frequencies to
mdss_dp3_out and make sure to include all frequencies.

Fixes: f9a9c11471 ("arm64: dts: qcom: x1e80100-qcp: Enable more support")
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240419-x1e80100-dts-fix-mdss-dp3-v2-3-10f4ed7a09b4@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-04-20 11:46:34 -05:00
Abel Vesa
2351d20508 arm64: dts: qcom: x1e80100-crd: Add data-lanes and link-frequencies to DP3 
The data-lanes are a property of the out remote endpoint, so move them
from mdss_dp3 to the mdss_dp3_out. Also add the link-frequencies to
mdss_dp3_out and make sure to include all frequencies.

Fixes: d7e03cce04 ("arm64: dts: qcom: x1e80100-crd: Enable more support")
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240419-x1e80100-dts-fix-mdss-dp3-v2-2-10f4ed7a09b4@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-04-20 11:46:34 -05:00
Abel Vesa
8a2a43a978 arm64: dts: qcom: x1e80100: Drop the link-frequencies from mdss_dp3_in 
The link-frequencies belong in mdss_dp3_out. Drop them from mdss_dp3_in.

Fixes: 1940c25eaa ("arm64: dts: qcom: x1e80100: Add display nodes")
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240419-x1e80100-dts-fix-mdss-dp3-v2-1-10f4ed7a09b4@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-04-20 11:46:34 -05:00
Konrad Dybcio
39c596304e arm64: dts: qcom: Add SM8550 Xperia 1 V 
Add support for Sony Xperia 1 V, a.k.a PDX234. This device is a part
of the SoMC SM8550 Yodo platform.

This commit brings support for:
* Remoteprocs (sans modem for now)
* Flash LED (the notification LED is gone :((((()
* SD Card
* USB (*including SuperSpeed*) + PMIC_GLINK (it's funky, requires a replug
  with an cable flip sometimes..)
* Most regulators
* Part of I2C-connected peripherals (notably no touch due to a
driver bug)
* PCIe0 (PCIe1 is unused)

Do note display via simplefb is not supported, as the display is blanked
upon exiting XBL.

To create a working boot image, you need to run:
cat arch/arm64/boot/Image.gz arch/arm64/boot/dts/qcom/sm8550-sony-xperia-\
yodo-pdx234.dtb > .Image.gz-dtb

mkbootimg \
--kernel .Image.gz-dtb \
--ramdisk some_initrd.img \
--pagesize 4096 \
--base 0x0 \
--kernel_offset 0x8000 \
--ramdisk_offset 0x1000000 \
--tags_offset 0x100 \
--cmdline "SOME_CMDLINE" \
--dtb_offset 0x1f00000 \
--header_version 2 \
-o boot.img-sony-xperia-pdx234

Then, you need to flash it on the device and get rid of all the
vendor_boot/dtbo mess:

// You have to either pull vbmeta{"","_system"} from
// /dev/block/bootdevice/by-name/ or build one as a part of AOSP build process
fastboot --disable-verity --disable-verification flash vbmeta vbmeta.img
fastboot --disable-verity --disable-verification flash vbmeta_system \
vbmeta_system.img

fastboot flash boot boot.img-sony-xperia-pdx234
fastboot erase vendor_boot
fastboot erase recovery
fastboot flash dtbo emptydtbo.img
fastboot erase init_boot // ? I don't remember if it's necessary, sorry
fastboot continue

Where emptydtbo.img is a tiny file that consists of 2 bytes (all zeroes), doing
a "fastboot erase" won't cut it, the bootloader will go crazy and things will
fall apart when it tries to overlay random bytes from an empty partition onto a
perfectly good appended DTB.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240210-topic-1v-v1-7-fda0db38e29b@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-04-15 20:54:03 -05:00
Konrad Dybcio
6e4f7e5399 arm64: dts: qcom: sm8550: Mark DWC3 as dma-coherent 
In a fairly new development, Qualcomm somehow made the DWC3 block
cache-coherent. Annotate that.

Fixes: 7f7e5c1b03 ("arm64: dts: qcom: sm8550: Add USB PHYs and controller nodes")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240210-topic-1v-v1-6-fda0db38e29b@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-04-15 20:54:03 -05:00
Konrad Dybcio
d18b5477dc arm64: dts: qcom: sm8550: Add missing DWC3 quirks 
As expected, Qualcomm DWC3 implementation come with a sizable number
of quirks. Make sure to account for all of them.

Fixes: 7f7e5c1b03 ("arm64: dts: qcom: sm8550: Add USB PHYs and controller nodes")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240210-topic-1v-v1-5-fda0db38e29b@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-04-15 20:54:03 -05:00