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arm64: dts: qcom: sc8280xp: Add PCIe bridge node

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On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.

While at it, let's remove the bridge properties from board dts as they are
now redundant.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-9-1eb790c53e43@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Manivannan Sadhasivam
2024-03-21 16:46:29 +05:30
committed by Bjorn Andersson
parent 3c3abb944d
commit e6bbf39055
2 changed files with 56 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
View File

@@ -733,22 +733,14 @@ &pcie4 {
pinctrl-0 = <&pcie4_default>;
status = "okay";
};
pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
&pcie4_port0 {
wifi@0 {
compatible = "pci17cb,1103";
reg = <0x10000 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
wifi@0 {
compatible = "pci17cb,1103";
reg = <0x10000 0x0 0x0 0x0 0x0>;
qcom,ath11k-calibration-variant = "LE_X13S";
};
qcom,ath11k-calibration-variant = "LE_X13S";
};
};

50
arch/arm64/boot/dts/qcom/sc8280xp.dtsi
View File

@@ -1803,6 +1803,16 @@ pcie4: pcie@1c00000 {
phy-names = "pciephy";
status = "disabled";
pcie4_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
};
pcie4_phy: phy@1c06000 {
@@ -1904,6 +1914,16 @@ pcie3b: pcie@1c08000 {
phy-names = "pciephy";
status = "disabled";
pcie3b_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
};
pcie3b_phy: phy@1c0e000 {
@@ -2005,6 +2025,16 @@ pcie3a: pcie@1c10000 {
phy-names = "pciephy";
status = "disabled";
pcie3a_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
};
pcie3a_phy: phy@1c14000 {
@@ -2109,6 +2139,16 @@ pcie2b: pcie@1c18000 {
phy-names = "pciephy";
status = "disabled";
pcie2b_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
};
pcie2b_phy: phy@1c1e000 {
@@ -2210,6 +2250,16 @@ pcie2a: pcie@1c20000 {
phy-names = "pciephy";
status = "disabled";
pcie2a_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
};
pcie2a_phy: phy@1c24000 {