mirrors/linux
2
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git synced 2026-05-13 18:49:22 -04:00
Code Issues Packages Projects Releases Wiki Activity
1,169,482 Commits 1 Branch 930 Tags
e8df226339fa032c49f8db4281903930d018a22c
Commit Graph

1169482 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Douglas Anderson
e8df226339 arm64: dts: qcom: sc7180: Remove superfluous "input-enable"s from trogdor 
As talked about in the patch ("dt-bindings: pinctrl: qcom: tlmm should
use output-disable, not input-enable"), using "input-enable" in
pinctrl states for Qualcomm TLMM pinctrl devices was either
superfluous or there to disable a pin's output.

Looking at trogdor:
* ap_ec_int_l, fp_to_ap_irq_l, h1_ap_int_odl, p_sensor_int_l:
  Superfluous. The pins will be configured as inputs automatically by
  the Linux GPIO subsystem (presumably the reference for other OSes
  using these device trees).
* bios_flash_wp_l: Superfluous. This pin is exposed to userspace
  through the kernel's GPIO API and will be configured automatically.

That means that in none of the cases for trogdor did we need to change
"input-enable" to "output-disable" and we can just remove these
superfluous properties.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230323102605.9.I94dbc53176e8adb0d7673b7feb2368e85418f938@changeid
 2023-04-07 10:54:09 -07:00
Douglas Anderson
ced32c299e arm64: dts: qcom: sc7180: Annotate l13a on trogdor to always-on 
The l13a rail on trogdor devices has always been intended to be
always-on on both S0 and S3. Different trogdor variants use l13a in
slightly different ways, but the overall theme is that it's a 1.8V
rail that the board uses for things that it wants powered in on S0 and
S3. On many boards this includes the boot SPI (AKA qspi).

For all intents and purposes this patch is actually a no-op since
something else in the system seems to already be keeping the rail on
all the time (confirmed via multimeter). That "something else" was
postulated to be the modem but the rail is on / stays on even without
the modem/wifi coming up so it's likely the boot config. In any case,
making the fact that this is always-on explicit seems like a good
idea.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230323102605.4.I9f47a8a53eacff6229711a827993792ceeb36971@changeid
 2023-04-07 10:54:08 -07:00
Douglas Anderson
37f7349b56 arm64: dts: sdm845: Rename qspi data12 as data23 
There are 4 qspi data pins: data0, data1, data2, and data3. Currently
we have a shared pin state for data0 and data1 (2 lane config) and a
pin state for data2 and data3 (you'd enable both this and the 2 lane
state for 4 lanes). The second state is obviously misnamed. Fix it.

Fixes: e1ce853932 ("arm64: dts: qcom: sdm845: Add qspi (quad SPI) node")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230323102605.3.I88528d037b7fda4e53a40f661be5ac61628691cd@changeid
 2023-04-07 10:54:08 -07:00
Douglas Anderson
14acf21c0d arm64: dts: sc7280: Rename qspi data12 as data23 
There are 4 qspi data pins: data0, data1, data2, and data3. Currently
we have a shared pin state for data0 and data1 (2 lane config) and a
pin state for data2 and data3 (you'd enable both this and the 2 lane
state for 4 lanes). The second state is obviously misnamed. Fix it.

Fixes: 7720ea001b ("arm64: dts: qcom: sc7280: Add QSPI node")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230323102605.2.I4043491bb24b1e92267c5033d76cdb0fe60934da@changeid
 2023-04-07 10:54:08 -07:00
Douglas Anderson
d84f8f2687 arm64: dts: sc7180: Rename qspi data12 as data23 
There are 4 qspi data pins: data0, data1, data2, and data3. Currently
we have a shared pin state for data0 and data1 (2 lane config) and a
pin state for data2 and data3 (you'd enable both this and the 2 lane
state for 4 lanes). The second state is obviously misnamed. Fix it.

Fixes: ba3fc64963 ("arm64: dts: sc7180: Add qupv3_0 and qupv3_1")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230323102605.1.Ifc1b5be04653f4ab119698a5944bfecded2080d6@changeid
 2023-04-07 10:54:08 -07:00
Bjorn Andersson
876a6d25ac Merge branch 'ib-qcom-quad-spi' of https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl into arm64-for-6.4 
Merge the support for output-enable/disable in the pinctrl-msm driver,
to ensure that bisection across the following SC7180/SC7280 DeviceTree
changes result in something electrically sound.

Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-04-07 10:53:45 -07:00
Devi Priya
97cb36ff52 arm64: dts: qcom: Add ipq9574 SoC and AL02 board support 
Add initial device tree support for Qualcomm IPQ9574 SoC and AL02 board

Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
Co-developed-by: Poovendhan Selvaraj <quic_poovendh@quicinc.com>
Signed-off-by: Poovendhan Selvaraj <quic_poovendh@quicinc.com>
Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230316072940.29137-6-quic_devipriy@quicinc.com
 2023-04-07 10:36:21 -07:00
Bjorn Andersson
5602dfc37a Merge branch '20230316072940.29137-2-quic_devipriy@quicinc.com' into HEAD 
Merge the IPQ9574 Global Clock Controller Devicetree binding, to make
available the clock definitions used in the Devicetree source.
 2023-04-07 10:35:12 -07:00
Devi Priya
b065b23d3c dt-bindings: clock: Add ipq9574 clock and reset definitions 
Add clock and reset ID definitions for ipq9574

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230316072940.29137-2-quic_devipriy@quicinc.com
 2023-04-07 10:27:16 -07:00
Petr Vorel
c85c8a9927 arm64: dts: qcom: msm8994-angler: removed clash with smem_region 
This fixes memory overlap error:
[    0.000000] reserved@6300000 (0x0000000006300000--0x0000000007000000) overlaps with smem_region@6a00000 (0x0000000006a00000--0x0000000006c00000)

smem_region is the same as in downstream (qcom,smem) [1], therefore
split reserved memory into two sections on either side of smem_region.

Not adding labels as it's not expected to be used.

[1] https://android.googlesource.com/kernel/msm/+/refs/heads/android-msm-angler-3.10-marshmallow-mr1/arch/arm/boot/dts/qcom/msm8994.dtsi#948

Fixes: 380cd3a34b ("arm64: dts: msm8994-angler: fix the memory map")

Signed-off-by: Petr Vorel <pvorel@suse.cz>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230131200414.24373-3-pvorel@suse.cz
 2023-04-07 10:21:27 -07:00
Petr Vorel
fe88480a6b arm64: dts: qcom: msm8994-angler: Fix cont_splash_mem mapping 
Angler's cont_splash_mem mapping is shorter in downstream [1],
therefore 380cd3a34b was wrong. Obviously also 0e5ded926f was wrong
(workaround which fixed booting at the time).

This fixes error:
[    0.000000] memory@3401000 (0x0000000003401000--0x0000000005601000) overlaps with tzapp@4800000 (0x0000000004800000--0x0000000006100000)

[1] https://android.googlesource.com/kernel/msm/+/refs/heads/android-msm-angler-3.10-marshmallow-mr1/arch/arm64/boot/dts/huawei/huawei_msm8994_angler_row_vn1/huawei-fingerprint.dtsi#16

Fixes: 380cd3a34b ("arm64: dts: msm8994-angler: fix the memory map")
Fixes: 0e5ded926f ("arm64: dts: qcom: msm8994-angler: Disable cont_splash_mem")

Signed-off-by: Petr Vorel <pvorel@suse.cz>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230131200414.24373-2-pvorel@suse.cz
 2023-04-07 10:21:23 -07:00
Douglas Anderson
cb5d1dd3a7 MAINTAINERS: qcom: Add reviewer for Qualcomm Chromebooks 
Developers on the ChromeOS team generally want to be notified to
review changes that affect Chromebook device tree files. While we
could individually add developers, the set of developers and the time
each one has available to review patches will change over time. Let's
try adding a group list as a reviewer and see if that's an effective
way to manage things.

A few notes:
* Though this email address is actually backed by a mailing list, I'm
  adding it as "R"eviewer and not "L"ist since it's not a publicly
  readable mailing list and it's intended just to have a few people on
  it. This also hopefully conveys a little more responisbility for the
  people that are part of this group.
* I've added all sc7180 and sc7280 files here. At the moment I'm not
  aware of any non-Chromebooks being supported that use these
  chips. If later something shows up then we can try to narrow down.
* I've added "sdm845-cheza" to this list but not the rest of
  "sdm845". Cheza never shipped but some developers still find the old
  developer boards useful and thus it continues to get minimal
  maintenance. Most sdm845 device tree work, however, seems to be for
  non-Chromebooks.

Cc: Stephen Boyd <swboyd@chromium.org>
Cc: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230330141051.1.If8eb4f30cb53a00a5bef1b7d3cc645c3536615ec@changeid
 2023-04-07 09:42:23 -07:00
Kathiravan T
d0367098dc arm64: dts: qcom: ipq5332: add few device nodes 
Add the nodes for QUP peripheral, PRNG and WDOG. While at it, enable the
I2C device for MI01.2 board.

Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230320104530.30411-3-quic_kathirav@quicinc.com
 2023-04-06 11:38:57 -07:00
Krzysztof Kozlowski
a10e2244f4 arm64: dts: qcom: sm8550: add ADSP audio codec macros 
Add the Low Power Audio SubSystem (LPASS) / ADSP audio codec macros on
Qualcomm SM8550.  The nodes are very similar to SM8450, except missing
NPL clock which is not exposed on SM8550 and should not be touched.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230310134925.514125-1-krzysztof.kozlowski@linaro.org
 2023-04-06 11:36:34 -07:00
Manivannan Sadhasivam
6340b391e1 arm64: dts: qcom: Remove "iommus" property from PCIe nodes 
Currently, most of the Qualcomm SoCs specify both "iommus" and "iommu-map"
properties for the PCIe nodes. First one passes the SMR mask to the iommu
driver and the latter specifies the SID for each PCIe device.

But with "iommus" property, the PCIe controller will be added to the
iommu group along with the devices. This makes no sense because the
controller will not initiate any DMA transaction on its own. And moreover,
it is not strictly required to pass the SMR mask to the iommu driver. If
the "iommus" property is not present, then the default mask of "0" would be
used which should work for all PCIe devices.

On the other side, if the SMR mask specified doesn't match the one expected
by the hypervisor, then all the PCIe transactions will end up triggering
"Unidentified Stream Fault" by the SMMU.

So to get rid of these hassles and also prohibit PCIe controllers from
adding to the iommu group, let's remove the "iommus" property from PCIe
nodes.

Reported-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/linux-arm-msm/20230227195535.GA749409-robh@kernel.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230308075648.134119-1-manivannan.sadhasivam@linaro.org
 2023-04-06 11:32:54 -07:00
Krzysztof Kozlowski
d6573b4c20 arm64: dts: qcom: sm8450: simplify interrupts-extended 
The parent controller for both interrupts is GIC, so no need for
interrupts-extended.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230405060906.143058-5-krzysztof.kozlowski@linaro.org
 2023-04-06 11:14:39 -07:00
Krzysztof Kozlowski
563065020d arm64: dts: qcom: sm8250: simplify interrupts-extended 
The parent controller for the interrupt is GIC, so no need for
interrupts-extended.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230405060906.143058-4-krzysztof.kozlowski@linaro.org
 2023-04-06 11:14:39 -07:00
Krzysztof Kozlowski
465b99f3b4 arm64: dts: qcom: sc8280xp: simplify interrupts-extended 
The parent controller for both interrupts is GIC, so no need for
interrupts-extended.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230405060906.143058-3-krzysztof.kozlowski@linaro.org
 2023-04-06 11:14:39 -07:00
Krzysztof Kozlowski
add214009d arm64: dts: qcom: sm8450: label the Soundwire nodes 
Use labels, instead of comments, for Soundwire controllers.  Naming them
is useful, because they are specialized and have also naming in
datasheet/programming guide.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230405060906.143058-2-krzysztof.kozlowski@linaro.org
 2023-04-06 11:14:39 -07:00
Krzysztof Kozlowski
f77256439c arm64: dts: qcom: sc8280xp: label the Soundwire nodes 
Use labels, instead of comments, for Soundwire controllers.  Naming them
is useful, because they are specialized and have also naming in
datasheet/programming guide.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230405060906.143058-1-krzysztof.kozlowski@linaro.org
 2023-04-06 11:14:39 -07:00
Konrad Dybcio
1e6e0c1c97 arm64: dts: qcom: sm6115: Use the correct DSI compatible 
Use the non-deprecated, SoC-specific DSI compatible.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230307-topic-dsi_qcm-v6-9-70e13b1214fa@linaro.org
 2023-04-05 09:00:50 -07:00
Steev Klimaszewski
105560b4fc arm64: dts: qcom: sc8280xp-x13s: Add bluetooth 
The Lenovo Thinkpad X13s has a WCN6855 Bluetooth controller on uart2,
add this.

Signed-off-by: Steev Klimaszewski <steev@kali.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Tested-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230326233812.28058-5-steev@kali.org
 2023-04-04 20:51:38 -07:00
Bjorn Andersson
9db28f2975 arm64: dts: qcom: sc8280xp: Define uart2 
Add the definition for uart2 for sc8280xp devices.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Steev Klimaszewski <steev@kali.org>
Reviewed-by: Brian Masney <bmasney@redhat.com>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230326233812.28058-4-steev@kali.org
 2023-04-04 20:51:37 -07:00
Manivannan Sadhasivam
de7d3d2f9d arm64: dts: qcom: sc8280xp: Add "mhi" region to the PCIe nodes 
The "mhi" region contains the debug registers that could be used to monitor
the PCIe link transitions.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230316081117.14288-19-manivannan.sadhasivam@linaro.org
 2023-04-04 20:46:35 -07:00
Manivannan Sadhasivam
8921034240 arm64: dts: qcom: sm8250: Add "mhi" region to the PCIe nodes 
The "mhi" region contains the debug registers that could be used to monitor
the PCIe link transitions.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230316081117.14288-18-manivannan.sadhasivam@linaro.org
 2023-04-04 20:46:20 -07:00
Manivannan Sadhasivam
b8e0ed06d1 arm64: dts: qcom: sdm845: Add "mhi" region to the PCIe nodes 
The "mhi" region contains the debug registers that could be used to monitor
the PCIe link transitions.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230316081117.14288-17-manivannan.sadhasivam@linaro.org
 2023-04-04 20:46:20 -07:00
Bartosz Golaszewski
81767c1591 arm64: dts: qcom: sa8775p-ride: set gpio-line-names for PMIC GPIOs 
Set line names for GPIO lines exposed by PMICs on sa8775p-ride.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230327125316.210812-16-brgl@bgdev.pl
 2023-04-04 20:42:29 -07:00
Bartosz Golaszewski
e5a893a7ce arm64: dts: qcom: sa8775p: add PMIC GPIO controller nodes 
Add GPIO controller nodes to PMICs that have the GPIO hooked up on
sa8775p-ride.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230327125316.210812-15-brgl@bgdev.pl
 2023-04-04 20:42:29 -07:00
Bartosz Golaszewski
fa40ca07e9 arm64: dts: qcom: sa8775p: pmic: add thermal zones 
Add the thermal zones and associated alarm nodes for the PMICs that have
them hooked up on sa8775p-ride.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230327125316.210812-12-brgl@bgdev.pl
 2023-04-04 20:42:29 -07:00
Bartosz Golaszewski
cecff1f542 arm64: dts: qcom: sa8775p: pmic: add support for the pmm8654 RESIN input 
Add the RESIN input for sa8775p platforms' PMIC.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230327125316.210812-11-brgl@bgdev.pl
 2023-04-04 20:42:29 -07:00
Bartosz Golaszewski
b3a755ba16 arm64: dts: qcom: sa8775p: pmic: add the power key 
Add the power key node under the PON node for PMIC #0 on sa8775p.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230327125316.210812-10-brgl@bgdev.pl
 2023-04-04 20:42:29 -07:00
Bartosz Golaszewski
d2d9a59274 arm64: dts: qcom: sa8775p: add the Power On device node 
Add the PON node to PMIC #0 for sa8775p platforms.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230327125316.210812-9-brgl@bgdev.pl
 2023-04-04 20:42:29 -07:00
Bartosz Golaszewski
634a3de323 arm64: dts: qcom: sa8775p: add support for the on-board PMICs 
Add a new .dtsi file for sa8775p PMICs and add the four PMICs interfaced
to the SoC via SPMI. Enable the PMICs for sa8775p-ride.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230327125316.210812-8-brgl@bgdev.pl
 2023-04-04 20:42:29 -07:00
Bartosz Golaszewski
fdd55b3bab arm64: dts: qcom: sa8775p: add the spmi node 
Add the SPMI PMIC Arbiter node for SA8775p platforms.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230327125316.210812-6-brgl@bgdev.pl
 2023-04-04 20:42:29 -07:00
Bartosz Golaszewski
8696cd072e arm64: dts: qcom: sa8775p: add the pdc node 
Add the Power Domain Controller node for SA8775p.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230327125316.210812-5-brgl@bgdev.pl
 2023-04-04 20:42:29 -07:00
Bartosz Golaszewski
f95f988cf7 arm64: dts: qcom: sa8775p: sort soc nodes by reg property 
Sort all children of the soc node by the first address in their reg
property. This was mostly already the case but there were some nodes
that didn't follow it so fix it now for consistency.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230327125316.210812-3-brgl@bgdev.pl
 2023-04-04 20:42:29 -07:00
Bartosz Golaszewski
3fd7e2eec8 arm64: dts: qcom: sa8775p: pad reg properties to 8 digits 
The file has inconsistent padding of the address part of soc node
children's reg properties. Fix it.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230327125316.210812-2-brgl@bgdev.pl
 2023-04-04 20:42:29 -07:00
Krzysztof Kozlowski
894e258b6a arm64: dts: qcom: sc8280xp: correct Soundwire wakeup interrupt name 
The bindings expect second Soundwire interrupt to be "wakeup" (Linux
driver takes by index):

  sc8280xp-crd.dtb: soundwire-controller@3330000: interrupt-names:1: 'wakeup' was expected

Fixes: c18773d162 ("arm64: dts: qcom: sc8280xp: add SoundWire and LPASS")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230403132328.61414-1-krzysztof.kozlowski@linaro.org
 2023-04-04 20:35:26 -07:00
Konrad Dybcio
da51e2ceed arm64: dts: qcom: sdm845-tama: Enable GPI_DMA0/1 
Enable both GPI DMAs.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230313-topic-tama_disp-v3-6-2b1567c039d7@linaro.org
 2023-04-04 20:29:45 -07:00
Konrad Dybcio
ff9108ea69 arm64: dts: qcom: sdm845-tama: Enable GPU 
Enable the A630 GPU and its GMU.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230313-topic-tama_disp-v3-5-2b1567c039d7@linaro.org
 2023-04-04 20:29:45 -07:00
Konrad Dybcio
39e0f8076f arm64: dts: qcom: sdm845-tama: Enable remoteprocs 
Enable ADSP, CDSP and Venus.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230313-topic-tama_disp-v3-4-2b1567c039d7@linaro.org
 2023-04-04 20:29:45 -07:00
Konrad Dybcio
1d99fee382 arm64: dts: qcom: sdm845-tama: Add regulator-system-load to l14a/l28a 
Add the properties to ensure the ever so delicate touchscreen setup
matches downstream.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230313-topic-tama_disp-v3-3-2b1567c039d7@linaro.org
 2023-04-04 20:29:45 -07:00
Konrad Dybcio
3ab8216de2 arm64: dts: qcom: sdm845-tama: Add Synaptics Touchscreen 
Add required pins and RMI4 node to the common DT and remove it
from Akatsuki, as it uses a different touch.

Since the panels are super high tech proprietary incell, they
need to be handled with very precise timings. As such the panel
driver sets up the power rails and GPIOs and the touchscreen
driver *has to* probe afterwards.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230313-topic-tama_disp-v3-2-2b1567c039d7@linaro.org
 2023-04-04 20:29:44 -07:00
Konrad Dybcio
5dcc6587fd arm64: dts: qcom: sdm845-tama: Add display nodes 
Add required nodes to support display on XZ2/XZ2c. XZ3 has a
different power rail setup and needs to be handled separately.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230313-topic-tama_disp-v3-1-2b1567c039d7@linaro.org
 2023-04-04 20:29:44 -07:00
Adam Skladowski
26aae2310f arm64: dts: msm8953: Pad regs to 8 digits 
Follow other dtses and pad regs to 8 digits.

Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230325112852.18841-4-a39.skl@gmail.com
 2023-04-04 20:23:15 -07:00
Adam Skladowski
c0494df2cd arm64: dts: msm8953: Drop unsupported dwc3 flag 
Property phy_mode according to binding checker does not exist,
drop it.

Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230325112852.18841-3-a39.skl@gmail.com
 2023-04-04 20:23:15 -07:00
Adam Skladowski
635abd8775 arm64: dts: msm8953: Provide dsi_phy clocks to gcc 
Provide clocks from dsi_phy to gcc, this will make
sure we don't fallback to global name lookup.

Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230325112852.18841-2-a39.skl@gmail.com
 2023-04-04 20:23:15 -07:00
Adam Skladowski
3042fb4b61 arm64: dts: msm8953: Replace xo_board with rpmcc sourced xo 
Assign RPM_SMD_XO_CLK_SRC from rpmcc in place
of fixed-clock where possible.

Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230325112852.18841-1-a39.skl@gmail.com
 2023-04-04 20:23:15 -07:00
Neil Armstrong
35fa9a7fc5 arm64: dts: qcom: sm8450: remove invalid properties in cluster-sleep nodes 
Fixes the following DT bindings check error:
domain-idle-states: cluster-sleep-0: 'idle-state-name', 'local-timer-stop' do not match any of the regexes:
'pinctrl-[0-9]+'
domain-idle-states: cluster-sleep-1: 'idle-state-name', 'local-timer-stop' do not match any of the regexes:
'pinctrl-[0-9]+'

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230323-topic-sm8450-upstream-dt-bindings-fixes-v2-2-0ca1bea1a843@linaro.org
 2023-04-04 20:22:08 -07:00
Krzysztof Kozlowski
ea1811e261 arm64: dts: qcom: sc8280xp: drop incorrect domain idle states properties 
Domain idle states do not use 'idle-state-name':

  sc8280xp-crd.dtb: domain-idle-states: cluster-sleep-0: 'idle-state-name' does not match any of the regexes: 'pinctrl-[0-9]+'

Reported-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/all/20230323-topic-sm8450-upstream-dt-bindings-fixes-v1-4-3ead1e418fe4@linaro.org/
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230324073813.22158-6-krzysztof.kozlowski@linaro.org
 2023-04-04 20:20:24 -07:00