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arm64: dts: qcom: sm8550: add ADSP audio codec macros

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Add the Low Power Audio SubSystem (LPASS) / ADSP audio codec macros on
Qualcomm SM8550.  The nodes are very similar to SM8450, except missing
NPL clock which is not exposed on SM8550 and should not be touched.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230310134925.514125-1-krzysztof.kozlowski@linaro.org
This commit is contained in:
Krzysztof Kozlowski
2023-03-10 14:49:25 +01:00
committed by Bjorn Andersson
parent 6340b391e1
commit a10e2244f4
1 changed files with 195 additions and 0 deletions
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195
arch/arm64/boot/dts/qcom/sm8550.dtsi
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@@ -1984,6 +1984,97 @@ IPCC_MPROC_SIGNAL_GLINK_QMP
};
};
lpass_wsa2macro: codec@6aa0000 {
compatible = "qcom,sm8550-lpass-wsa-macro";
reg = <0 0x06aa0000 0 0x1000>;
clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&lpass_vamacro>;
clock-names = "mclk", "macro", "dcodec", "fsgen";
assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
assigned-clock-rates = <19200000>;
#clock-cells = <0>;
clock-output-names = "wsa2-mclk";
pinctrl-names = "default";
pinctrl-0 = <&wsa2_swr_active>;
#sound-dai-cells = <1>;
};
lpass_rxmacro: codec@6ac0000 {
compatible = "qcom,sm8550-lpass-rx-macro";
reg = <0 0x06ac0000 0 0x1000>;
clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&lpass_vamacro>;
clock-names = "mclk", "macro", "dcodec", "fsgen";
assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
assigned-clock-rates = <19200000>;
#clock-cells = <0>;
clock-output-names = "mclk";
pinctrl-names = "default";
pinctrl-0 = <&rx_swr_active>;
#sound-dai-cells = <1>;
};
lpass_txmacro: codec@6ae0000 {
compatible = "qcom,sm8550-lpass-tx-macro";
reg = <0 0x06ae0000 0 0x1000>;
clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&lpass_vamacro>;
clock-names = "mclk", "macro", "dcodec", "fsgen";
assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
assigned-clock-rates = <19200000>;
#clock-cells = <0>;
clock-output-names = "mclk";
pinctrl-names = "default";
pinctrl-0 = <&tx_swr_active>;
#sound-dai-cells = <1>;
};
lpass_wsamacro: codec@6b00000 {
compatible = "qcom,sm8550-lpass-wsa-macro";
reg = <0 0x06b00000 0 0x1000>;
clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&lpass_vamacro>;
clock-names = "mclk", "macro", "dcodec", "fsgen";
assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
assigned-clock-rates = <19200000>;
#clock-cells = <0>;
clock-output-names = "mclk";
pinctrl-names = "default";
pinctrl-0 = <&wsa_swr_active>;
#sound-dai-cells = <1>;
};
lpass_vamacro: codec@6d44000 {
compatible = "qcom,sm8550-lpass-va-macro";
reg = <0 0x06d44000 0 0x1000>;
clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
clock-names = "mclk", "macro", "dcodec";
assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
assigned-clock-rates = <19200000>;
#clock-cells = <0>;
clock-output-names = "fsgen";
#sound-dai-cells = <1>;
};
lpass_tlmm: pinctrl@6e80000 {
compatible = "qcom,sm8550-lpass-lpi-pinctrl";
reg = <0 0x06e80000 0 0x20000>,
@@ -1995,6 +2086,110 @@ lpass_tlmm: pinctrl@6e80000 {
clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
clock-names = "core", "audio";
tx_swr_active: tx-swr-active-state {
clk-pins {
pins = "gpio0";
function = "swr_tx_clk";
drive-strength = <2>;
slew-rate = <1>;
bias-disable;
};
data-pins {
pins = "gpio1", "gpio2", "gpio14";
function = "swr_tx_data";
drive-strength = <2>;
slew-rate = <1>;
bias-bus-hold;
};
};
rx_swr_active: rx-swr-active-state {
clk-pins {
pins = "gpio3";
function = "swr_rx_clk";
drive-strength = <2>;
slew-rate = <1>;
bias-disable;
};
data-pins {
pins = "gpio4", "gpio5";
function = "swr_rx_data";
drive-strength = <2>;
slew-rate = <1>;
bias-bus-hold;
};
};
dmic01_default: dmic01-default-state {
clk-pins {
pins = "gpio6";
function = "dmic1_clk";
drive-strength = <8>;
output-high;
};
data-pins {
pins = "gpio7";
function = "dmic1_data";
drive-strength = <8>;
input-enable;
};
};
dmic02_default: dmic02-default-state {
clk-pins {
pins = "gpio8";
function = "dmic2_clk";
drive-strength = <8>;
output-high;
};
data-pins {
pins = "gpio9";
function = "dmic2_data";
drive-strength = <8>;
input-enable;
};
};
wsa_swr_active: wsa-swr-active-state {
clk-pins {
pins = "gpio10";
function = "wsa_swr_clk";
drive-strength = <2>;
slew-rate = <1>;
bias-disable;
};
data-pins {
pins = "gpio11";
function = "wsa_swr_data";
drive-strength = <2>;
slew-rate = <1>;
bias-bus-hold;
};
};
wsa2_swr_active: wsa2-swr-active-state {
clk-pins {
pins = "gpio15";
function = "wsa2_swr_clk";
drive-strength = <2>;
slew-rate = <1>;
bias-disable;
};
data-pins {
pins = "gpio16";
function = "wsa2_swr_data";
drive-strength = <2>;
slew-rate = <1>;
bias-bus-hold;
};
};
};
lpass_lpiaon_noc: interconnect@7400000 {