Ville Syrjälä
e225161e2a
drm/i915/bios: Define VBT blocks 19,30,32 (Display Configuration Removal Table) contents
...
Define the contenst is VBT blocks 19,30,32 (Display Configuration
Removal Table) contents. There are three variants of this block:
pre-IVB, IVB, HSW+, with each having slightly different entries.
Curiously many HSW/BDW machines seem to have both the IVB and HSW+
variants in their VBTs simultanously. No idea why.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-21-ville.syrjala@linux.intel.com
Acked-by: Jani Nikula <jani.nikula@intel.com >
2024-05-08 16:41:55 +03:00
Ville Syrjälä
e547b97e9d
drm/i915/bios: Define VBT blocks 16,29,31 (Toggle List) contents
...
Define the contenst is VBT blocks 16,19,31 (Toggle List).
There are three variants of this block: pre-IVB, IVB, HSW+,
with each having slightly different entries.
Curiously many HSW/BDW machines seem to have both the IVB and
HSW+ variants in their VBTs simultanously. No idea why.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-20-ville.syrjala@linux.intel.com
Acked-by: Jani Nikula <jani.nikula@intel.com >
2024-05-08 16:41:39 +03:00
Ville Syrjälä
95f4cbc8fb
drm/i915/bios: Define VBT block 18 (Driver Rotation) contents
...
Define the contents of block 18 (Driver Rotation).
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-19-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com >
2024-05-08 16:41:19 +03:00
Ville Syrjälä
8e94221f78
drm/i915/bios: Define VBT block 17 (SV Test Functions) contents
...
Define the contents of VBT block 17 (SV Test Functions).
Nothing real here for us, but might as well define it for
completeness.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-18-ville.syrjala@linux.intel.com
Acked-by: Jani Nikula <jani.nikula@intel.com >
2024-05-08 16:41:01 +03:00
Ville Syrjälä
55c6b98676
drm/i915/bios: Define ALM only VBT block 9 contents
...
For some reason ALM VBT has two dot clock override tables.
One as the normal block 15 and a second one as block 9.
The table in block 9 has no row_size/num_rows information.
On my Fujitsu Lifebook S6010 only the block 9 table has actual
data in it. Block 15 is present but all zeroes.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-17-ville.syrjala@linux.intel.com
Acked-by: Jani Nikula <jani.nikula@intel.com >
2024-05-08 16:40:35 +03:00
Ville Syrjälä
f7d5b5ff08
drm/i915/bios: Define VBT block 15 (Dot Clock Override Table) contents
...
Define the contents of VBT block 15 (Dot Clock Override Table)
The contents were reverse engineered by intuition. The gen2 stuff
seems solid as I can verify that against real world VBT data. The
gen3 stuff less so as all the gen3+ VBTs I have just filla the
entire block with zeroes.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-16-ville.syrjala@linux.intel.com
Acked-by: Jani Nikula <jani.nikula@intel.com >
2024-05-08 16:39:58 +03:00
Ville Syrjälä
2f1aa210fe
drm/i915/bios: Define VBT block 12 (Driver Persistent Algorithm) contents
...
Define the contents of VBT block 12 (Driver Persistent Algorithm).
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-15-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com >
2024-05-08 16:38:54 +03:00
Ville Syrjälä
98fe6aed8a
drm/i915/bios: Define VBT block 10 (Mode Removal Table) contents
...
Define the contents of VBT block 10 (Mode Removal Table).
There seem to be two variants:
- 8 byte entries for desktop systems
- 10 byte entries for mobile systems, with the extra
panel_flags being a bitmask of LFPs
It seems starting from HSW only the mobile variant is
used anymore.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-14-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com >
2024-05-08 16:38:45 +03:00
Ville Syrjälä
2318da471a
drm/i915/bios: Define VBT blocks 6,7,8 (register tables) contents
...
Define the contents for VBT blocks:
- Block 6 (Extended MMIO Register Table)
- Block 7 (IO Software Flag Table)
- Block 8 (MMIO SWF Register Table)
All of these use the same basic layout, with two known variants:
- data_access_size==0xce -> offset,value tuples are u8,u8
- data_access_size==0x02 -> offset,value tuples are u32,u32
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-13-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com >
2024-05-08 16:38:33 +03:00
Ville Syrjälä
2e8b807317
drm/i915/bios: Define VBT block 5 (Generic Mode Table)
...
Define the contents of VBT block 5 (Generic Mode Table).
Details were mostly gleaned from some VBIOS sources.
There are apparently two variants of the block: ALM only
vs. MGM, defined here as bdb_generic_mode_table_alm
and bdb_generic_mode_table_mgm. And those are the only two
platforms where I've seen this block.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-12-ville.syrjala@linux.intel.com
Acked-by: Jani Nikula <jani.nikula@intel.com >
2024-05-08 16:37:54 +03:00
Ville Syrjälä
22794e6cee
drm/i915/bios: Define VBT block 4 (Mode Support List) contents
...
Define the contents of VBT block 4 (Mode Support List).
Slightly crazy layout with a variable length list at the start,
followed by the length of said list.
No real idea what these "Intel mode numbers" really are. What
I see in real world VBTs seems to be always the same list of
26 numbers, ranging between 0x30 and 0x84.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-11-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com >
2024-05-08 16:37:19 +03:00
Ville Syrjälä
c58f254be3
drm/i915/bios: Define VBT block 3 (Display Toggle Option) contents
...
Define the contents of VBT block 3 (Display Toggle Option).
On modern VBTs this is just a single byte, but on ALM there is
also some extra to do with toggle lists or something.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-10-ville.syrjala@linux.intel.com
Acked-by: Jani Nikula <jani.nikula@intel.com >
2024-05-08 16:35:36 +03:00
Ville Syrjälä
a17b317c11
drm/i915/bios: Add version notes for some blocks
...
Document which VBT blocks were defined in which BDB version,
for the cases where the spec actually states this accurately.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-9-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com >
2024-05-08 16:35:22 +03:00
Ville Syrjälä
e760a7dade
drm/i915/bios: Flag "VBIOS only" VBT data blocks
...
Several data blocks are mean to be consumbed by VBIOS only.
Flag them as such.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-8-ville.syrjala@linux.intel.com
Acked-by: Jani Nikula <jani.nikula@intel.com >
2024-05-08 16:35:07 +03:00
Ville Syrjälä
10632fcbf0
drm/i915/bios: Define "TV" child device handle
...
Child device 0x2 used to be "TV" until redefined to mean
EFP5 in version 215. Add a define for the old meaning as well.
Technically it was probably deprecated a lot before version
215 since native TV encoders were last seen on CTG, and SDVO
was fully gone by HSW. So something like "???-164" might also
be a reasonable way to document this, but no real harm in
saying "???-214" since nothing else presumably occupied that
bit in the meantime.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-7-ville.syrjala@linux.intel.com
Acked-by: Jani Nikula <jani.nikula@intel.com >
2024-05-08 16:34:55 +03:00
Ville Syrjälä
8e26690851
drm/i915/bios: Rename SDVO DTD blocks a bit
...
The SDVO LVDS blocks are specifically about LVDS, so stick
to naming that reflects that. This also makes the names match
the spec.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-6-ville.syrjala@linux.intel.com
Acked-by: Jani Nikula <jani.nikula@intel.com >
2024-05-08 16:34:31 +03:00
Ville Syrjälä
6ac67ccf4c
drm/i915/bios: Get rid of "LVDS" from all LFP data stuff
...
The LFP data applies to all kinds of display interfaces, so
stop calling things by the "LVDS" name.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-5-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com >
2024-05-08 16:34:03 +03:00
Ville Syrjälä
7234f948b5
drm/i915/bios: Indicate which VBT structures are based on EDID
...
VBT reuses a bunch of EDID data structures. Flag those as such
for clarity.
I chose "bdb_edid_" as the namespace for these.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-4-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com >
2024-05-08 16:24:51 +03:00
Ville Syrjälä
d9981f36e4
drm/i915/bios: Remove version number comment from DEVICE_HANDLE_EFP4
...
DEVICE_HANDLE_EFP4 has actually been in use since the very beginning,
or at least something has been occupying that bit because old
VBTs actually use it, and it definitely looks to be about external
displays given how its used. So let's ignore what the current spec
claims and remove the misleading version number comment.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-3-ville.syrjala@linux.intel.com
Acked-by: Jani Nikula <jani.nikula@intel.com >
2024-05-08 16:24:22 +03:00
Ville Syrjälä
7043141fbb
drm/i915/bios: Define eDP DSC disable bit
...
There's a new "DSC disable" bit in the eDP VBT block. Define it.
TODO: actually use it?
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-2-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com >
2024-05-08 16:24:03 +03:00
Jani Nikula
c06387ab44
drm/i915: pass dev_priv explicitly to PORT_DFT2_G4X
...
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PORT_DFT2_G4X register macro.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/0db8ee7b66b9660fc9fd80598257c6d36f0f506b.1714990089.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com >
2024-05-08 12:08:46 +03:00
Jani Nikula
19e74ba7f8
drm/i915: pass dev_priv explicitly to PIPE_CRC_*
...
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_CRC_RES_* register macros.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/849315d4417a2ce60e867648d9a040c5e96bc22d.1714990089.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com >
2024-05-08 12:08:46 +03:00
Jani Nikula
6dd2bd94d2
drm/i915: pass dev_priv explicitly to PIPE_CRC_CTL
...
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_CRC_CTL register macro.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/2ac4438aa885be9d0fcf5c697beee99a4cd2c23f.1714990089.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com >
2024-05-08 12:08:45 +03:00
Karthikeyan Ramasubramanian
c286f6a973
drm/i915/bios: Fix parsing backlight BDB data
...
Starting BDB version 239, hdr_dpcd_refresh_timeout is introduced to
backlight BDB data. Commit 700034566d ("drm/i915/bios: Define more BDB
contents") updated the backlight BDB data accordingly. This broke the
parsing of backlight BDB data in VBT for versions 236 - 238 (both
inclusive) and hence the backlight controls are not responding on units
with the concerned BDB version.
backlight_control information has been present in backlight BDB data
from at least BDB version 191 onwards, if not before. Hence this patch
extracts the backlight_control information for BDB version 191 or newer.
Tested on Chromebooks using Jasperlake SoC (reports bdb->version = 236).
Tested on Chromebooks using Raptorlake SoC (reports bdb->version = 251).
v2: removed checking the block size of the backlight BDB data
[vsyrjala: this is completely safe thanks to commit e163cfb4c9
("drm/i915/bios: Make copies of VBT data blocks")]
Fixes: 700034566d ("drm/i915/bios: Define more BDB contents")
Cc: stable@vger.kernel.org
Cc: Jani Nikula <jani.nikula@intel.com >
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com >
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@chromium.org >
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20240221180622.v2.1.I0690aa3e96a83a43b3fc33f50395d334b2981826@changeid
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
2024-05-07 13:58:49 +03:00
Jani Nikula
accd3e041e
drm/i915: pass dev_priv explicitly to PORT_ALPM_LFPS_CTL
...
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PORT_ALPM_LFPS_CTL register macro.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/f8a3bbade94258852b8129c5f5918fb06ceab54b.1714471597.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com >
2024-05-06 11:24:53 +03:00
Jani Nikula
7f4eae0a94
drm/i915: pass dev_priv explicitly to PORT_ALPM_CTL
...
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PORT_ALPM_CTL register macro.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/86e8f5649c822ff6fa0502ad88964bfcb269c6c5.1714471597.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com >
2024-05-06 11:24:53 +03:00
Jani Nikula
94e760584a
FIXME drm/i915: pass dev_priv explicitly to ALPM_CTL2
...
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the ALPM_CTL2 register macro.
Reviewed-by: Jouni Högander <jouni.hogander@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/09acf2751cfd2f524e6ba97c3ac285495eae5c86.1714471597.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com >
2024-05-06 11:24:46 +03:00
Jani Nikula
13b77ac5dc
drm/i915: pass dev_priv explicitly to ALPM_CTL
...
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the ALPM_CTL register macro.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/96da9be36dc93fa9a7c329f25ff963e4998998c1.1714471597.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com >
2024-05-06 10:25:41 +03:00
Jani Nikula
db92d423dc
drm/i915: pass dev_priv explicitly to PIPE_SRCSZ_ERLY_TPT
...
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_SRCSZ_ERLY_TPT register macro.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/b37217f55702fc10190c2c5aded7d845a36766f6.1714471597.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com >
2024-05-06 10:25:39 +03:00
Jani Nikula
dd17285e94
drm/i915: pass dev_priv explicitly to PSR2_MAN_TRK_CTL
...
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PSR2_MAN_TRK_CTL register macro.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/72934c8ac3a923ca0c12fc6cdeec1e0b87ecc4a4.1714471597.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com >
2024-05-06 10:25:38 +03:00
Jani Nikula
a0d1cfa86c
drm/i915: pass dev_priv explicitly to PSR2_SU_STATUS
...
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PSR2_SU_STATUS register macro.
v2: Expand from _PSR2_SU_STATUS to PSR2_SU_STATUS (Rodrigo)
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20240502103925.1829104-1-jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com >
2024-05-06 10:25:35 +03:00
Jani Nikula
d82d1a6be6
drm/i915: pass dev_priv explicitly to EDP_PSR2_STATUS
...
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the EDP_PSR2_STATUS register macro.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/5d86a48f51ae6fa4c5a3abf098440a94d07de870.1714471597.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com >
2024-05-06 10:25:34 +03:00
Jani Nikula
ccd5bc537b
drm/i915: pass dev_priv explicitly to PSR_EVENT
...
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PSR_EVENT register macro.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/9bc5819afa46416eb8f12ac050ed4d3bcde34b63.1714471597.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com >
2024-05-06 10:25:32 +03:00
Jani Nikula
9b0dddd50e
drm/i915: pass dev_priv explicitly to EDP_PSR2_CTL
...
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the EDP_PSR2_CTL register macro.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/e7df99445716ce404bbfe733dd962288a529cf0d.1714471597.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com >
2024-05-06 10:25:31 +03:00
Jani Nikula
83f4ccb3f3
drm/i915: pass dev_priv explicitly to EDP_PSR_DEBUG
...
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the EDP_PSR_DEBUG register macro.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/187dd49632d46e67705bd258ed7f9eabdeb108b2.1714471597.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com >
2024-05-06 10:25:30 +03:00
Jani Nikula
5aa0cb6b1e
drm/i915: pass dev_priv explicitly to EDP_PSR_PERF_CNT
...
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the EDP_PSR_PERF_CNT register macro.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/21805960967ab88c1418037b98fe3e051eb00608.1714471597.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com >
2024-05-06 10:25:29 +03:00
Jani Nikula
218f3d28d1
drm/i915: pass dev_priv explicitly to EDP_PSR_STATUS
...
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the EDP_PSR_STATUS register macro.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/4aaa0187b16d2b96b5b4b1d775d7349c9fc28c7c.1714471597.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com >
2024-05-06 10:25:27 +03:00
Jani Nikula
4c3cbdb12d
drm/i915: pass dev_priv explicitly to EDP_PSR_AUX_DATA
...
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the EDP_PSR_AUX_DATA register macro.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/4e3dc15b170c2b64168e46ebf1802d63df34b4a2.1714471597.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com >
2024-05-06 10:25:26 +03:00
Jani Nikula
cf3d5f89a6
drm/i915: pass dev_priv explicitly to EDP_PSR_AUX_CTL
...
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the EDP_PSR_AUX_CTL register macro.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/66ec1f81be49c87cd9613ba052ce6fd50362d0e0.1714471597.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com >
2024-05-06 10:25:25 +03:00
Jani Nikula
7a7a4c4eeb
drm/i915: pass dev_priv explicitly to TRANS_PSR_IIR
...
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the TRANS_PSR_IIR register macro.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/3a03109d11e7f55a456c3e5ef28d3ffa69582d3d.1714471597.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com >
2024-05-06 10:25:23 +03:00
Jani Nikula
f9f8f84717
drm/i915: pass dev_priv explicitly to TRANS_PSR_IMR
...
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the TRANS_PSR_IMR register macro.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/09e9c11ffb669dac901c2416462a8f3dabc86020.1714471597.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com >
2024-05-06 10:25:22 +03:00
Jani Nikula
676a6a1c99
drm/i915: pass dev_priv explicitly to EDP_PSR_CTL
...
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the EDP_PSR_CTL register macro.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/198858bc3925c02c0975670e3ebb5ce2084ac658.1714471597.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com >
2024-05-06 10:25:20 +03:00
Jani Nikula
1d231cd898
drm/i915: pass dev_priv explicitly to TRANS_EXITLINE
...
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the TRANS_EXITLINE register macro.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/eb1e5fe155daf2d271af76e683a1f3f33e34403a.1714471597.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com >
2024-05-06 10:25:19 +03:00
Balasubramani Vivekanandan
ca5d5ecbb9
drm/xe/bmg: Enable the display support
...
Enable the display support for Battlemage
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com >
Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com >
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com >
Acked-by: Lucas De Marchi <lucas.demarchi@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-20-radhakrishna.sripada@intel.com
2024-05-03 13:15:54 -07:00
Matthew Auld
4071ada7ae
drm/i915/display: perform transient flush
...
Perform manual transient cache flush prior to flip and at the end of
frontbuffer_flush. This is needed to ensure display engine doesn't see
garbage if the surface is L3:XD dirty.
Testcase: igt@xe-pat@display-vs-wb-transient
Signed-off-by: Matthew Auld <matthew.auld@intel.com >
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com >
Acked-by: Nirmoy Das <nirmoy.das@intel.com >
Reviewed-by: Matt Roper <matthew.d.roper@intel.com >
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-19-radhakrishna.sripada@intel.com
2024-05-03 13:15:54 -07:00
Nirmoy Das
c01c6066e6
drm/xe/device: implement transient flush
...
Display surfaces can be tagged as transient by mapping it using one of
the various L3:XD PAT index modes on Xe2. The expectation is that KMD
needs to request transient data flush at the start of flip sequence to
ensure all transient data in L3 cache is flushed to memory. Add a
routine for this which we can then call from the display code.
v2: rebase(RK)
Signed-off-by: Nirmoy Das <nirmoy.das@intel.com >
Co-developed-by: Matthew Auld <matthew.auld@intel.com >
Signed-off-by: Matthew Auld <matthew.auld@intel.com >
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com >
Reviewed-by: Matt Roper <matthew.d.roper@intel.com >
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com >
Acked-by: Lucas De Marchi <lucas.demarchi@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-18-radhakrishna.sripada@intel.com
2024-05-03 13:15:54 -07:00
Matthew Auld
1372708168
drm/xe/gt_print: add xe_gt_err_once()
...
Needed in an upcoming patch, where we want GT level print, but only
which to trigger once to avoid flooding dmesg.
Signed-off-by: Matthew Auld <matthew.auld@intel.com >
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com >
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com >
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com >
Acked-by: Lucas De Marchi <lucas.demarchi@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-17-radhakrishna.sripada@intel.com
2024-05-03 13:15:54 -07:00
Balasubramani Vivekanandan
98b1c87a5e
drm/i915/xe2hpd: Set maximum DP rate to UHBR13.5
...
Max supported speed by xe2hpd is UHBR13.5. Limit the max DP source rate
to it.
Bspec: 67066
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com >
Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com >
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-16-radhakrishna.sripada@intel.com
2024-05-03 13:15:54 -07:00
Ankit Nautiyal
c528aaa36d
Revert "drm/i915/dgfx: DGFX uses direct VBT pin mapping"
...
This reverts commit 562f33836f .
For BMG it seems that the VBT to DDI mapping does not follow DG1, and
DG2, but follows ADLP mapping given in Bspec:20124.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com >
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com >
Reviewed-by: Matt Roper <matthew.d.roper@intel.com >
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-15-radhakrishna.sripada@intel.com
2024-05-03 13:15:54 -07:00
Matt Roper
a8c026d0e6
drm/i915/bmg: BMG should re-use MTL's south display logic
...
Battlemage's south display is the same as Meteor Lake's, including the
need to invert the HPD pins, which Lunar Lake does not need.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com >
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com >
Reviewed-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com >
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-14-radhakrishna.sripada@intel.com
2024-05-03 13:15:54 -07:00