Commit Graph

948946 Commits

Author SHA1 Message Date
Stephan Gerhold
c2f0cbb57d arm64: dts: qcom: pm8916: Remove invalid reg size from wcd_codec
Tha parent node of "wcd_codec" specifies #address-cells = <1>
and #size-cells = <0>, which means that each resource should be
described by one cell for the address and size omitted.

However, wcd_codec currently lists 0x200 as second cell (probably
the size of the resource). When parsing this would be treated like
another memory resource - which is entirely wrong.

To quote the device tree specification [1]:
  "If the parent node specifies a value of 0 for #size-cells,
   the length field in the value of reg shall be omitted."

[1]: https://www.devicetree.org/specifications/

Fixes: 5582fcb382 ("arm64: dts: apq8016-sbc: add analog audio support with multicodec")
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200915071221.72895-4-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-15 15:33:17 +00:00
Stephan Gerhold
e6859ae860 arm64: dts: qcom: msm8916: Remove one more thermal trip point unit name
Commit fe2aff0c57 ("arm64: dts: qcom: msm8916: remove unit name for thermal trip points")
removed the unit names for most of the thermal trip points defined
in msm8916.dtsi, but missed to update the one for cpu0_1-thermal.

So why wasn't this spotted by "make dtbs_check"? Apparently, the name
of the thermal zone is already invalid: thermal-zones.yaml specifies
a regex of ^[a-zA-Z][a-zA-Z0-9\\-]{1,12}-thermal$, so it is not allowed
to contain underscores. Therefore the thermal zone was never verified
using the DTB schema.

After replacing the underscore in the thermal zone name, the warning
shows up:

    apq8016-sbc.dt.yaml: thermal-zones: cpu0-1-thermal:trips: 'trip-point@0'
    does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+'

Fix up the thermal zone names and remove the unit name for the trip point.

Cc: Amit Kucheria <amit.kucheria@linaro.org>
Fixes: fe2aff0c57 ("arm64: dts: qcom: msm8916: remove unit name for thermal trip points")
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200915071221.72895-3-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-15 15:33:00 +00:00
Stephan Gerhold
b2106c670e arm64: dts: qcom: msm8916: Configure DSI port with labels
&dsi0 -> ports -> port@1 -> endpoint already has the "dsi0_out" label,
so we can use it for configuring instead of replicating the entire
node hierarchy. Looks like I missed that when converting the boards.

Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200915071221.72895-2-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-15 15:31:08 +00:00
Dmitry Baryshkov
01e869cc0d arm64: dts: sm8250: Add OPP table for all qup devices
qup has a requirement to vote on the performance state of the CX domain
in sm8250 devices. Add OPP tables for these and also add power-domains
property for all qup instances for uart and spi.
i2c does not support scaling and uses a fixed clock.

Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20200915120203.290295-1-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-15 15:08:02 +00:00
Robert Foss
43bb807400 arm64: dts: qcom: msm8996: Add VFE1_GDSC power domain to camss node
As the MSM8996 has two VFE IP-blocks, and each has a power domain,
both of them have to be enabled. Previously only the power domain
of VFE0 was enabled, but not the domain for VFE1.

This patch adds the VFE1_GDSC power domain to the camss device tree
node of the MSM8996 soc.

Signed-off-by: Robert Foss <robert.foss@linaro.org>
Link: https://lore.kernel.org/r/20200915142316.147208-1-robert.foss@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-15 15:05:55 +00:00
Stephan Gerhold
bfd5d21abc arm64: dts: qcom: msm8916: Move common USB properties to msm8916.dtsi
Right now we define "hnp-disable", "srp-disable", "adp-disable"
separately for every MSM8916 board that has USB working.

They are needed for USB to work properly if CONFIG_USB_OTG_FSM
is enabled. This is because the chipidea OTG FSM code waits for
interrupts regarding the VBUS state (AVVIS). Those never happen
on MSM8916 because VBUS is always connected to the PMIC instead
of the USB controller.

There was a patch [1] to work around this but ultimately it was
decided that it's easier to disable the OTG FSM altogether using
these properties. This works fine for most use cases, because the
OTG FSM isn't needed for simple dual role host/gadget operation.

Given that these properties are needed for every MSM8916 device,
move them to msm8916.dtsi so we can avoid some more duplication.

[1]: https://lore.kernel.org/lkml/20160707222114.1673-10-stephen.boyd@linaro.org/

Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200720085406.6716-11-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-15 04:51:36 +00:00
Stephan Gerhold
b0d330c29e arm64: dts: qcom: msm8916: Set default pinctrl for blsp1_uart1/2
Right now some device nodes set default pinctrl within msm8916.dtsi
(e.g. I2C, SPI), but for others it needs to be explicitly set in the
board-specific device tree (e.g. UART).

While it is theoretically possible that some super special board
needs different pinctrl for these, in practice pretty much every
board ends up using the common pinctrl definitions.

Make this consistent by also defining the common pinctrl properties
for blsp1_uart1 and blsp1_uart2 so we don't need to copy this for every
board. If there is really such a super special board it could just
override these properties with custom pinctrl or make minor modifications
to the common pinctrl configurations provided by msm8916-pins.dtsi.

Also move #address-cells/#size-cells for &dsi0 to msm8916.dtsi
since this is specific to the DSI node, not the board.

Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200720085406.6716-10-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-15 04:51:29 +00:00
Stephan Gerhold
cc99dd61b7 arm64: dts: qcom: msm8916: Move more supplies to msm8916-pm8916.dtsi
So far we had some supplies defined for all boards in msm8916.dtsi,
while others were duplicated into every board-specific device tree.

Now that we have msm8916-pm8916.dtsi as a common include for all
standard MSM8916 devices using PM8916, move the remaining common
supplies to msm8916-pm8916.dtsi to reduce duplication a bit.

Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200720085406.6716-9-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-15 04:51:13 +00:00
Stephan Gerhold
bfe9d75425 arm64: dts: qcom: msm8916: Move PM8916-specific parts to msm8916-pm8916.dtsi
Device trees for newer SoCs avoid defining the regulator nodes directly
in the SoC device tree (here: msm8916.dtsi). The reason for this is that
theoretically it is possible to combine the SoC with a different PMIC,
or to use all the regulators in a board-specific way.

Therefore let's remove those from the SoC include (msm8916.dtsi).

In practice, pretty much all MSM8916 boards were combined with PM8916,
and use the regulators in similar ways. After looking at many different
MSM8916 boards (mostly smartphones and tablets), I haven't seen a single
device that isn't using the same regulators for components integrated
into the SoC.

If all boards end up defining all regulators and supplies in the same way
then it is useful to have an include for that, so we can avoid duplicating
it everywhere. If there is really a super special board that does it
differently it could just override some properties or avoid using the
include altogether.

This patch moves the regulator and common supply definitions to
a new include called "msm8916-pm8916.dtsi".

This is also going to be useful when introducing CPR (Core Power
Reduction) later because we can configure the CPU regulator
(pm8916_spmi_s2) for all devices in this common include.

Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200720085406.6716-8-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-15 04:50:49 +00:00
Stephan Gerhold
4eb7b63d4f arm64: dts: qcom: pm8916: Add resin node
Right now we define the entire pm8916 resin node separately in
the board-specific device tree part, including the interrupt that
belongs to PM8916.

As a feature of the PMIC it should be declared in pm8916.dtsi,
disabled by default. Like all other optional components it can then
by enabled and configured in the board-specific device tree part.

Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200720085406.6716-7-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-15 04:49:38 +00:00
Stephan Gerhold
e2f6482aff arm64: dts: qcom: msm8916: Use labels in board device trees
Device trees for newer SoCs avoid replicating the entire device
hierarchy in the board-specific device tree part. Instead,
they set additional properties only by referencing labels,
sorted alphabetically.

Now that we have labels for all relevant nodes, convert the MSM8916
board device trees to use the same style and remove the "soc" node
entirely.

Note: There is a large block of coresight nodes in apq8016-sbc.dtsi,
which are enabled by setting status = "okay". I kept them grouped
together (not alphabetically sorted with everything else),
since that would be just unnecessarily verbose and hard to see.

This commit only moves all existing properties to nodes that reference
the respective label. The resulting binary DTBs are exactly the same.

Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200720085406.6716-6-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-15 04:49:20 +00:00
Stephan Gerhold
2329e5fb54 arm64: dts: qcom: msm8916: Add more labels
Add a few more labels to device nodes declared in msm8916.dtsi
so that we can set all needed properties using labels in the
board-specific device tree part.

Also rename the "otg" label to "usb" to allow grouping it with
the USB PHY (usb_hs_phy) node when ordering referenced labels
alphabetically.

Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200720085406.6716-5-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-15 04:48:29 +00:00
Stephan Gerhold
48faf07941 arm64: dts: qcom: apq8016-sbc: Define leds outside of soc node
The leds node does not use any memory regions of the SoC and should
therefore be declared outside the "soc" node.

Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200720085406.6716-4-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-15 04:48:19 +00:00
Stephan Gerhold
974dc2f395 arm64: dts: qcom: msm8916: Declare sound node in msm8916.dtsi
The "sound" node in apq8016-sbc.dtsi references memory regions
provided by the SoC and should be therefore declared in msm8916.dtsi.

Additionally, the machine driver used for the "qcom,apq8016-sbc-sndcard"
compatible also works on other MSM8916 devices (provided that audio
routing is set up properly). It is not really specific to apq8016-sbc.

Simplify setting up sound on other boards by moving the common part
to msm8916.dtsi. This also allows referencing the node by the label,
so that we can eventually drop the "soc" node entirely from the
board-specific device tree part and use labels exclusively.

Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200720085406.6716-3-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-15 04:48:08 +00:00
Stephan Gerhold
4134b8ef08 arm64: dts: qcom: apq8016-sbc: Remove properties that are already default
apq8016-sbc.dtsi overrides several properties that are already the
default in msm8916.dtsi. Remove these to simplify the device tree
a bit.

Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200720085406.6716-2-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-15 04:48:00 +00:00
Dmitry Baryshkov
08a9ae2d25 arch64: dts: qcom: sm8250: add uart nodes
Currently sm8250.dtsi only defines default debug uart. Port rest uart
nodes from the downstream dtsi file.

Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20200909103238.149761-1-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-15 04:45:39 +00:00
satya priya
4e0a3e04e4 arm64: dts: qcom: sc7180-trogdor: Add wakeup support for BT UART
Add the necessary pinctrl, interrupt property and a suitable sleep config
to support Bluetooth wakeup feature.

GPIO mode is configured in sleep state to drive the RTS/RFR line low.
If QUP function is selected in sleep state, UART RTS/RFR is pulled high
during suspend and BT SoC not able to send wakeup bytes.

Tested-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: satya priya <skakit@codeaurora.org>
Link: https://lore.kernel.org/r/1600091917-7464-4-git-send-email-skakit@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-15 00:15:26 +00:00
satya priya
9a36c6fd09 arm64: dts: qcom: sc7180: Add wakeup support for BT UART on sc7180-idp
Add the necessary pinctrl, interrupt property and a suitable sleep config
to support Bluetooth wakeup feature.

GPIO mode is configured in sleep state to drive the RTS/RFR line low.
If QUP function is selected in sleep state, UART RTS/RFR is pulled high
during suspend and BT SoC not able to send wakeup bytes.

Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: satya priya <skakit@codeaurora.org>
Link: https://lore.kernel.org/r/1600091917-7464-3-git-send-email-skakit@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-15 00:15:15 +00:00
satya priya
ff11a79878 arm64: dts: qcom: sc7180: Improve the uart3 pin config for sc7180-idp
Remove output-high from CTS and TX as this is not really required. During
bringup to fix transfer failures this was added to match with console uart
settings. Probably some boot loader config was missing then. As it is
working fine now, remove it.

Signed-off-by: satya priya <skakit@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/1600091917-7464-2-git-send-email-skakit@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-15 00:15:07 +00:00
Stephen Boyd
7c6d828e90 arm64: dts: qcom: trogdor: Add labels for type-c ports
Some trogdor board variants only have one USB port, so add a couple
labels to these ports so we can modify them later.

Reviewed-by: Douglas Anderson <dianders@chromium.org>
Cc: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20200914232218.658664-1-swboyd@chromium.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-14 23:48:52 +00:00
Łukasz Patron
b1c0da47cc arm64: dts: qcom: pm660: Fix missing pound sign in interrupt-cells
Also add a space after '=' while at it.

Tested-by: Konrad Dybcio <konradybcio@gmail.com>
Signed-off-by: Łukasz Patron <priv.luk@gmail.com>
Link: https://lore.kernel.org/r/20200725082417.8507-1-priv.luk@gmail.com
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-14 00:04:52 +00:00
Stephen Boyd
51e9874d38 arm64: dts: qcom: sc7180: Drop flags on mdss irqs
The number of interrupt cells for the mdss interrupt controller is 1,
meaning there should only be one cell for the interrupt number, not two
where the second cell is the irq flags. Drop the second cell to match
the binding.

Cc: Kalyan Thota <kalyan_t@codeaurora.org>
Cc: Harigovindan P <harigovi@codeaurora.org
Fixes: a3db7ad1af ("arm64: dts: sc7180: add display dt nodes")
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20200811192503.1811462-1-swboyd@chromium.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-14 00:04:52 +00:00
Gokul Sriram Palanisamy
5f854f096f dt-bindings: qcom: Add ipq8074 bindings
Document the new device-tree bindings for boards
HK10-C1 and HK10-C2 based on ipq8074 SoC.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Link: https://lore.kernel.org/r/1596706332-12957-2-git-send-email-gokulsri@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-13 23:59:24 +00:00
Kathiravan T
292b18741e arm64: dts: ipq8074: Use the A53 PMU compatible
IPQ8074 has A53 cores, so lets use the corresponding PMU compatible.

Signed-off-by: Kathiravan T <kathirav@codeaurora.org>
Link: https://lore.kernel.org/r/1597642116-15902-1-git-send-email-kathirav@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-13 23:56:30 +00:00
Kathiravan T
36f91e6316 arm64: dts: ipq6018: enable DVFS support
Add A53 PLL, APCS clock, RPM Glink, RPM message RAM, cpu-opp-table,
SMPA2 regulator to enable the cpu frequency on IPQ6018.

Co-developed-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
Signed-off-by: Kathiravan T <kathirav@codeaurora.org>
Link: https://lore.kernel.org/r/1597648720-13649-3-git-send-email-kathirav@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-13 23:56:11 +00:00
Kathiravan T
5a8c1669f3 dt-bindings: mailbox: add compatible for the IPQ6018 SoC
Add the mailbox compatible for the IPQ6018 SoC.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Kathiravan T <kathirav@codeaurora.org>
Link: https://lore.kernel.org/r/1597648720-13649-2-git-send-email-kathirav@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-13 23:56:11 +00:00
Adrian Schmutzler
7a1dcc9d02 arm64: dts: qcom: replace status value "ok" by "okay"
While the DT parser recognizes "ok" as a valid value for the
"status" property, it is actually mentioned nowhere. Use the
proper value "okay" instead, as done in the majority of files
already.

Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
Link: https://lore.kernel.org/r/20200830200845.1771-1-freifunk@adrianschmutzler.de
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-13 23:55:34 +00:00
Kathiravan T
949766e0a3 arm64: dts: ipq8074: enable watchdog support
Enable watchdog support for the IPQ8074 SoCs.

Signed-off-by: Kathiravan T <kathirav@codeaurora.org>
Link: https://lore.kernel.org/r/1598862428-13996-1-git-send-email-kathirav@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-13 23:55:29 +00:00
Jonathan Marek
9ff8b0591f arm64: dts: qcom: sm8250: use the right clock-freqency for sleep-clk
Downstream has this clock as 32000 rate, but testing shows it is close to
32768.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Link: https://lore.kernel.org/r/20200903215923.14314-1-jonathan@marek.ca
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-13 23:54:50 +00:00
Douglas Anderson
bcd86d327a arm64: dts: qcom: Add sc7180-lazor sku2
Add a new SKU variant.  This is a pick from the downstream tree that
is the current source of truth for this platform.

Link: https://crrev.com/c/2386997
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20200908133037.1.Ia98a6b938453254e360c4a9fa253d2d6807dff3f@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-13 23:53:43 +00:00
Venkata Lakshmi Narayana Gubba
135db20655 arm64: dts: qcom: sc7180: Remove clock for bluetooth on SC7180 IDP board
Removed voting for RPMH_RF_CLK2 which is not required as it is
getting managed by BT SoC through SW_CTRL line.

Signed-off-by: Venkata Lakshmi Narayana Gubba <gubbaven@codeaurora.org>
Link: https://lore.kernel.org/r/1599734980-22580-1-git-send-email-gubbaven@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-13 23:51:25 +00:00
Dmitry Baryshkov
c0011172f9 arm64: dts: qcom: sm8250-mtp: add i2c device tree nodes
Add device tree nodes describing used i2c busses according to the dts
found in msm-4.19 tree.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20200913224738.30046-1-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-13 23:49:57 +00:00
Dmitry Baryshkov
76bd127e6c arm64: dts: qcom: sm8250: add bi_tcxo_ao to gcc clocks
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20200913225135.30366-1-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-13 23:49:30 +00:00
Amit Pundir
77809cf74a arm64: dts: qcom: Add support for Xiaomi Poco F1 (Beryllium)
Add initial dts support for Xiaomi Poco F1 (Beryllium).

This initial support is based on upstream Dragonboard 845c
(sdm845) device. With this dts, Beryllium boots AOSP up to
ADB shell over USB-C.

Supported functionality includes UFS, USB-C (peripheral),
microSD card and Vol+/Vol-/power keys. Bluetooth should work
too but couldn't be verified from adb command line, it is
verified when enabled from UI with few WIP display patches.

Just like initial db845c support, initializing the SMMU is
clearing the mapping used for the splash screen framebuffer,
which causes the device to hang during boot and recovery
needs a hard power reset. This can be worked around using:

    fastboot oem select-display-panel none

To switch ON the display back run:

    fastboot oem select-display-panel

But this only works on Beryllium devices running bootloader
version BOOT.XF.2.0-00369-SDM845LZB-1 that shipped with
Android-9 based release. Newer bootloader version do not
support switching OFF the display panel at all.

Reviewed-by: Konrad Dybcio <konradybcio@gmail.com>
Signed-off-by: Amit Pundir <amit.pundir@linaro.org>
Link: https://lore.kernel.org/r/1599840940-18144-1-git-send-email-amit.pundir@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-12 23:26:18 +00:00
Krishna Manikandan
0a4fd091cf arm64: dts: sc7180: add bus clock to mdp node for sc7180 target
Move the bus clock to mdp device node,in order
to facilitate bus band width scaling on sc7180
target.

The parent device MDSS will not vote for bus bw,
instead the vote will be triggered by mdp device
node. Since a minimum vote is required to turn
on bus clock, move the clock node to mdp device
from where the votes are requested.

This patch has dependency on the below series
https://patchwork.kernel.org/patch/11468783/

Reviewed-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
Link: https://lore.kernel.org/r/1594899334-19772-2-git-send-email-kalyan_t@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-10 22:30:51 +00:00
Pradeep P V K
fa8da06628 arm64: dts: qcom: sc7180: Add bandwidth votes for eMMC and SDcard
Add the bandwidth domain supporting performance state and
the corresponding OPP tables for the sdhc device on sc7180.

Signed-off-by: Pradeep P V K <ppvk@codeaurora.org>
Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org>
Link: https://lore.kernel.org/r/1597646464-1863-1-git-send-email-sbhanu@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-10 22:28:06 +00:00
Matthias Kaehlcke
5a4d9f3e18 arm64: dts: qcom: sc7180: Add 'sustainable_power' for CPU thermal zones
The 'sustainable_power' attribute provides an estimate of the sustained
power that can be dissipated at the desired control temperature. One
could argue that this value is not necessarily the same for all devices
with the same SoC, which may have different form factors or thermal
designs. However there are reasons to specify a (default) value at SoC
level for SC7180: most importantly, if no value is specified at all the
power_allocator thermal governor (aka 'IPA') estimates a value, using the
minimum power of all cooling devices of the zone, which can result in
overly aggressive thermal throttling. For most devices an approximate
conservative value should be more useful than the minimum guesstimate
of power_allocator. Devices that need a different value can overwrite
it in their <device>.dts. Also the thermal zones for SC7180 have a high
level of granularity (essentially one for each function block), which
makes it more likely that the default value just works for many devices.

The values correspond to 1901 MHz for the big cores, and 1804 MHz for
the small cores. The values were determined by limiting the CPU
frequencies to different max values and launching a bunch of processes
that cause high CPU load ('while true; do true; done &' is simple and
does a good job). A frequency is deemed sustainable if the CPU
temperatures don't rise (consistently) above the second trip point
('control temperature', 95 degC in this case). Once the highest
sustainable frequency is found, the sustainable power can be calculated
by multiplying the energy consumption per core at this frequency (which
can be found in /sys/kernel/debug/energy_model/) with the number of
cores that are specified as cooling devices.

The sustainable frequencies were determined at room temperature
on a device without heat sink or other passive cooling elements.

Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Link: https://lore.kernel.org/r/20200813113030.1.I89c33c4119eaffb986b1e8c1bc6f0e30267089cd@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-10 22:10:03 +00:00
Rajendra Nayak
ef8e58f837 arm64: dts: qcom: sc7180: Add OPP tables and power-domains for venus
Add the OPP tables in order to be able to vote on the performance state
of a power-domain

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Link: https://lore.kernel.org/r/1598970026-7199-6-git-send-email-rnayak@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-10 22:03:16 +00:00
Rajendra Nayak
137154871c arm64: dts: qcom: sdm845: Add OPP tables and power-domains for venus
Add the OPP tables in order to be able to vote on the performance state of
a power-domain.

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Link: https://lore.kernel.org/r/1598970026-7199-5-git-send-email-rnayak@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-10 22:03:11 +00:00
Krishna Manikandan
81921a3714 arm64: dts: qcom: sc7180: add interconnect bindings for display
This change adds the interconnect bindings to the
MDSS node. This will establish Display to DDR path
for bus bandwidth voting.

Reviewed-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
Link: https://lore.kernel.org/r/1594899334-19772-1-git-send-email-kalyan_t@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-10 21:42:59 +00:00
Taniya Das
f05f2c2118 arm64: dts: qcom: sc7180: Add LPASS clock controller nodes
Update the clock controller nodes for Low power audio subsystem
functionality.

Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/1596305615-5894-2-git-send-email-tdas@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-10 16:58:02 +00:00
Manivannan Sadhasivam
70ff10d5e3 arm64: dts: qcom: qrb5165-rb5: Add gpio-line-names for PM8150(B&L)
Add gpio-line-names for the GPIO pins exposed by PM8150, PM8150B and
PM8150L PMIC nodes.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20200904063637.28632-7-manivannan.sadhasivam@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-10 16:40:43 +00:00
Manivannan Sadhasivam
6c6a6d81f5 arm64: dts: qcom: qrb5165-rb5: Add gpio-line-names for TLMM block
Add gpio-line-names property for QRB5165 RB5 board for naming all GPIOs
exposed by TLMM block.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20200904063637.28632-6-manivannan.sadhasivam@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-10 16:40:41 +00:00
Manivannan Sadhasivam
b5cbd84e49 arm64: dts: qcom: qrb5165-rb5: Add onboard LED support
Only User4, WLAN and BT LEDs are added for now. These GPIOs are coming
from PM8150. Rest are coming from LPG block which is not supported yet!

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20200904063637.28632-5-manivannan.sadhasivam@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-10 16:40:30 +00:00
Manivannan Sadhasivam
b1d2674e61 arm64: dts: qcom: Add basic devicetree support for QRB5165 RB5
Add basic devicetree support for Qualcomm Technologies, Inc. Robotics
RB5 platform. This board is one of the 96Boards CE platform targeted for
Robotics usecases from Qualcomm.

This basic devicetree support includes regulators, onboard debug UART,
I2C, SPI, and UFS support.

Co-developed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20200904063637.28632-4-manivannan.sadhasivam@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-10 16:40:14 +00:00
Manivannan Sadhasivam
bb1dfb4da1 arm64: dts: qcom: sm8250: Rename UART2 node to UART12
The UART12 node has been mistakenly mentioned as UART2. Let's fix that
for both SM8250 SoC and MTP board and also add pinctrl definition for
it.

Fixes: 60378f1a17 ("arm64: dts: qcom: sm8250: Add sm8250 dts file")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20200904063637.28632-3-manivannan.sadhasivam@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-10 16:40:08 +00:00
Manivannan Sadhasivam
152a1b4c3e dt-bindings: arm: qcom: Document SM8250 SoC and boards
Document the SM8250 SoC binding and also the boards using it.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20200904063637.28632-2-manivannan.sadhasivam@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-10 16:38:35 +00:00
Rob Clark
7ec3e67307 arm64: dts: qcom: sc7180-trogdor: add initial trogdor and lazor dt
This is essentialy a squash of a bunch of history of trogdor and lazor
dt updates from the chromium kernel tree.

I don't claim any credit other than wanting to more easily boot upstream
kernel on these devices.

I've tried to add cc tags for all the original authors.

Cc: Stephen Boyd <swboyd@chromium.org>
Cc: Douglas Anderson <dianders@chromium.org>
Cc: Matthias Kaehlcke <mka@chromium.org>
Cc: Atul Dhudase <adhudase@codeaurora.org>
Cc: Venkata Lakshmi Narayana Gubba <gubbaven@codeaurora.org>
Cc: Evan Green <evgreen@chromium.org>
Cc: Cheng-Yi Chiang <cychiang@chromium.org>
Cc: Ajit Pandey <ajitp@codeaurora.org>
Cc: Alexandru Stan <amstan@chromium.org>
Cc: Sujit Kautkar <sujitka@chromium.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20200828204052.2085508-1-robdclark@gmail.com
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-08-31 18:10:03 +00:00
Sai Prakash Ranjan
efe788361f arm64: dts: qcom: sc7180: Fix the LLCC base register size
There is one LLCC logical bank(LLCC0) on SC7180 SoC and the
size of the LLCC0 base is 0x50000(320KB) not 2MB, so correct
the size and fix copy paste mistake carried over from SDM845.

Reviewed-by: Douglas Anderson <dianders@chromium.org>
Fixes: 7cee5c7428 ("arm64: dts: qcom: sc7180: Fix node order")
Fixes: c831fa2999 ("arm64: dts: qcom: sc7180: Add Last level cache controller node")
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Link: https://lore.kernel.org/r/20200818145514.16262-1-saiprakash.ranjan@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-08-30 17:24:30 +00:00
Jonathan Marek
0e6aa9db44 arm64: dts: qcom: use sm8250 gpucc dt-bindings
Constants were used to allow merging separately from the dt-bindings,
switch to symbolic names now that dt-bindings have landed.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Link: https://lore.kernel.org/r/20200818160445.14008-3-jonathan@marek.ca
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-08-30 17:24:12 +00:00