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arm64: dts: qcom: sm8250: Rename UART2 node to UART12

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The UART12 node has been mistakenly mentioned as UART2. Let's fix that
for both SM8250 SoC and MTP board and also add pinctrl definition for
it.

Fixes: 60378f1a17 ("arm64: dts: qcom: sm8250: Add sm8250 dts file")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20200904063637.28632-3-manivannan.sadhasivam@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This commit is contained in:
Manivannan Sadhasivam
2020-09-04 12:06:33 +05:30
committed by Bjorn Andersson
parent 152a1b4c3e
commit bb1dfb4da1
2 changed files with 12 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm64/boot/dts/qcom/sm8250-mtp.dts
View File

@@ -17,7 +17,7 @@ / {
compatible = "qcom,sm8250-mtp";
aliases {
serial0 = &uart2;
serial0 = &uart12;
};
chosen {
@@ -371,7 +371,7 @@ &tlmm {
gpio-reserved-ranges = <28 4>, <40 4>;
};
&uart2 {
&uart12 {
status = "okay";
};

11
arch/arm64/boot/dts/qcom/sm8250.dtsi
View File

@@ -936,11 +936,13 @@ spi12: spi@a90000 {
status = "disabled";
};
uart2: serial@a90000 {
uart12: serial@a90000 {
compatible = "qcom,geni-debug-uart";
reg = <0x0 0x00a90000 0x0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_uart12_default>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -1881,6 +1883,13 @@ config {
bias-disable;
};
};
qup_uart12_default: qup-uart12-default {
mux {
pins = "gpio34", "gpio35";
function = "qup12";
};
};
};
adsp: remoteproc@17300000 {