mirrors/linux
2
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git synced 2026-05-22 08:35:10 -04:00
Code Issues Packages Projects Releases Wiki Activity
1,398,251 Commits 1 Branch 931 Tags
bf94dea7fd4e6708d1a784be23db65eff84d82f1
Commit Graph

125 Commits

Author SHA1 Message Date
Linus Torvalds
0f048c878e Merge tag 'soc-dt-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc 
Pull SoC dt updates from Arnd Bergmann:
 "There are five sets of new SoCs that get added in existing families,
  all of them being either upgrades or cut-down versions of the older
  chips:

   - Apple M2 Pro, M2 Max and M2 Ultra, used in the 2022/2023 generation
     of high-end workstations and laptops from Apple. Linux has been
     working on these for a while but stil requires patches.

   - Axis Artpec8 is an Armv8 chip based on Samsung Exynos design,
     unlike the earlier Armv7 Artpec6 from the same company that was
     part of a separate family of chips.

   - NXP i.MX91 is a cut-down version of i.MX93, using only a single
     Cortex-A55 core.

   - Qualcomm Lemans Auto is a variant of the Lemans SoC that was
     originally merged under the sa8775p name, the differences being
     mostly the firmware configuration of the platform.

   - Four new Renesas SoCs RZ/T2H (r9a09g077m44), RZ/N2H (r9a09g087m44),
     RZ/T2H (r9a09g077), and RZ/N2H (r9a09g087) are all industrial
     bedded SoCs based on Cortex-A55 cores

  In total, there are 65 new machines, including:

   - Industrial embedded system and single-board computers based on NXP,
     Allwinner, TI, Rockchips, Marvell, Xilinx Spacemit, Starfive chips.

   - Reference boards for the newly added Renesas, Qualcomm, NXP and
     Axis ARMv8 chips as well as Microchip's MPFS RISC-V SoC

   - Laptops and Workstations using Apple M2 and Qualcomm Snapdragon X1
     chips.

   - Several Samsung phones using Qualcomm Snapdragon chips

   - Set-top boxes based on Allwinner H313

   - Five BMC boards using 32-bit ASpeed SoCs

   - Three network routers using IXP4xx (ARMv5!) and Broadcom bcm4708
     (ARMv7) SoCs

  Two machines get phased out because they were available only in small
  quantities but never made it into products: one STi407 based reference
  board, and a Snapdragon 845 based Chromebook.

  Aside from the newly added machines, a lot of work went into improving
  hardware support on the existing machines and cleaning up contents for
  validation"

* tag 'soc-dt-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (931 commits)
  arm64: dts: apm-shadowcat: Drop "apm,xgene2-pcie" compatible
  arm64: dts: apm-shadowcat: Move slimpro nodes out of "simple-bus" node
  ARM: dts: microchip: sam9x7: Add qspi controller
  arm64: dts: qcom: Add MST pixel streams for displayport
  arm64: dts: qcom: sm6350: correct DP compatibility strings
  arm64: dts: qcom: monaco-evk: Enable Adreno 623 GPU
  arm64: dts: qcom: qcs8300-ride: Enable Adreno 623 GPU
  arm64: dts: qcom: qcs8300: Add gpu and gmu nodes
  arm64: dts: allwinner: h313: Add Amediatech X96Q
  dt-bindings: arm: sunxi: Add Amediatech X96Q
  arm64: dts: apple: t8015: Add SPMI node
  arm64: dts: apple: t8012: Add SPMI node
  arm64: dts: apple: Add J180d (Mac Pro, M2 Ultra, 2023) device tree
  arm64: dts: rockchip: Add devicetree for the ROC-RK3588-RT
  dt-bindings: arm: rockchip: Add Firefly ROC-RK3588-RT
  arm64: dts: rockchip: update pinctrl names for Radxa E52C
  arm64: dts: rockchip: remove vcc_3v3_pmu regulator for Radxa E52C
  arm64: dts: apple: Add J474s, J475c and J475d device trees
  arm64: dts: apple: Add J414 and J416 Macbook Pro device trees
  arm64: dts: apple: Add initial t6020/t6021/t6022 DTs
  ...
 2025-10-01 17:19:38 -07:00
Dharma Balasubiramani
c656932c3e ARM: dts: microchip: sam9x7: Add qspi controller 
Add support for QSPI controller.

Signed-off-by: Dharma Balasubiramani <dharma.b@microchip.com>
Link: https://lore.kernel.org/r/20250915-sam9x7-qspi-dtsi-v1-1-1cc9adba7573@microchip.com
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
 2025-09-22 18:20:34 +02:00
Ryan Wanner
217efb4409 ARM: dts: microchip: sama7d65: Force SDMMC Legacy mode 
The SDMMC in this IP currently only supports legacy mode
due to a hardware quirk, setting the flags to reflect the limitation.

Fixes: deaa14ab6b ("ARM: dts: microchip: add support for sama7d65_curiosity board")
Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20250819170528.126010-1-Ryan.Wanner@microchip.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
 2025-09-03 18:52:08 +02:00
Nicolas Ferre
82ab67d762 ARM: dts: microchip: sama7d65: add uart3 definition for flexcom3 peripheral 
Add the definition of uart3 at the side of i2c3 for flexcom3.

Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Reviewed-by: Ryan Wanner <ryan.wanner@microchip.com>
Link: https://lore.kernel.org/r/20250905092044.25429-1-nicolas.ferre@microchip.com
[claudiu.beznea: moved atmel,usart-mode at the end of the node to comply
 with dts coding style]
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
 2025-08-30 11:38:55 +03:00
Ryan Wanner
04334f9e8e ARM: dts: microchip: sama7d65: Add GPIO buttons and LEDs 
Add the USER button as a GPIO input as well as add the LEDs and enable
the blue LED as a heartbeat.

Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Link: https://lore.kernel.org/r/20250917210409.503830-1-Ryan.Wanner@microchip.com
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
 2025-09-22 15:26:41 +02:00
Krzysztof Kozlowski
d0fd848949 ARM: dts: microchip: Minor whitespace cleanup 
The DTS code coding style expects exactly one space around '=' or '{'
characters.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20250819131736.86862-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
 2025-08-22 18:10:52 +03:00
Mihai Sain
314862edb1 ARM: dts: microchip: sama7g5: Add cache configuration for cpu node 
Describe the cache memories according with datasheet chapter 15.2:

- L1 cache configuration with 32KB for both data and instruction cache.
- L2 cache configuration with 256KB unified cache.

Before this patch the kernel reported the warning:

[    0.171425] cacheinfo: Unable to detect cache hierarchy for CPU 0

Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
Link: https://lore.kernel.org/r/20250619070636.8844-3-mihai.sain@microchip.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
 2025-07-05 10:43:31 +03:00
Mihai Sain
4101c8274b ARM: dts: microchip: sama7d65: Add cache configuration for cpu node 
Describe the cache memories according with datasheet chapter 15.2:

- L1 cache configuration with 32KB for both data and instruction cache.
- L2 cache configuration with 256KB unified cache.

Before this patch the kernel reported the warning:

[    0.161955] cacheinfo: Unable to detect cache hierarchy for CPU 0

Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
Link: https://lore.kernel.org/r/20250619070636.8844-2-mihai.sain@microchip.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
 2025-07-05 10:43:30 +03:00
Mihai Sain
1e2e0ed390 ARM: dts: microchip: sama5d4: Update the cache configuration for CPU 
Add the memory size properties for L1 and L2 according with block
diagram from datasheet:

- L1 cache configuration with 32 KB for both data and instruction cache.
- L2 cache configuration with 128 KB unified cache.

[root@sama5d4 ~]$ lscpu
Architecture:             armv7l
  Byte Order:             Little Endian
CPU(s):                   1
  On-line CPU(s) list:    0
Vendor ID:                ARM
  Model name:             Cortex-A5
Caches (sum of all):
  L1d:                    32 KiB (1 instance)
  L1i:                    32 KiB (1 instance)
  L2:                     128 KiB (1 instance)

Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
Link: https://lore.kernel.org/r/20250625064934.4828-4-mihai.sain@microchip.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
 2025-07-05 10:37:29 +03:00
Mihai Sain
31a8202459 ARM: dts: microchip: sama5d3: Update the cache configuration for CPU 
Add the memory size properties for L1 according with block
diagram from datasheet:

- L1 cache configuration with 32 KB for both data and instruction cache.

[root@sama5d3 ~]$ lscpu
Architecture:             armv7l
  Byte Order:             Little Endian
CPU(s):                   1
  On-line CPU(s) list:    0
Vendor ID:                ARM
  Model name:             Cortex-A5
Caches (sum of all):
  L1d:                    32 KiB (1 instance)
  L1i:                    32 KiB (1 instance)

Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
Link: https://lore.kernel.org/r/20250625064934.4828-3-mihai.sain@microchip.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
 2025-07-05 10:37:28 +03:00
Mihai Sain
ab435d1265 ARM: dts: microchip: sama5d2: Update the cache configuration for CPU 
Add the memory size properties for L1 and L2 according with block
diagram from datasheet:

- L1 cache configuration with 32 KB for both data and instruction cache.
- L2 cache configuration with 128 KB unified cache.

[root@sama5d2 ~]$ lscpu
Architecture:             armv7l
  Byte Order:             Little Endian
CPU(s):                   1
  On-line CPU(s) list:    0
Vendor ID:                ARM
  Model name:             Cortex-A5
Caches (sum of all):
  L1d:                    32 KiB (1 instance)
  L1i:                    32 KiB (1 instance)
  L2:                     128 KiB (1 instance)

Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
Link: https://lore.kernel.org/r/20250625064934.4828-2-mihai.sain@microchip.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
 2025-07-05 10:37:28 +03:00
Dharma Balasubiramani
7360dab3be ARM: dts: microchip: sam9x7: Add LVDS controller 
Add support for LVDS controller.

Signed-off-by: Dharma Balasubiramani <dharma.b@microchip.com>
Link: https://lore.kernel.org/r/20250625-b4-sam9x7-dts-v1-1-92aaee14ed16@microchip.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
 2025-06-25 19:13:22 +03:00
Manikandan Muralidharan
5b4522098b ARM: dts: microchip: sama5d2_icp: rename spi-cs-setup-ns property to spi-cs-setup-delay-ns 
The naming scheme for delay properties includes "delay" in the name,
so renaming spi-cs-setup-ns property to spi-cs-setup-delay-ns.

Fixes: 46a8a137d8 ("ARM: dts: at91: sama5d2_icp: Set sst26vf064b SPI NOR flash at its maximum frequency")
Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Link: https://lore.kernel.org/r/20250521054309.361894-4-manikandan.m@microchip.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
 2025-06-24 10:12:23 +03:00
Manikandan Muralidharan
fa664ff76e ARM: dts: microchip: sama5d27_wlsom1: rename spi-cs-setup-ns property to spi-cs-setup-delay-ns 
The naming scheme for delay properties includes "delay" in the name,
so renaming spi-cs-setup-ns property to spi-cs-setup-delay-ns.

Fixes: 417e58ea41 ("ARM: dts: at91-sama5d27_wlsom1: Set sst26vf064b SPI NOR flash at its maximum frequency")
Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Link: https://lore.kernel.org/r/20250521054309.361894-3-manikandan.m@microchip.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
 2025-06-24 10:12:23 +03:00
Manikandan Muralidharan
71c6dc93e9 ARM: dts: microchip: sama5d27_som1: rename spi-cs-setup-ns property to spi-cs-setup-delay-ns 
The naming scheme for delay properties includes "delay" in the name,
so renaming spi-cs-setup-ns property to spi-cs-setup-delay-ns.

Fixes: 09ce865122 ("ARM: dts: at91-sama5d27_som1: Set sst26vf064b SPI NOR flash at its maximum frequency")
Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com>
Reviewed-by: Alexander Dahl <ada@thorsis.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Link: https://lore.kernel.org/r/20250521054309.361894-2-manikandan.m@microchip.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
 2025-06-24 10:12:22 +03:00
Manikandan Muralidharan
55fae6f3e5 ARM: dts: microchip: sam9x60ek: rename spi-cs-setup-ns property to spi-cs-setup-delay-ns 
The naming scheme for delay properties includes "delay" in the name,
so renaming spi-cs-setup-ns property to spi-cs-setup-delay-ns.

Fixes: 2c0a1faa4d ("ARM: dts: at91: sam9x60ek: Set sst26vf064b SPI NOR flash at its maximum frequency")
Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com>
Reviewed-by: Alexander Dahl <ada@thorsis.com>
Link: https://lore.kernel.org/r/20250521054309.361894-1-manikandan.m@microchip.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
 2025-06-24 10:12:22 +03:00
Fabio Estevam
51860eebc9 ARM: dts: at91-sama5d27_wlsom1: Improve the Wifi compatible 
The at91-sama5d27_wlsom1 SoM has a WIL3000 Wifi SDIO device populated.

Improve the description of the Wifi compatible string by passing the
more specific "microchip,wilc3000" string.

Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Link: https://lore.kernel.org/r/20250617140502.1042812-1-festevam@gmail.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
 2025-06-22 17:08:50 +03:00
Ezra Buehler
7c0650f1f9 ARM: dts: microchip: gardena-smart-gateway: Fix power LED 
When starting up, the GARDENA smart Gateway's power LED should be
flashing green. It is unclear why this has not been done earlier.

The LED frequency cannot be configured in the devicetree. Luckily, the
default is 1 Hz, which is what we want.

Signed-off-by: Ezra Buehler <ezra.buehler@husqvarnagroup.com>
Link: https://lore.kernel.org/r/20250612074737.311346-1-ezra@easyb.ch
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
 2025-06-22 17:06:52 +03:00
Ryan Wanner
2e24723492 ARM: dts: microchip: sam9x7: Add clock name property 
Add clock-output-names to the xtal nodes, so the driver can correctly
register the main and slow xtal.

This fixes the issue of the SoC clock driver not being able to find
the main xtal and slow xtal correctly causing a bad clock tree.

Fixes: 41af45af8b ("ARM: dts: at91: sam9x7: add device tree for SoC")
Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Link: https://lore.kernel.org/r/036518968ac657b93e315bb550b822b59ae6f17c.1750175453.git.Ryan.Wanner@microchip.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
 2025-06-22 16:58:15 +03:00
Ryan Wanner
0029468132 ARM: dts: microchip: sama7d65: Add clock name property 
Add clock-output-names to the xtal nodes, so the driver can correctly
register the main and slow xtal.

This fixes the issue of the SoC clock driver not being able to find
the main xtal and slow xtal correctly causing a bad clock tree.

Fixes: 261dcfad1b ("ARM: dts: microchip: add sama7d65 SoC DT")
Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Link: https://lore.kernel.org/r/3878ae6d0016d46f0c91bd379146d575d5d336aa.1750175453.git.Ryan.Wanner@microchip.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
 2025-06-22 16:58:15 +03:00
Ryan Wanner
47b77557d3 ARM: dts: microchip: sama7g5: Adjust clock xtal phandle 
Adjust clock xtal phandles to match the new xtal phandle formatting.

Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Link: https://lore.kernel.org/r/8a9ece664958d07b1be73b4b6676a2a2ee397a94.1750175453.git.Ryan.Wanner@microchip.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
 2025-06-22 16:58:14 +03:00
Dharma Balasubiramani
11b83df6bb ARM: dts: microchip: sam9x7: Add HLCD controller 
Add support for HLCD controller.

Signed-off-by: Dharma Balasubiramani <dharma.b@microchip.com>
Link: https://lore.kernel.org/r/20250611-sam9x7-dts-v1-1-7f52fcb488ad@microchip.com
[claudiu.beznea: keep reg the 1st property on port@0 to comply with dts
 coding style]
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
 2025-06-22 16:57:14 +03:00
Ryan Wanner
198b54b0a6 ARM: dts: microchip: sama7d65: Enable CAN bus 
Enable CAN bus for SAMA7D65 curiosity board.

Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Link: https://lore.kernel.org/r/ab719861de53432bdf19593fa4eee40adf57aed9.1749666053.git.Ryan.Wanner@microchip.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
 2025-06-22 16:44:55 +03:00
Ryan Wanner
5a4aad596e ARM: dts: microchip: sama7d65: Clean up extra space 
Remove the extra space that causes formatting issues.

Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Link: https://lore.kernel.org/r/ac1decc35e2b4f706cf6ab9378f2c88e5295dde4.1749666053.git.Ryan.Wanner@microchip.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
 2025-06-22 16:44:55 +03:00
Ryan Wanner
ec9a309d0c ARM: dts: microchip: sama7d65: Add CAN bus support 
Add support for CAN bus to the SAMA7D65 SoC.

Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Link: https://lore.kernel.org/r/f80a4206c05ed5d80a9527476963a18070ca42b6.1749666053.git.Ryan.Wanner@microchip.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
 2025-06-22 16:44:54 +03:00
Ryan Wanner
a9ea0d5f70 ARM: dts: microchip: sama7d65: Add PWM support 
Add support for PWMs to the SAMA7D65 SoC.

Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Link: https://lore.kernel.org/r/195c69a19be1ff14736db402e0f1ee64438b4b20.1749666053.git.Ryan.Wanner@microchip.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
 2025-06-22 16:44:54 +03:00
Ryan Wanner
71b39aeaaf ARM: dts: microchip: sama7d65: Add crypto support 
Add and enable SHA, AES, TDES, and TRNG for SAMA7D65 SoC.

Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Link: https://lore.kernel.org/r/fc791949c97f368f32a710e64d8db4018e45e70f.1749666053.git.Ryan.Wanner@microchip.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
 2025-06-22 16:44:53 +03:00
Wolfram Sang
9c2026fe46 ARM: dts: microchip: use recent scl/sda gpio bindings 
We have dedictaded bindings for scl/sda nowadays. Switch away from the
deprecated plain 'gpios' property.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Link: https://lore.kernel.org/r/20250519112107.2980-4-wsa+renesas@sang-engineering.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
 2025-06-22 16:41:56 +03:00
Mihai Sain
36e9e1ab59 ARM: dts: microchip: sama7g54_curiosity: Add fixed-partitions for spi-nor flash 
Add fixed-partitions for spi-nor flash to match the at91 boot flow
and layout of the nand flash.
Partitions can be listed from /proc/mtd:

[root@sama7g54 ~]$ cat /proc/mtd | grep qspi
mtd6: 00040000 00001000 "qspi1: at91bootstrap"
mtd7: 00100000 00001000 "qspi1: u-boot"
mtd8: 00040000 00001000 "qspi1: u-boot env"
mtd9: 00080000 00001000 "qspi1: device tree"
mtd10: 00600000 00001000 "qspi1: kernel"

[root@sama7g54 ~]$ mtdinfo /dev/mtd10
mtd10
Name:                           qspi1: kernel
Type:                           nor
Eraseblock size:                4096 bytes, 4.0 KiB
Amount of eraseblocks:          1536 (6291456 bytes, 6.0 MiB)
Minimum input/output unit size: 1 byte
Sub-page size:                  1 byte
Character device major/minor:   90:20
Bad blocks are allowed:         false
Device is writable:             true

Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
Link: https://lore.kernel.org/r/20250429064547.5807-1-mihai.sain@microchip.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
 2025-05-16 08:31:29 +03:00
Ryan Wanner
e634fd7166 ARM: dts: microchip: sama7d65: Add RTT timer to curiosity board 
Add RTT timer with backup register for SAMA7D65_Curiosity board.

Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Link: https://lore.kernel.org/r/463581224a07bf122c6907d34a0c5c71b1cc73e1.1744666011.git.Ryan.Wanner@microchip.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
 2025-05-16 08:31:29 +03:00
Ryan Wanner
4b3d951f28 ARM: dts: microchip: sama7d65: Add RTT and GPBR Support for sama7d65 SoC 
Add RTT support for SAMA7D65 SoC. The GPBR is added so the SoC is able
to store the RTT time data.

Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Link: https://lore.kernel.org/r/e8868ef06102241b47883ba10edaed751831be6d.1744666011.git.Ryan.Wanner@microchip.com
[claudiu.beznea: keep nodes sorted by their address]
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
 2025-05-16 08:31:29 +03:00
Ryan Wanner
f5b56abe58 ARM: dts: microchip: sama7d65: Add SRAM and DRAM components support 
Add SRAM, secumod, UDDRC, and DDR3phy to enable support for low power modes.

Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Link: https://lore.kernel.org/r/354ecd628fdd292d2125570a6b10a93cbecb7706.1744666011.git.Ryan.Wanner@microchip.com
[claudiu.beznea: keep nodes sorted by their address]
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
 2025-05-16 08:31:28 +03:00
Ryan Wanner
0bbc54da32 ARM: dts: microchip: sama7d65_curiosity: add EEPROM 
If the MAC address is not fetched and loaded by U-boot then Linux will
have to load the address. The EEPROM and nvmem-layout to describe
EUI48 MAC address regions.

Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Link: https://lore.kernel.org/r/96ee6832d9b55acfae8d3560f625798025dfd89c.1743523114.git.Ryan.Wanner@microchip.com
[claudiu.beznea: added nvmem properties in gmac0 node before the status
 one]
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
 2025-05-16 08:31:28 +03:00
Ryan Wanner
e65a13a290 ARM: dts: microchip: sama7d65: Add MCP16502 to sama7d65 curiosity 
Add MCP16502 to the sama7d65_curiosity board to control voltages in the
MPU. The device is connected to twi 10 interface

Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Link: https://lore.kernel.org/r/60f6b7764227bb42c74404e8ca1388477183b7b5.1743523114.git.Ryan.Wanner@microchip.com
[claudiu.beznea: drop regulator-suspend-voltage for ldo2 as it is not
 needed]
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
 2025-05-16 08:31:28 +03:00
Ryan Wanner
7116fb2f15 ARM: dts: microchip: sama7d65: Enable GMAC interface 
Enable GMAC0 interface for sama7d65_curiosity board.

Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Link: https://lore.kernel.org/r/fca0c1deb74006cdedbdd71061dec9dabf1e9b9a.1743523114.git.Ryan.Wanner@microchip.com
[claudiu.beznea: move gmac0 node to keep the nodes alphanumerically
 sorted, dropped status property on the PHY node, added missing blank
 line]
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
 2025-05-16 08:31:28 +03:00
Ryan Wanner
b51e4aea3e ARM: dts: microchip: sama7d65: Add FLEXCOMs to sama7d65 SoC 
Add FLEXCOMs to the SAMA7D65 SoC device tree.

Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Link: https://lore.kernel.org/r/d474fcd850978261ac889950ac1c3a36bc6d3926.1743523114.git.Ryan.Wanner@microchip.com
[claudiu.beznea: use vendor specific properties at the end of the node,
 align DMA entries, add missing spaces]
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
 2025-05-16 08:31:27 +03:00
Ryan Wanner
37aa981a33 ARM: dts: microchip: sama7d65: Add gmac interfaces for sama7d65 SoC 
Add support for GMAC interfaces on SAMA7D65 SoC.

Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Link: https://lore.kernel.org/r/05b107796b6f3a173d0dd0a5b2107b675cfd994e.1743523114.git.Ryan.Wanner@microchip.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
 2025-05-16 08:31:26 +03:00
Wolfram Sang
c72ede1c24 ARM: dts: at91: at91sam9263: fix NAND chip selects 
NAND did not work on my USB-A9263. I discovered that the offending
commit converted the PIO bank for chip selects wrongly, so all A9263
boards need to be fixed.

Fixes: 1004a2977b ("ARM: dts: at91: Switch to the new NAND bindings")
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Link: https://lore.kernel.org/r/20250402210446.5972-2-wsa+renesas@sang-engineering.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
 2025-04-11 10:41:30 +03:00
Wolfram Sang
dc658570a2 ARM: dts: at91: usb_a9g20: move wrong RTC node 
Only the LPW variant has the external RTC. Move it to that board
specific DT. As a result, the common include for A9G20 boards can
go now.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Link: https://lore.kernel.org/r/20250402204856.5197-5-wsa+renesas@sang-engineering.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
 2025-04-11 10:39:36 +03:00
Wolfram Sang
3984cc0f79 ARM: dts: at91: calao_usb: simplify chosen node 
All devices use equal parameters in 'chosen'. So, the memory node can
be put into the most generic DTSI.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Link: https://lore.kernel.org/r/20250402204856.5197-4-wsa+renesas@sang-engineering.com
[claudiu.beznea: s/can bet put/can be put/g in commit description]
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
 2025-04-11 10:39:35 +03:00
Wolfram Sang
1477dd96e9 ARM: dts: at91: usb_a9260: use 'stdout-path' 
Do not use the kernel command line for specifying the default serial
console.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Link: https://lore.kernel.org/r/20250402204856.5197-3-wsa+renesas@sang-engineering.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
 2025-04-11 10:39:35 +03:00
Wolfram Sang
2b72d99c63 ARM: dts: at91: calao_usb: simplify memory node 
All devices have 64MB RAM. So, the memory node can be put into the
most generic DTSI.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Link: https://lore.kernel.org/r/20250402204856.5197-2-wsa+renesas@sang-engineering.com
[claudiu.beznea: s/can bet put/can be put/g in commit description]
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
 2025-04-11 10:39:34 +03:00
Wolfram Sang
67ba341e57 ARM: dts: at91: usb_a9263: fix GPIO for Dataflash chip select 
Dataflash did not work on my board. After checking schematics and using
the proper GPIO, it works now. Also, make it active low to avoid:

flash@0 enforce active low on GPIO handle

Fixes: 2432d20146 ("ARM: at91: dt: usb-a9263: add dataflash support")
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20250404112742.67416-2-wsa+renesas@sang-engineering.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
 2025-04-11 10:39:34 +03:00
Wolfram Sang
6f7549bdb9 ARM: dts: at91: usb_a9g20: add SPI EEPROM 
Schematics and board layout indicate that versions with a dataflash
instead of an EEPROM might exist. Let's handle that once we have
hardware to test.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20250403064336.4846-2-wsa+renesas@sang-engineering.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
 2025-04-11 10:39:33 +03:00
Nayab Sayed
6aafec3d21 ARM: dts: microchip: sama7g5: add ADC hw trigger edge type 
Set ADC trigger edge type property as interrupt edge rising value.

Signed-off-by: Nayab Sayed <nayabbasha.sayed@microchip.com>
Link: https://lore.kernel.org/r/20250304-sama7g5-hw-trigger-enable-v1-1-61b5618285f0@microchip.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
 2025-03-04 20:39:29 +02:00
Ryan Wanner
df41b7c0cc ARM: dts: microchip: sama7d65: Add watchdog for sama7d65 
Add watchdog timer support for SAMA7D65 SoC.

Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Link: https://lore.kernel.org/r/05785a34b9181b7debb57c1896cc733bd3088c56.1740675317.git.Ryan.Wanner@microchip.com
[claudiu.beznea: fixed conflict]
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
 2025-03-03 20:57:49 +02:00
Ryan Wanner
e89b7cc877 ARM: dts: microchip: sama7d65: Enable shutdown controller 
Enable shutdown controller to support shutdown and wake up.

Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Link: https://lore.kernel.org/r/c31c40eb388b2fc0ad6ee17ed2e23bcd04e8e1c8.1740671156.git.Ryan.Wanner@microchip.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
 2025-03-02 17:49:09 +02:00
Ryan Wanner
640276c3e3 ARM: dts: microchip: sama7d65: Add SFRBU support to sama7d65 
Add SFRBU support to the SAMA7D65 SoC. This is required to change the power
source for backup mode for the SoC.

Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Link: https://lore.kernel.org/r/dbc51f95f301c106c031fb93f84d0d847e818d91.1740671156.git.Ryan.Wanner@microchip.com
[claudiu.beznea: fixed conflict]
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
 2025-03-02 17:48:39 +02:00
Ryan Wanner
3e2b7addb6 ARM: dts: microchip: sama7d65: Add RTC support for sama7d65 
Add RTC support for the SAMA7D65 SoC.

Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Link: https://lore.kernel.org/r/fa1587ffef21a8198317062c15d8eb5c3ca6187c.1740671156.git.Ryan.Wanner@microchip.com
[claudiu.beznea: fixed conflict, keep nodes sorted by their addresses]
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
 2025-03-02 17:46:11 +02:00
Ryan Wanner
3121396214 ARM: dts: microchip: sama7d65: Add Shutdown controller support 
Add shutdown controller support for SAMA7D65 SoC.

Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Link: https://lore.kernel.org/r/ffc76b757cd1ba4ca38947f8b30525b848aa8ad7.1740671156.git.Ryan.Wanner@microchip.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
 2025-03-02 17:42:38 +02:00