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ARM: dts: microchip: sama7d65: Add CAN bus support

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Add support for CAN bus to the SAMA7D65 SoC.

Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Link: https://lore.kernel.org/r/f80a4206c05ed5d80a9527476963a18070ca42b6.1749666053.git.Ryan.Wanner@microchip.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
This commit is contained in:
Ryan Wanner
2025-06-11 12:47:32 -07:00
committed by Claudiu Beznea
parent a9ea0d5f70
commit ec9a309d0c
1 changed files with 80 additions and 0 deletions
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80
arch/arm/boot/dts/microchip/sama7d65.dtsi
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@@ -163,6 +163,86 @@ chipid@e0020000 {
reg = <0xe0020000 0x8>;
};
can0: can@e0828000 {
compatible = "bosch,m_can";
reg = <0xe0828000 0x200>, <0x100000 0x7800>;
reg-names = "m_can", "message_ram";
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
clocks = <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>;
clock-names = "hclk", "cclk";
assigned-clocks = <&pmc PMC_TYPE_GCK 58>;
assigned-clock-rates = <40000000>;
assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>;
status = "disabled";
};
can1: can@e082c000 {
compatible = "bosch,m_can";
reg = <0xe082c000 0x200>, <0x100000 0xbc00>;
reg-names = "m_can", "message_ram";
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
clocks = <&pmc PMC_TYPE_PERIPHERAL 59>, <&pmc PMC_TYPE_GCK 59>;
clock-names = "hclk", "cclk";
assigned-clocks = <&pmc PMC_TYPE_GCK 59>;
assigned-clock-rates = <40000000>;
assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>;
status = "disabled";
};
can2: can@e0830000 {
compatible = "bosch,m_can";
reg = <0xe0830000 0x200>, <0x100000 0x10000>;
reg-names = "m_can", "message_ram";
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
clocks = <&pmc PMC_TYPE_PERIPHERAL 60>, <&pmc PMC_TYPE_GCK 60>;
clock-names = "hclk", "cclk";
assigned-clocks = <&pmc PMC_TYPE_GCK 60>;
assigned-clock-rates = <40000000>;
assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
bosch,mram-cfg = <0xbc00 0 0 64 0 0 32 32>;
status = "disabled";
};
can3: can@e0834000 {
compatible = "bosch,m_can";
reg = <0xe0834000 0x200>, <0x110000 0x4400>;
reg-names = "m_can", "message_ram";
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
clocks = <&pmc PMC_TYPE_PERIPHERAL 61>, <&pmc PMC_TYPE_GCK 61>;
clock-names = "hclk", "cclk";
assigned-clocks = <&pmc PMC_TYPE_GCK 61>;
assigned-clock-rates = <40000000>;
assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>;
status = "disabled";
};
can4: can@e0838000 {
compatible = "bosch,m_can";
reg = <0xe0838000 0x200>, <0x110000 0x8800>;
reg-names = "m_can", "message_ram";
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
clocks = <&pmc PMC_TYPE_PERIPHERAL 62>, <&pmc PMC_TYPE_GCK 62>;
clock-names = "hclk", "cclk";
assigned-clocks = <&pmc PMC_TYPE_GCK 62>;
assigned-clock-rates = <40000000>;
assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
bosch,mram-cfg = <0x4400 0 0 64 0 0 32 32>;
status = "disabled";
};
dma2: dma-controller@e1200000 {
compatible = "microchip,sama7d65-dma", "microchip,sama7g5-dma";
reg = <0xe1200000 0x1000>;