Arm SCMI updates/fixes for v6.18
These SCMI changes bring a mix of improvements, fixes, and cleanups:
1. Device Tree bindings - allow multiple SCMI instances by suffixing
node names (Nikunj Kela).
2. Code hardening - constify both scmi_{transport,voltage_proto}_ops
so they reside in read-only memory (Christophe JAILLET).
3. VirtIO transport initialization - set DRIVER_OK before SCMI probing
to prevent potential stalls; while recent rework removes the practical
risk, this ensures correctness (Junnan Wu).
4. Quirk handling - fix a critical bug by preventing writes to string
constants, avoiding faults in read-only memory (Johan Hovold).
5. i.MX SCMI MISC protocol - extend support to discover board info,
retrieve configuration and build data, and document the new
MISC_BOARD_INFO command; all handled gracefully if unsupported (Peng Fan).
6. Logging cleanup - simplify device tree node name logging by using
the %pOF format to print full paths (Krzysztof Kozlowski).
* tag 'scmi-updates-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
firmware: arm_scmi: Simplify printks with pOF format
firmware: arm_scmi: imx: Discover MISC board info from the system manager
firmware: arm_scmi: imx: Support retrieving MISC protocol configuration info
firmware: arm_scmi: imx: Discover MISC build info from the system manager
firmware: arm_scmi: imx: Add documentation for MISC_BOARD_INFO
firmware: arm_scmi: quirk: Prevent writes to string constants
firmware: arm_scmi: Fix function name typo in scmi_perf_proto_ops struct
firmware: arm_scmi: Mark VirtIO ready before registering scmi_virtio_driver
firmware: arm_scmi: Constify struct scmi_transport_ops
firmware: arm_scmi: Constify struct scmi_voltage_proto_ops
dt-bindings: firmware: arm,scmi: Allow multiple instances
Link: https://lore.kernel.org/r/20250915101341.2987516-1-sudeep.holla@arm.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Samsung SoC drivers for v6.18
1. Google GS101:
Enable CPU Idle, which needs programming C2 idle hints
via ACPM firmware (Alive Clock and Power Manager). The patch
introducing this depends on 'local-timer-stop' Devicetree property,
which was merged in v6.17.
Fix handling error codes in ACPM firmware driver when talking to
PMIC.
2. Exynos2200: Add dedicated compatible for serial engines (USI).
* tag 'samsung-drivers-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
firmware: exynos-acpm: fix PMIC returned errno
dt-bindings: soc: samsung: usi: add samsung,exynos2200-usi compatible
soc: samsung: exynos-pmu: Enable CPU Idle for gs101
Link: https://lore.kernel.org/r/20250912135448.203678-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
generic_delete_inode() is rather misleading for what the routine is
doing. inode_just_drop() should be much clearer.
The new naming is inconsistent with generic_drop_inode(), so rename that
one as well with inode_ as the suffix.
No functional changes.
Signed-off-by: Mateusz Guzik <mjguzik@gmail.com>
Reviewed-by: Jan Kara <jack@suse.cz>
Signed-off-by: Christian Brauner <brauner@kernel.org>
Reset controller updates for v6.18
* Fix the reset tree git repository link in MAINTAINERS.
* Add support for bcm63xx ephy reset control to reset-bcm6345.
* Add support for the AST2700 reset controller, as an auxiliary
device driver to the corresponding clock controller driver.
* Add support for the remaining TH1520 VO subsystem reset controls to
reset-th1520.
* Drop unnecessary .fast_io setting from MMIO regmap_configs.
* tag 'reset-for-v6.18' of https://git.pengutronix.de/git/pza/linux:
reset: remove unneeded 'fast_io' parameter in regmap_config
reset: th1520: add resets for display pipeline
dt-bindings: reset: thead,th1520-reset: add more VOSYS resets
reset: aspeed: register AST2700 reset auxiliary bus device
reset: bcm6345: add support for bcm63xx ephy control register
dt-bindings: reset: add compatible for bcm63xx ephy control
MAINTAINERS: Use https:// protocol for Reset Controller Framework tree
Link: https://lore.kernel.org/r/20250904154135.2385905-1-p.zabel@pengutronix.de
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Further ASPEED devicetree updates for v6.18
New platforms:
- Meta Clemente
Clemente is a compute-tray platform using an AST2600 SoC
Updated platforms:
- Harma (Meta): Hot-swap controller, power monitoring, GPIO names
There are also some devicetree cleanups from Rob and Krzysztof that touch a
variety of platforms and the DTSIs. These lead to fewer warnings emitted for the
ASPEED devicetrees.
* tag 'aspeed-6.18-devicetree-1' of https://git.kernel.org/pub/scm/linux/kernel/git/bmc/linux:
ARM: dts: aspeed: Drop syscon "reg-io-width" properties
ARM: dts: aspeed: Drop "sdhci" compatibles
ARM: dts: aspeed: Fix/add I2C device vendor prefixes
ARM: dts: aspeed: Minor whitespace cleanup
ARM: dts: aspeed: clemente: add Meta Clemente BMC
ARM: dts: aspeed: Add NCSI3 and NCSI4 pinctrl nodes
dt-bindings: arm: aspeed: add Meta Clemente board
ARM: dts: aspeed: harma: add mp5990
ARM: dts: aspeed: harma: revise gpio name
ARM: dts: aspeed: harma: add power monitor support
Link: https://lore.kernel.org/r/5793039afcedeb28179a3c9909631d8251abc73e.camel@codeconstruct.com.au
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
dt-bindings: Changes for v6.18-rc1
Support for the Tegra264 generation of I2C is documented as well as some
older Tegra devices, such as the Xiaomi Mi Pad and the ASUS 101 devices.
Contained are also some additions to existing bindings for Tegra114 and
a fix for the power supply feeding VI/CSI.
* tag 'tegra-for-6.18-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
dt-bindings: arm: tegra: Add ASUS TF101G and SL101
dt-bindings: reset: Add Tegra114 CAR header
dt-bindings: arm: tegra: Add Xiaomi Mi Pad (A0101)
dt-bindings: clock: tegra30: Add IDs for CSI pad clocks
dt-bindings: display: tegra: Move avdd-dsi-csi-supply from VI to CSI
dt-bindings: i2c: nvidia,tegra20-i2c: Document Tegra264 I2C
Link: https://lore.kernel.org/r/20250914063927.89981-1-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
arm64: Xilinx DT changes for 6.18
- Fix some issues reported by dtschema
- Properly mark EMMC devices
- Update PSCI version
- Update DP description and enable it on boards
- Disable DEBUG IPs by default
SOM:
- Describe usb hubs
- Fix PWM polarity issue
- Add support for k24, kr260 and kd240
Versal NET:
- Describe CPU cache layout
- Fix RTC calibration value
* tag 'zynqmp-dt-for-6.18' of https://github.com/Xilinx/linux-xlnx:
arm64: versal-net: Describe L1/L2/L3/LLC caches
arm64: zynqmp: Enable DP in kr260/kv260 revA
arm64: zynqmp: Describe ethernet controllers via aliases on SOM
arm64: zynqmp: Revert usb node drive strength and slew rate for zcu106
arm64: zynqmp: Disable coresight by default
arm64: zynqmp: Add support for kd240 board
arm64: zynqmp: Add support for kr260 board
dt-bindings: soc: xilinx: Add support for K24, KR260 and KD240 CCs
arm64: zynqmp: Enable PSCI 1.0
arm64: zynqmp: Enable DP for zcu100, zcu102, zcu104, zcu111
arm64: zynqmp: Introduce DP port labels
arm64: zynqmp: Fix pwm-fan polarity
arm64: zynqmp: Update the usb5744 hub node as per binding
arm64: zynqmp: Add cap-mmc-hw-reset and no-sd, no-sdio property to eMMC
arm64: zynqmp: Remove undocumented arasan,has-mdma property
arm64: zynqmp: Use generic spi@ name in zcu111-revA
arm64: versal-net: Update rtc calibration value
Link: https://lore.kernel.org/r/CAHTX3dK6if9f+-DW5ZEnfSO4=K_Zje-WH-fwysTY77farsSS9g@mail.gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Qualcomm Arm64 DeviceTree updates for v6.18
Add support for Lenovo Thinkbook 16, Dell Inspiron 7441, Dell Latitude
7455, Samsung Galaxy S20, Billion Capture+, the Monaco EVK and the
Lemans EVK.
The SDM845 Cheza development boards are removed, as they are not longer
in use.
For IPQ5018 crypto, tsens, rng, SPI NAND support is dded, the two MDIO
buses are added and the internal GE PHY.
IPQ5424 gets CPU frequency scaling and a missing UART.
The SA8775P SoC is remaned Lemans, to reduce confusion about the chip
name. The IoT memory map introduced and made the default, GDSP FastRPC
and GPR nodes are added.
Touch keys are enabled on the BQ Aquaris X5 Plus.
On QCM2290 the video accelerator is enabled, so is HS timing modes for
eMMC.
The QCS615 platform is renamed SM6150. CPU frequency scaling and the WiFi
PCIe controller is introduced.
On Monaco (QCS8300) scaling of L3 and DDR bandwidth is introduced. So is
eMMC support and generic packer router (GPR).
On the Monaco Ride board, the eMMC controller is enabled.
On QRB220 RB1, the venus video accelerator is enabled.
For SC7280 the first PCIe controller and PHY is introduced. SoundWire,
LPASS, and USB offload support is added, the codecs and sound card is
then described on the QCM6490 IDP. The MDSS core reset is introduced, to
clear bootloader configuration on SC7280-based devices.
On Fairphone5, USB audio offload is added.
AudioReach support on SC7280 (QCS6490) is introduced and used to
enable sound on the RB3Gen2 board.
The video clock controller is added to SC8180X.
On SC8280XP the GPI DMA controllers are described and enabled.
Display and GPU is enabled for the Fairphone 3 and charging is enabled
on the Google Pixel 3a.
The routing for the second USB connector on the Lenovo Yoga C630 is
described.
On SM6150 ADSP and CDSP FastRPC is introduced, as is the video
encoder/decoder (venus).
On SM6350 RPMh statistics is enabled, the USB audio offload DAI is
introduced and on Fairphone4 the USB audio offload support is enabled.
On SM8450 QRD the PMIC GLINK is described, to add USB Type-C and battery
functionality.
On SM8650 ACD levels are added for the GPU.
Camera and video clock controllers power-domains are updated on SM8450,
SM8550, and SM8650, now that support for multiple power-domains is
accepted.
SM8750 gains bwmon support for dynamic bus scaling, and PCIe nodes.
The DWC3 glue and core nodes are flattened on a number of platforms.
USB Type-C DisplayPort support is extended to 4 lanes (from 2) on a
variety of platforms, now that the QMP PHY driver supports this.
Platform specific RPMh PD constants are replaced with generic constants
wherever possible.
On X Elite the PM8010 is disabled by default, removing boot splats
on a variety of boards without this PMIC, the video clock controller is
added.
For the X Elite and X Plus CRDs, and the Lenovo Thinkpad T14s, HBR3 is
marked as valid for the external DisplayPorts. The fingerprint reader
found on the CRDs are enabled. The PCIe x8 slot on the QCP is enabled.
The two Microsoft Surface Laptop 7 gains WiFi and Bluetooth support.
GPU support is added for the X Plus SoC.
* tag 'qcom-arm64-for-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (208 commits)
arm64: dts: qcom: x1e80100: Update GPU OPP table
arm64: dts: qcom: sm8650: Drop redundant status from PMK8550 RTC
arm64: dts: qcom: add initial support for Samsung Galaxy S20
dt-bindings: arm: qcom: document x1q board binding
arm64: dts: qcom: sm8250-samsung-r8q: Move common parts to dtsi
arm64: dts: qcom: lemans-evk: Add sound card
arm64: dts: qcom: lemans: Add gpr node
arm64: dts: qcom: x1e78100-t14s-oled: Add eDP panel
arm64: dts: qcom: qcs615-ride: enable venus node to initialize video codec
arm64: dts: qcom: sm6150: add venus node to devicetree
arm64: dts: qcom: x1e80100-romulus: Add WCN7850 Wi-Fi/BT
arm64: dts: qcom: qrb2210-rb1: Enable Venus
arm64: dts: qcom: qcm2290: Add Venus video node
arm64: dts: qcom: monaco-evk: Add sound card
arm64: dts: qcom: qcs8300: Add gpr node
arm64: dts: qcom: qcs8300: Add Monaco EVK board
dt-bindings: arm: qcom: Add Monaco EVK support
arm64: dts: qcom: qcm6490-idp: Add sound card
arm64: dts: qcom: qcm6490-idp: Add WSA8830 speakers and WCD9370 headset codec
arm64: dts: qcom: qcs6490-rb3gen2: Add sound card
...
Link: https://lore.kernel.org/r/20250911233600.3033675-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Qualcomm Arm32 DeviceTree updates for v6.18
Bring a few updates to the MSM8960 platform and add support for the Sony
Xperia SP.
Touch keys support is added to the Samsung Galaxy Grand 2.
A number of DeviceTree cleanups.
* tag 'qcom-arm32-for-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
ARM: dts: qcom: Use GIC_SPI for interrupt-map for readability
ARM: dts: qcom: sdx55: Add default GIC address cells
ARM: dts: qcom: ipq8064: Add default GIC address cells
ARM: dts: qcom: apq8064: Add default GIC address cells
ARM: dts: qcom: ipq4019: Add default GIC address cells
ARM: dts: qcom: apq8064-mako: Minor whitespace cleanup
ARM: dts: qcom: msm8226-samsung-ms013g: Add touch keys
ARM: dts: qcom: msm8974-samsung-hlte: Add touchkey support
ARM: dts: qcom: pm8921: add vibrator device node
ARM: dts: qcom: add device tree for Sony Xperia SP
dt-bindings: arm: qcom: add Sony Xperia SP
ARM: dts: qcom: msm8960: disable gsbi1 and gsbi5 nodes in msm8960 dtsi
ARM: dts: qcom: msm8960: add gsbi8 and its serial configuration
ARM: dts: qcom: msm8960: add sdcc3 pinctrl states
Link: https://lore.kernel.org/r/20250911220940.3023575-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
ARM: nxp: lpc: device tree updates for v6.18
This pull request contains device tree changes for ARM NXP LPC32xx and
ARM NXP LPC18xx/LPC43xx for v6.18, please pull the following:
- Frank fixes a multitude of device tree checker warnings reported for
NXP LPC18xx/LPC43xx powered boards,
- Vladimir fixes a number of compile time warnings issued by a dt checker
for NXP LPC32xx powered boards,
- Vladimir replaces Roland as a maintainer of NXP LPC32xx platform
device trees, Roland is inactive for more than 10 years.
* tag 'lpc32xx-dt-for-6.18' of https://github.com/vzapolskiy/linux-lpc32xx:
ARM: dts: lpc32xx: Correct PL080 DMA controller device node name
ARM: dts: lpc32xx: Specify #dma-cells property of PL080 DMA controller
ARM: dts: lpc32xx: Specify a precise version of the SD/MMC controller IP
ARM: dts: lpc32xx: Correct SD/MMC controller device node name
ARM: dts: lpc32xx: Correct motor PWM device tree node name
ARM: dts: lpc32xx: Set motor PWM #pwm-cells property value to 3 cells
dt-bindings: arm: nxp: lpc: Assign myself as maintainer of NXP LPC32xx platforms
ARM: dts: lpc18xx: add missed arm,num-irq-priority-bits
ARM: dts: lpc18xx: add #address-cell and #szie-cell for spi flash controller
ARM: dts: lpc4357-myd-lpc4357: change node name mdio0 to mdio
ARM: dts: lpc: change node name 'button[0-9]' to button-[0-9]'
ARM: dts: lpc4357-myd-lpc4357: add power-supply for innolux,at070tn92
ARM: dts: lpc: add cfg surfix in pinctrl child node
ARM: dts: lpc: add #address-cells and #size-cells for sram node
ARM: dts: lpc18xx: swap clock-names bic and cui
ARM: dts: lpc4350-hitex-eval: change node name flash to flash@0
ARM: dts: lpc18xx: rename node name mmcsd to mmc
ARM: dts: lpc18xx: rename node name flash-controller to spi
Link: https://lore.kernel.org/r/20250911130642.41958-1-vz@mleia.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This pull request contains Broadcom ARM64-based SoCs Device Tree updates
for 6.18, please pull the following:
- Krzysztof fixes a DTC warning for the ARM GIC in bcm2712.dtsi
- Ivan adds the pin controller node(s), an additional GPIO controller,
the second SDHCI controller node for SDIO Wi-Fi, and the UARTA for
Bluetooth to the BCM2712 DTS (Raspberry Pi 5)
- Stanimir adds the Ethernet DT node and enables it for the RP1 sister
chip
- Andrea deletes a number of redundant PCIe DT node enablement, updates
a comment to describe the relationship between bcm2712 and RP1 and
finally enables the USB controllers with RP1
* tag 'arm-soc/for-6.18/devicetree-arm64' of https://github.com/Broadcom/stblinux:
arm64: dts: broadcom: Enable USB devicetree entries for Rpi5
arm64: dts: broadcom: rp1: Add USB nodes
arm64: dts: broadcom: amend the comment about the role of BCM2712 board DTS
arm64: dts: broadcom: delete redundant pcie enablement nodes
arm64: dts: broadcom: Enable RP1 ethernet for Raspberry Pi 5
arm64: dts: rp1: Add ethernet DT node
dt-bindings: mmc: Add support for capabilities to Broadcom SDHCI controller
arm64: dts: broadcom: bcm2712: Add UARTA controller node
arm64: dts: broadcom: bcm2712: Add second SDHCI controller node
arm64: dts: broadcom: bcm2712: Add one more GPIO node
arm64: dts: broadcom: bcm2712: Add pin controller nodes
arm64: dts: broadcom: bcm2712: Add default GIC address cells
Link: https://lore.kernel.org/r/20250910171910.666401-3-florian.fainelli@broadcom.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Samsung DTS ARM changes for v6.18
1. Drop S3C2416 SoC from bindings, because it was removed from kernel
in 2023.
2. Add Ethernet attached via SROM controller (memory bus) on SMDK5250.
This wasn't tested, but code should work just like it is working on
Exynos5410-based boards.
* tag 'samsung-dt-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
ARM: dts: samsung: smdk5250: add sromc node
ARM: dts: samsung: exynos5250: describe sromc bank memory map
ARM: dts: samsung: exynos5410: use multiple tuples for sromc ranges
dt-bindings: arm: samsung: Drop S3C2416
Link: https://lore.kernel.org/r/20250909184559.105777-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
New boards: FriendlyElec NanoPi Zero2, ArmSoM Sige1, Radxa ROCK 2A/2F,
HINLINK H66K / H68K .
Interesting new peripherals: I guess the most interesting one is likely
the NPU on RK3588. The rocket driver has been merged into both the DRM
tree as well as mainline Mesa.
Other stll interesting ones are DW-Displayport on RK3588, DSI on RK3576
(missing soc pwm-support to be useful on most boards), thermal support
and watchdog on RK3576.
The rest peripheral additions on a number of boards (Beelink A1,
Pine{phone,book}, rk3576-evb1-v10, Rock 5*, ...)
* tag 'v6.18-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (46 commits)
arm64: dts: rockchip: Enable DP2HDMI for ROCK 5 ITX
arm64: dts: rockchip: Enable DisplayPort for rk3588s Cool Pi 4B
arm64: dts: rockchip: Add DP1 for rk3588
arm64: dts: rockchip: Add DP0 for rk3588
arm64: dts: rockchip: Add FriendlyElec NanoPi Zero2
dt-bindings: arm: rockchip: Add FriendlyElec NanoPi Zero2
arm64: dts: rockchip: Add ArmSoM Sige1
dt-bindings: arm: rockchip: Add ArmSoM Sige1
arm64: dts: rockchip: Add Radxa ROCK 2A/2F
dt-bindings: arm: rockchip: Add Radxa ROCK 2A/2F
dt-bindings: soc: rockchip: add missing clock reference for rk3576-dcphy syscon
arm64: dts: rockchip: add USB3 on Beelink A1
arm64: dts: rockchip: add SPDIF audio to Beelink A1
arm64: dts: rockchip: add IR receiver to rk3328-roc
arm64: dts: rockchip: Further describe the WiFi for the Pinephone Pro
arm64: dts: rockchip: Further describe the WiFi for the Pinebook Pro
arm64: dts: rockchip: Enable the NPU on NanoPi R6C/R6S
arm64: dts: rockchip: enable NPU on OPI5/5B
arm64: dts: rockchip: Add Bluetooth on rk3576-evb1-v10
arm64: dts: rockchip: Add WiFi on rk3576-evb1-v10
...
Link: https://lore.kernel.org/r/5241735.C4sosBPzcN@phil
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Similar to FIMD and Exynos5433's DECON, the Exynos7 DECON hardware:
- May optionally require an IOMMU to initialize a display region.
- Outputs image data to another block, say an MIC or a DSI master.
If an IOMMU is present, it may also require to access the reserved
framebuffer region.
Document these bindings in the devicetree schema.
Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Add compatible string for Exynos7870 DSIM bridge controller. The
device requires four clock sources, in schema they're named as "bus",
"pll", "byte", and "esc".
Suggested-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Resctrl subsystem can support two monitoring modes, "mbm_event" or "default".
In mbm_event mode, monitoring event can only accumulate data while it is
backed by a hardware counter. In "default" mode, resctrl assumes there is
a hardware counter for each event within every CTRL_MON and MON group.
Introduce mbm_assign_mode resctrl file to switch between mbm_event and default
modes.
Example:
To list the MBM monitor modes supported:
$ cat /sys/fs/resctrl/info/L3_MON/mbm_assign_mode
[mbm_event]
default
To enable the "mbm_event" counter assignment mode:
$ echo "mbm_event" > /sys/fs/resctrl/info/L3_MON/mbm_assign_mode
To enable the "default" monitoring mode:
$ echo "default" > /sys/fs/resctrl/info/L3_MON/mbm_assign_mode
Reset MBM event counters automatically as part of changing the mode. Clear
both architectural and non-architectural event states to prevent overflow
conditions during the next event read. Clear assignable counter configuration
on all the domains. Also, enable auto assignment when switching to "mbm_event"
mode.
Signed-off-by: Babu Moger <babu.moger@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
Link: https://lore.kernel.org/cover.1757108044.git.babu.moger@amd.com
Enable the mbm_l3_assignments resctrl file to be used to modify counter
assignments of CTRL_MON and MON groups when the "mbm_event" counter
assignment mode is enabled.
Process the assignment modifications in the following format:
<Event>:<Domain id>=<Assignment state>;<Domain id>=<Assignment state>
Event: A valid MBM event in the
/sys/fs/resctrl/info/L3_MON/event_configs directory.
Domain ID: A valid domain ID. When writing, '*' applies the changes
to all domains.
Assignment states:
_ : Unassign a counter.
e : Assign a counter exclusively.
Examples:
$ cd /sys/fs/resctrl
$ cat /sys/fs/resctrl/mbm_L3_assignments
mbm_total_bytes:0=e;1=e
mbm_local_bytes:0=e;1=e
To unassign the counter associated with the mbm_total_bytes event on
domain 0:
$ echo "mbm_total_bytes:0=_" > mbm_L3_assignments
$ cat /sys/fs/resctrl/mbm_L3_assignments
mbm_total_bytes:0=_;1=e
mbm_local_bytes:0=e;1=e
To unassign the counter associated with the mbm_total_bytes event on
all the domains:
$ echo "mbm_total_bytes:*=_" > mbm_L3_assignments
$ cat /sys/fs/resctrl/mbm_L3_assignments
mbm_total_bytes:0=_;1=_
mbm_local_bytes:0=e;1=e
Signed-off-by: Babu Moger <babu.moger@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
Link: https://lore.kernel.org/cover.1757108044.git.babu.moger@amd.com
Introduce the mbm_L3_assignments resctrl file associated with CTRL_MON and MON
resource groups to display the counter assignment states of the resource group
when "mbm_event" counter assignment mode is enabled.
Display the list in the following format:
<Event>:<Domain id>=<Assignment state>;<Domain id>=<Assignment state>
Event: A valid MBM event listed in
/sys/fs/resctrl/info/L3_MON/event_configs directory.
Domain ID: A valid domain ID.
The assignment state can be one of the following:
_ : No counter assigned.
e : Counter assigned exclusively.
Example:
To list the assignment states for the default group
$ cd /sys/fs/resctrl
$ cat /sys/fs/resctrl/mbm_L3_assignments
mbm_total_bytes:0=e;1=e
mbm_local_bytes:0=e;1=e
Signed-off-by: Babu Moger <babu.moger@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
Link: https://lore.kernel.org/cover.1757108044.git.babu.moger@amd.com
The "mbm_event" counter assignment mode allows users to assign a hardware
counter to an RMID, event pair and monitor the bandwidth as long as it is
assigned.
Introduce a user-configurable option that determines if a counter will
automatically be assigned to an RMID, event pair when its associated
monitor group is created via mkdir. Accessible when "mbm_event" counter
assignment mode is enabled.
Suggested-by: Peter Newman <peternewman@google.com>
Signed-off-by: Babu Moger <babu.moger@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
Link: https://lore.kernel.org/cover.1757108044.git.babu.moger@amd.com
When "mbm_event" counter assignment mode is enabled, users can modify the
event configuration by writing to the 'event_filter' resctrl file. The event
configurations for mbm_event mode are located in
/sys/fs/resctrl/info/L3_MON/event_configs/.
Update the assignments of all CTRL_MON and MON resource groups when the event
configuration is modified.
Example:
$ mount -t resctrl resctrl /sys/fs/resctrl
$ cd /sys/fs/resctrl/
$ cat info/L3_MON/event_configs/mbm_local_bytes/event_filter
local_reads,local_non_temporal_writes,local_reads_slow_memory
$ echo "local_reads,local_non_temporal_writes" >
info/L3_MON/event_configs/mbm_total_bytes/event_filter
$ cat info/L3_MON/event_configs/mbm_total_bytes/event_filter
local_reads,local_non_temporal_writes
Signed-off-by: Babu Moger <babu.moger@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
Link: https://lore.kernel.org/cover.1757108044.git.babu.moger@amd.com
The "mbm_event" counter assignment mode allows the user to assign a hardware
counter to an RMID, event pair and monitor the bandwidth as long as it is
assigned. The user can specify the memory transaction(s) for the counter to
track.
When this mode is supported, the /sys/fs/resctrl/info/L3_MON/event_configs
directory contains a sub-directory for each MBM event that can be assigned to
a counter. The MBM event sub-directory contains a file named "event_filter"
that is used to view and modify which memory transactions the MBM event is
configured with.
Create /sys/fs/resctrl/info/L3_MON/event_configs directory on resctrl mount
and pre-populate it with directories for the two existing MBM events:
mbm_total_bytes and mbm_local_bytes. Create the "event_filter" file within
each MBM event directory with the needed *show() that displays the memory
transactions with which the MBM event is configured.
Example:
$ mount -t resctrl resctrl /sys/fs/resctrl
$ cd /sys/fs/resctrl/
$ cat info/L3_MON/event_configs/mbm_total_bytes/event_filter
local_reads,remote_reads,local_non_temporal_writes,
remote_non_temporal_writes,local_reads_slow_memory,
remote_reads_slow_memory,dirty_victim_writes_all
$ cat info/L3_MON/event_configs/mbm_local_bytes/event_filter
local_reads,local_non_temporal_writes,local_reads_slow_memory
Signed-off-by: Babu Moger <babu.moger@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
Link: https://lore.kernel.org/cover.1757108044.git.babu.moger@amd.com
When "mbm_event" counter assignment mode is enabled, the architecture requires
a counter ID to read the event data.
Introduce an is_mbm_cntr field in struct rmid_read to indicate whether counter
assignment mode is in use.
Update the logic to call resctrl_arch_cntr_read() and resctrl_arch_reset_cntr()
when the assignment mode is active. Report 'Unassigned' in case the user attempts
to read an event without assigning a hardware counter.
Suggested-by: Reinette Chatre <reinette.chatre@intel.com>
Signed-off-by: Babu Moger <babu.moger@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
Link: https://lore.kernel.org/cover.1757108044.git.babu.moger@amd.com
The "mbm_event" counter assignment mode allows users to assign a hardware
counter to an RMID, event pair and monitor bandwidth usage as long as it is
assigned. The hardware continues to track the assigned counter until it is
explicitly unassigned by the user.
Create 'num_mbm_cntrs' resctrl file that displays the number of counters
supported in each domain. 'num_mbm_cntrs' is only visible to user space when
the system supports "mbm_event" mode.
Signed-off-by: Babu Moger <babu.moger@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
Link: https://lore.kernel.org/cover.1757108044.git.babu.moger@amd.com
Introduce the resctrl file "mbm_assign_mode" to list the supported counter
assignment modes.
The "mbm_event" counter assignment mode allows users to assign a hardware
counter to an RMID, event pair and monitor bandwidth usage as long as it is
assigned. The hardware continues to track the assigned counter until it is
explicitly unassigned by the user. Each event within a resctrl group can be
assigned independently in this mode.
On AMD systems "mbm_event" mode is backed by the ABMC (Assignable Bandwidth
Monitoring Counters) hardware feature and is enabled by default.
The "default" mode is the existing mode that works without the explicit
counter assignment, instead relying on dynamic counter assignment by hardware
that may result in hardware not dedicating a counter resulting in monitoring
data reads returning "Unavailable".
Provide an interface to display the monitor modes on the system.
$ cat /sys/fs/resctrl/info/L3_MON/mbm_assign_mode
[mbm_event]
default
Add IS_ENABLED(CONFIG_RESCTRL_ASSIGN_FIXED) check to support Arm64.
On x86, CONFIG_RESCTRL_ASSIGN_FIXED is not defined. On Arm64, it will be
defined when the "mbm_event" mode is supported.
Add IS_ENABLED(CONFIG_RESCTRL_ASSIGN_FIXED) check early to ensure the user
interface remains compatible with upcoming Arm64 support. IS_ENABLED() safely
evaluates to 0 when the configuration is not defined.
As a result, for MPAM, the display would be either:
[default]
or
[mbm_event]
Signed-off-by: Babu Moger <babu.moger@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
Link: https://lore.kernel.org/cover.1757108044.git.babu.moger@amd.com
The PWM controller on Apple's M2 Pro/Max SoCs behaves in the same way as
on previous M1 and M2 SoCs. Add its per SoC compatible.
At the same time fix the order of existing entries. The sort order logic
is having SoC numeric code families in release order, and SoCs within
each family in release order:
- t8xxx (Apple HxxP/G series, "phone"/"tablet" chips)
- t8103 (Apple H13G/M1)
- t8112 (Apple H14G/M2)
- t6xxx (Apple HxxJ series, "desktop" chips)
- t6000/t6001/t6002 (Apple H13J(S/C/D) / M1 Pro/Max/Ultra)
- t6020/t6021/t6022 (Apple H14J(S/C/D) / M2 Pro/Max/Ultra)
Note that SoCs of the t600[0-2] / t602[0-2] family share the
t6000 / t6020 compatible where the hardware is 100% compatible, which is
usually the case in this highly related set of SoCs.
Signed-off-by: Janne Grunau <j@jannau.net>
Reviewed-by: Neal Gompa <neal@gompa.dev>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250828-dt-apple-t6020-v1-20-507ba4c4b98e@jannau.net
Signed-off-by: Uwe Kleine-König <ukleinek@kernel.org>
PowerPC FW introduced HVPIPE RTAS calls such as
ibm,send-hvpipe-msg and ibm,receive-hvpipe-msg for the user space
to exchange information with different sources such as Hardware
Management Consoles (HMC).
HVPIPE_IOC_CREATE_HANDLE is defined to use /dev/papr-hvpipe
interface for ibm,send-hvpipe-msg and ibm,receive-hvpipe-msg
RTAS calls.
Also defined papr_hvpipe_hdr which will added in the payload
that is passed between the kernel and the user space.
Signed-off-by: Haren Myneni <haren@linux.ibm.com>
Tested-by: Shashank MS <shashank.gowda@in.ibm.com>
Reviewed-by: Mahesh Salgaonkar <mahesh@linux.ibm.com>
Reviewed-by: Tyrel Datwyler <tyreld@linux.ibm.com>
Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com>
Link: https://patch.msgid.link/20250909084402.1488456-2-haren@linux.ibm.com
Pull generic phy driver fixes from Vinod Koul:
- Qualcomm repeater override properties, qmp pcie bindings fix for
clocks and initialization sequence for firmware power down case
- Marvell comphy bindings clock and child node constraints
- Tegra xusb device reference leaks fix
- TI omap usb device ref leak on unbind and RGMII IS settings fix
* tag 'phy-fix-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy:
phy: qcom: qmp-pcie: Fix PHY initialization when powered down by firmware
phy: ti: gmii-sel: Always write the RGMII ID setting
dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Update pcie phy bindings
phy: ti-pipe3: fix device leak at unbind
phy: ti: omap-usb2: fix device leak at unbind
phy: tegra: xusb: fix device and OF node leak at probe
dt-bindings: phy: marvell,comphy-cp110: Fix clock and child node constraints
phy: qualcomm: phy-qcom-eusb2-repeater: fix override properties
After discussion with the devicetree maintainers we agreed to not extend
lists with the generic compatible "apple,spi" anymore [1]. Use
"apple,t8103-spi" as base compatible as it is the SoC the driver and
bindings were written for.
The SPI controller on Apple M2 Pro/Max/Ultra SoCs is compatible with
"apple,t8103-spi" so add its per-SoC compatible with the former as
fallback used by the existing driver.
[1]: https://lore.kernel.org/asahi/12ab93b7-1fc2-4ce0-926e-c8141cfe81bf@kernel.org/
Acked-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Janne Grunau <j@jannau.net>
After discussion with the devicetree maintainers we agreed to not extend
lists with the generic compatible "apple,mca" anymore [1]. Use
"apple,t8103-mca" as base compatible as it is the SoC the driver and
bindings were written for.
mca on Apple's M2 Pro/Max/Ultra SoCs is compatible with
"apple,t8103-mca" so add its per-SoC compatible with the former as
fallbeck used by the existing driver.
[1]: https://lore.kernel.org/asahi/12ab93b7-1fc2-4ce0-926e-c8141cfe81bf@kernel.org/
Acked-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Neal Gompa <neal@gompa.dev>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Janne Grunau <j@jannau.net>
