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Merge tag 'v6.17-next-dts64' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/dt

Browse Source 
mt7988 (bpi r4):
* enable network

mt7986:
* add dedicated sram node
* add interrupts for RSS to ethernet

mt7981:
* add thermal sensor and auxadc nodes

mt8395 (NIO 12L):
* enable UFS
* add gpio keys to the PMIC

mt8195:
* drop reset for PCIe device

* tag 'v6.17-next-dts64' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux:
  dt-bindings: arm: mediatek: Add grinn,genio-510-sbc
  dt-bindings: arm: mediatek: Add grinn,genio-700-sbc
  arm64: dts: mediatek: mt7988a-bpi-r4: configure switch phys and leds
  arm64: dts: mediatek: mt7988a-bpi-r4: add sfp cages and link to gmac
  arm64: dts: mediatek: mt7988a-bpi-r4: add aliases for ethernet
  arm64: dts: mediatek: mt7988: add switch node
  arm64: dts: mediatek: mt7988: add basic ethernet-nodes
  arm64: dts: mediatek: mt7986: add interrupts for RSS and interrupt names
  arm64: dts: mediatek: mt7986: add sram node
  arm64: dts: mediatek: add thermal sensor support on mt7981
  arm64: dts: mediatek: mt8395-nio-12l: add PMIC and GPIO keys support
  arm64: dts: mediatek: mt8395-nio-12l: Enable UFS
  arm64: dts: mediatek: mt8183: Fix out of range pull values
  arm64: dts: mediatek: mt8195: Remove suspend-breaking reset from pcie0

Link: https://lore.kernel.org/r/46756067-ca2f-4053-b9e9-bc6e66170b21@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2025-09-15 15:12:54 +02:00
parent 9a801e8b96 12a565af70
commit 2c58d35618
11 changed files with 508 additions and 23 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/devicetree/bindings/arm/mediatek.yaml
View File

@@ -431,11 +431,13 @@ properties:
- const: mediatek,mt8365
- items:
- enum:
- grinn,genio-510-sbc
- mediatek,mt8370-evk
- const: mediatek,mt8370
- const: mediatek,mt8188
- items:
- enum:
- grinn,genio-700-sbc
- mediatek,mt8390-evk
- const: mediatek,mt8390
- const: mediatek,mt8188

31
arch/arm64/boot/dts/mediatek/mt7981b.dtsi
View File

@@ -76,7 +76,7 @@ watchdog: watchdog@1001c000 {
#reset-cells = <1>;
};
clock-controller@1001e000 {
apmixedsys: clock-controller@1001e000 {
compatible = "mediatek,mt7981-apmixedsys";
reg = <0 0x1001e000 0 0x1000>;
#clock-cells = <1>;
@@ -184,6 +184,31 @@ spi@1100b000 {
status = "disabled";
};
thermal@1100c800 {
compatible = "mediatek,mt7981-thermal",
"mediatek,mt7986-thermal";
reg = <0 0x1100c800 0 0x800>;
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg CLK_INFRA_THERM_CK>,
<&infracfg CLK_INFRA_ADC_26M_CK>;
clock-names = "therm", "auxadc";
nvmem-cells = <&thermal_calibration>;
nvmem-cell-names = "calibration-data";
#thermal-sensor-cells = <1>;
mediatek,auxadc = <&auxadc>;
mediatek,apmixedsys = <&apmixedsys>;
};
auxadc: adc@1100d000 {
compatible = "mediatek,mt7981-auxadc",
"mediatek,mt7986-auxadc";
reg = <0 0x1100d000 0 0x1000>;
clocks = <&infracfg CLK_INFRA_ADC_26M_CK>;
clock-names = "main";
#io-channel-cells = <1>;
status = "disabled";
};
pio: pinctrl@11d00000 {
compatible = "mediatek,mt7981-pinctrl";
reg = <0 0x11d00000 0 0x1000>,
@@ -211,6 +236,10 @@ efuse@11f20000 {
reg = <0 0x11f20000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
thermal_calibration: thermal-calib@274 {
reg = <0x274 0xc>;
};
};
clock-controller@15000000 {

20
arch/arm64/boot/dts/mediatek/mt7986a.dtsi
View File

@@ -523,11 +523,17 @@ wed1: wed@15011000 {
eth: ethernet@15100000 {
compatible = "mediatek,mt7986-eth";
reg = <0 0x15100000 0 0x80000>;
reg = <0 0x15100000 0 0x40000>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "fe0", "fe1", "fe2", "fe3", "pdma0",
"pdma1", "pdma2", "pdma3";
clocks = <&ethsys CLK_ETH_FE_EN>,
<&ethsys CLK_ETH_GP2_EN>,
<&ethsys CLK_ETH_GP1_EN>,
@@ -553,6 +559,7 @@ eth: ethernet@15100000 {
<&topckgen CLK_TOP_SGM_325M_SEL>;
assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
<&apmixedsys CLK_APMIXED_SGMPLL>;
sram = <&eth_sram>;
#address-cells = <1>;
#size-cells = <0>;
mediatek,ethsys = <&ethsys>;
@@ -562,6 +569,15 @@ eth: ethernet@15100000 {
status = "disabled";
};
/*15100000+0x40000*/
eth_sram: sram@15140000 {
compatible = "mmio-sram";
reg = <0 0x15140000 0 0x40000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x15140000 0 0x40000>;
};
wo_ccif0: syscon@151a5000 {
compatible = "mediatek,mt7986-wo-ccif", "syscon";
reg = <0 0x151a5000 0 0x1000>;

11
arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts
View File

@@ -9,3 +9,14 @@ / {
model = "Banana Pi BPI-R4 (1x SFP+, 1x 2.5GbE)";
chassis-type = "embedded";
};
&gmac1 {
phy = <&int_2p5g_phy>;
phy-mode = "internal";
status = "okay";
};
&int_2p5g_phy {
pinctrl-0 = <&i2p5gbe_led0_pins>;
pinctrl-names = "i2p5gbe-led";
};

19
arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
View File

@@ -8,6 +8,25 @@ / {
compatible = "bananapi,bpi-r4", "mediatek,mt7988a";
model = "Banana Pi BPI-R4 (2x SFP+)";
chassis-type = "embedded";
/* SFP2 cage (LAN) */
sfp2: sfp2 {
compatible = "sff,sfp";
i2c-bus = <&i2c_sfp2>;
maximum-power-milliwatt = <3000>;
los-gpios = <&pio 2 GPIO_ACTIVE_HIGH>;
mod-def0-gpios = <&pio 83 GPIO_ACTIVE_LOW>;
rate-select0-gpios = <&pio 3 GPIO_ACTIVE_LOW>;
tx-disable-gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
tx-fault-gpios = <&pio 1 GPIO_ACTIVE_HIGH>;
};
};
&gmac1 {
managed = "in-band-status";
phy-mode = "usxgmii";
sfp = <&sfp2>;
};
&pca9545 {

86
arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
View File

@@ -5,10 +5,17 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/regulator/richtek,rt5190a-regulator.h>
#include <dt-bindings/leds/common.h>
#include "mt7988a.dtsi"
/ {
aliases {
ethernet0 = &gmac0;
ethernet1 = &gmac1;
ethernet2 = &gmac2;
};
chosen {
stdout-path = "serial0:115200n8";
};
@@ -58,6 +65,19 @@ reg_3p3v: regulator-3p3v {
regulator-boot-on;
regulator-always-on;
};
/* SFP1 cage (WAN) */
sfp1: sfp1 {
compatible = "sff,sfp";
i2c-bus = <&i2c_sfp1>;
maximum-power-milliwatt = <3000>;
los-gpios = <&pio 54 GPIO_ACTIVE_HIGH>;
mod-def0-gpios = <&pio 82 GPIO_ACTIVE_LOW>;
rate-select0-gpios = <&pio 21 GPIO_ACTIVE_LOW>;
tx-disable-gpios = <&pio 70 GPIO_ACTIVE_HIGH>;
tx-fault-gpios = <&pio 69 GPIO_ACTIVE_HIGH>;
};
};
&cci {
@@ -128,6 +148,72 @@ map-cpu-active-low {
};
};
&gmac2 {
managed = "in-band-status";
phy-mode = "usxgmii";
sfp = <&sfp1>;
};
&gsw_phy0 {
pinctrl-0 = <&gbe0_led0_pins>;
pinctrl-names = "gbe-led";
};
&gsw_phy0_led0 {
function = LED_FUNCTION_WAN;
color = <LED_COLOR_ID_GREEN>;
status = "okay";
};
&gsw_port0 {
label = "wan";
};
&gsw_phy1 {
pinctrl-0 = <&gbe1_led0_pins>;
pinctrl-names = "gbe-led";
};
&gsw_phy1_led0 {
function = LED_FUNCTION_LAN;
color = <LED_COLOR_ID_GREEN>;
status = "okay";
};
&gsw_port1 {
label = "lan1";
};
&gsw_phy2 {
pinctrl-0 = <&gbe2_led0_pins>;
pinctrl-names = "gbe-led";
};
&gsw_phy2_led0 {
function = LED_FUNCTION_LAN;
color = <LED_COLOR_ID_GREEN>;
status = "okay";
};
&gsw_port2 {
label = "lan2";
};
&gsw_phy3 {
pinctrl-0 = <&gbe3_led0_pins>;
pinctrl-names = "gbe-led";
};
&gsw_phy3_led0 {
function = LED_FUNCTION_LAN;
color = <LED_COLOR_ID_GREEN>;
status = "okay";
};
&gsw_port3 {
label = "lan3";
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;

285
arch/arm64/boot/dts/mediatek/mt7988a.dtsi
View File

@@ -680,7 +680,28 @@ xphyu3port0: usb-phy@11e13000 {
};
};
clock-controller@11f40000 {
xfi_tphy0: phy@11f20000 {
compatible = "mediatek,mt7988-xfi-tphy";
reg = <0 0x11f20000 0 0x10000>;
clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>,
<&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>;
clock-names = "xfipll", "topxtal";
resets = <&watchdog 14>;
mediatek,usxgmii-performance-errata;
#phy-cells = <0>;
};
xfi_tphy1: phy@11f30000 {
compatible = "mediatek,mt7988-xfi-tphy";
reg = <0 0x11f30000 0 0x10000>;
clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>,
<&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>;
clock-names = "xfipll", "topxtal";
resets = <&watchdog 15>;
#phy-cells = <0>;
};
xfi_pll: clock-controller@11f40000 {
compatible = "mediatek,mt7988-xfi-pll";
reg = <0 0x11f40000 0 0x1000>;
resets = <&watchdog 16>;
@@ -714,19 +735,277 @@ phy_calibration_p3: calib@97c {
};
};
clock-controller@15000000 {
ethsys: clock-controller@15000000 {
compatible = "mediatek,mt7988-ethsys", "syscon";
reg = <0 0x15000000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
clock-controller@15031000 {
switch: switch@15020000 {
compatible = "mediatek,mt7988-switch";
reg = <0 0x15020000 0 0x8000>;
interrupt-controller;
#interrupt-cells = <1>;
interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
resets = <&ethwarp MT7988_ETHWARP_RST_SWITCH>;
ports {
#address-cells = <1>;
#size-cells = <0>;
gsw_port0: port@0 {
reg = <0>;
phy-handle = <&gsw_phy0>;
phy-mode = "internal";
};
gsw_port1: port@1 {
reg = <1>;
phy-handle = <&gsw_phy1>;
phy-mode = "internal";
};
gsw_port2: port@2 {
reg = <2>;
phy-handle = <&gsw_phy2>;
phy-mode = "internal";
};
gsw_port3: port@3 {
reg = <3>;
phy-handle = <&gsw_phy3>;
phy-mode = "internal";
};
port@6 {
reg = <6>;
ethernet = <&gmac0>;
phy-mode = "internal";
fixed-link {
speed = <10000>;
full-duplex;
pause;
};
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
mediatek,pio = <&pio>;
gsw_phy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
interrupts = <0>;
nvmem-cells = <&phy_calibration_p0>;
nvmem-cell-names = "phy-cal-data";
leds {
#address-cells = <1>;
#size-cells = <0>;
gsw_phy0_led0: led@0 {
reg = <0>;
status = "disabled";
};
gsw_phy0_led1: led@1 {
reg = <1>;
status = "disabled";
};
};
};
gsw_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
interrupts = <1>;
nvmem-cells = <&phy_calibration_p1>;
nvmem-cell-names = "phy-cal-data";
leds {
#address-cells = <1>;
#size-cells = <0>;
gsw_phy1_led0: led@0 {
reg = <0>;
status = "disabled";
};
gsw_phy1_led1: led@1 {
reg = <1>;
status = "disabled";
};
};
};
gsw_phy2: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <2>;
interrupts = <2>;
nvmem-cells = <&phy_calibration_p2>;
nvmem-cell-names = "phy-cal-data";
leds {
#address-cells = <1>;
#size-cells = <0>;
gsw_phy2_led0: led@0 {
reg = <0>;
status = "disabled";
};
gsw_phy2_led1: led@1 {
reg = <1>;
status = "disabled";
};
};
};
gsw_phy3: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <3>;
interrupts = <3>;
nvmem-cells = <&phy_calibration_p3>;
nvmem-cell-names = "phy-cal-data";
leds {
#address-cells = <1>;
#size-cells = <0>;
gsw_phy3_led0: led@0 {
reg = <0>;
status = "disabled";
};
gsw_phy3_led1: led@1 {
reg = <1>;
status = "disabled";
};
};
};
};
};
ethwarp: clock-controller@15031000 {
compatible = "mediatek,mt7988-ethwarp";
reg = <0 0x15031000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
eth: ethernet@15100000 {
compatible = "mediatek,mt7988-eth";
reg = <0 0x15100000 0 0x40000>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "fe0", "fe1", "fe2", "fe3", "pdma0",
"pdma1", "pdma2", "pdma3";
clocks = <&ethsys CLK_ETHDMA_CRYPT0_EN>,
<&ethsys CLK_ETHDMA_FE_EN>,
<&ethsys CLK_ETHDMA_GP2_EN>,
<&ethsys CLK_ETHDMA_GP1_EN>,
<&ethsys CLK_ETHDMA_GP3_EN>,
<&ethwarp CLK_ETHWARP_WOCPU2_EN>,
<&ethwarp CLK_ETHWARP_WOCPU1_EN>,
<&ethwarp CLK_ETHWARP_WOCPU0_EN>,
<&ethsys CLK_ETHDMA_ESW_EN>,
<&topckgen CLK_TOP_ETH_GMII_SEL>,
<&topckgen CLK_TOP_ETH_REFCK_50M_SEL>,
<&topckgen CLK_TOP_ETH_SYS_200M_SEL>,
<&topckgen CLK_TOP_ETH_SYS_SEL>,
<&topckgen CLK_TOP_ETH_XGMII_SEL>,
<&topckgen CLK_TOP_ETH_MII_SEL>,
<&topckgen CLK_TOP_NETSYS_SEL>,
<&topckgen CLK_TOP_NETSYS_500M_SEL>,
<&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>,
<&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>,
<&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>,
<&topckgen CLK_TOP_NETSYS_WARP_SEL>,
<&ethsys CLK_ETHDMA_XGP1_EN>,
<&ethsys CLK_ETHDMA_XGP2_EN>,
<&ethsys CLK_ETHDMA_XGP3_EN>;
clock-names = "crypto", "fe", "gp2", "gp1", "gp3",
"ethwarp_wocpu2", "ethwarp_wocpu1",
"ethwarp_wocpu0", "esw", "top_eth_gmii_sel",
"top_eth_refck_50m_sel", "top_eth_sys_200m_sel",
"top_eth_sys_sel", "top_eth_xgmii_sel",
"top_eth_mii_sel", "top_netsys_sel",
"top_netsys_500m_sel", "top_netsys_pao_2x_sel",
"top_netsys_sync_250m_sel",
"top_netsys_ppefb_250m_sel",
"top_netsys_warp_sel","xgp1", "xgp2", "xgp3";
assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
<&topckgen CLK_TOP_NETSYS_GSW_SEL>,
<&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
<&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
<&topckgen CLK_TOP_SGM_0_SEL>,
<&topckgen CLK_TOP_SGM_1_SEL>;
assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
<&topckgen CLK_TOP_NET1PLL_D4>,
<&topckgen CLK_TOP_NET1PLL_D8_D4>,
<&topckgen CLK_TOP_NET1PLL_D8_D4>,
<&apmixedsys CLK_APMIXED_SGMPLL>,
<&apmixedsys CLK_APMIXED_SGMPLL>;
sram = <&eth_sram>;
#address-cells = <1>;
#size-cells = <0>;
mediatek,ethsys = <&ethsys>;
mediatek,infracfg = <&topmisc>;
gmac0: mac@0 {
compatible = "mediatek,eth-mac";
reg = <0>;
phy-mode = "internal";
/* Connected to internal switch */
fixed-link {
speed = <10000>;
full-duplex;
pause;
};
};
gmac1: mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
status = "disabled";
};
gmac2: mac@2 {
compatible = "mediatek,eth-mac";
reg = <2>;
status = "disabled";
};
mdio_bus: mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
/* internal 2.5G PHY */
int_2p5g_phy: ethernet-phy@15 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <15>;
};
};
};
eth_sram: sram@15400000 {
compatible = "mmio-sram";
reg = <0 0x15400000 0 0x200000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x15400000 0 0x200000>;
};
};
thermal-zones {

14
arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
View File

@@ -580,7 +580,7 @@ pins-cmd-dat {
pins-clk {
pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
drive-strength = <MTK_DRIVE_14mA>;
mediatek,pull-down-adv = <10>;
mediatek,pull-down-adv = <2>;
};
pins-rst {
@@ -609,13 +609,13 @@ pins-cmd-dat {
pins-clk {
pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
drive-strength = <MTK_DRIVE_14mA>;
mediatek,pull-down-adv = <10>;
mediatek,pull-down-adv = <2>;
};
pins-ds {
pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>;
drive-strength = <MTK_DRIVE_14mA>;
mediatek,pull-down-adv = <10>;
mediatek,pull-down-adv = <2>;
};
pins-rst {
@@ -633,13 +633,13 @@ pins-cmd-dat {
<PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
<PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
input-enable;
mediatek,pull-up-adv = <10>;
mediatek,pull-up-adv = <2>;
};
pins-clk {
pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
input-enable;
mediatek,pull-down-adv = <10>;
mediatek,pull-down-adv = <2>;
};
};
@@ -652,13 +652,13 @@ pins-cmd-dat {
<PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
drive-strength = <6>;
input-enable;
mediatek,pull-up-adv = <10>;
mediatek,pull-up-adv = <2>;
};
pins-clk {
pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
drive-strength = <8>;
mediatek,pull-down-adv = <10>;
mediatek,pull-down-adv = <2>;
input-enable;
};
};

14
arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts
View File

@@ -324,7 +324,7 @@ pins_cmd_dat {
pins_clk {
pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
drive-strength = <MTK_DRIVE_14mA>;
mediatek,pull-down-adv = <10>;
mediatek,pull-down-adv = <2>;
};
pins_rst {
@@ -353,13 +353,13 @@ pins_cmd_dat {
pins_clk {
pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
drive-strength = <MTK_DRIVE_14mA>;
mediatek,pull-down-adv = <10>;
mediatek,pull-down-adv = <2>;
};
pins_ds {
pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>;
drive-strength = <MTK_DRIVE_14mA>;
mediatek,pull-down-adv = <10>;
mediatek,pull-down-adv = <2>;
};
pins_rst {
@@ -377,13 +377,13 @@ pins_cmd_dat {
<PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
<PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
input-enable;
mediatek,pull-up-adv = <10>;
mediatek,pull-up-adv = <2>;
};
pins_clk {
pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
input-enable;
mediatek,pull-down-adv = <10>;
mediatek,pull-down-adv = <2>;
};
pins_pmu {
@@ -401,13 +401,13 @@ pins_cmd_dat {
<PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
drive-strength = <6>;
input-enable;
mediatek,pull-up-adv = <10>;
mediatek,pull-up-adv = <2>;
};
pins_clk {
pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
drive-strength = <8>;
mediatek,pull-down-adv = <10>;
mediatek,pull-down-adv = <2>;
input-enable;
};
};

3
arch/arm64/boot/dts/mediatek/mt8195.dtsi
View File

@@ -1588,9 +1588,6 @@ pcie0: pcie@112f0000 {
power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>;
resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P0_SWRST>;
reset-names = "mac";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc0 0>,

46
arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts
View File

@@ -8,6 +8,7 @@
#include "mt8195.dtsi"
#include "mt6359.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
#include <dt-bindings/regulator/mediatek,mt6360-regulator.h>
@@ -60,6 +61,18 @@ backlight: backlight {
status = "disabled";
};
keys: gpio-keys {
compatible = "gpio-keys";
button-volume-up {
wakeup-source;
debounce-interval = <100>;
gpios = <&pio 106 GPIO_ACTIVE_LOW>;
label = "volume_up";
linux,code = <KEY_VOLUMEUP>;
};
};
wifi_vreg: regulator-wifi-3v3-en {
compatible = "regulator-fixed";
regulator-name = "wifi_3v3_en";
@@ -626,6 +639,14 @@ pins-txd {
};
};
gpio_key_pins: gpio-keys-pins {
pins {
pinmux = <PINMUX_GPIO106__FUNC_GPIO106>;
bias-pull-up;
input-enable;
};
};
i2c2_pins: i2c2-pins {
pins-bus {
pinmux = <PINMUX_GPIO12__FUNC_SDA2>,
@@ -880,6 +901,21 @@ &pciephy {
&pmic {
interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
mt6359keys: keys {
compatible = "mediatek,mt6359-keys";
mediatek,long-press-mode = <1>;
power-off-time-sec = <0>;
power-key {
linux,keycodes = <KEY_POWER>;
wakeup-source;
};
home {
linux,keycodes = <KEY_HOME>;
};
};
};
&scp {
@@ -990,6 +1026,16 @@ &uart1 {
status = "okay";
};
&ufshci {
vcc-supply = <&mt6359_vemc_1_ldo_reg>;
vccq2-supply = <&mt6359_vufs_ldo_reg>;
status = "okay";
};
&ufsphy {
status = "okay";
};
&ssusb0 {
pinctrl-names = "default";
pinctrl-0 = <&usb3_port0_pins>;