From 3374b5fb26b300809ecd6aed9f414987dd17c313 Mon Sep 17 00:00:00 2001 From: Guoqing Jiang Date: Mon, 21 Jul 2025 17:59:59 +0800 Subject: [PATCH 01/14] arm64: dts: mediatek: mt8195: Remove suspend-breaking reset from pcie0 When test suspend resume with 6.8 based kernel, system can't resume and I got below error which can be also reproduced with 6.16 rc6+ kernel. mtk-pcie-gen3 112f0000.pcie: PCIe link down, current LTSSM state: detect.quiet (0x0) mtk-pcie-gen3 112f0000.pcie: PM: dpm_run_callback(): genpd_resume_noirq returns -110 mtk-pcie-gen3 112f0000.pcie: PM: failed to resume noirq: error -110 After investigation, looks pcie0 has the same problem as pcie1 as decribed in commit 3d7fdd8e38aa ("arm64: dts: mediatek: mt8195: Remove suspend-breaking reset from pcie1"). Fixes: ecc0af6a3fe6 ("arm64: dts: mt8195: Add pcie and pcie phy nodes") Signed-off-by: Guoqing Jiang Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Macpaul Lin Link: https://lore.kernel.org/r/20250721095959.57703-1-guoqing.jiang@canonical.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 8877953ce292..ab0b2f606eb4 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1588,9 +1588,6 @@ pcie0: pcie@112f0000 { power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>; - resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P0_SWRST>; - reset-names = "mac"; - #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0 0 0 1 &pcie_intc0 0>, From 0aeb7ed4bcb244862a35f880053cd64d28c6fb04 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Tue, 22 Jul 2025 12:11:52 -0500 Subject: [PATCH 02/14] arm64: dts: mediatek: mt8183: Fix out of range pull values A value of 10 is not valid for "mediatek,pull-down-adv" and "mediatek,pull-up-adv" properties which have defined values of 0-3. It appears the "10" was written as a binary value. The driver only looks at the lowest 2 bits, so the value "10" decimal works out the same as if "2" was used. Fixes: cd894e274b74 ("arm64: dts: mt8183: Add krane-sku176 board") Fixes: 19b6403f1e2a ("arm64: dts: mt8183: add mt8183 pumpkin board") Signed-off-by: Rob Herring (Arm) Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20250722171152.58923-2-robh@kernel.org Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 14 +++++++------- arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts | 14 +++++++------- 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index 400c61d11035..fff93e26eb76 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -580,7 +580,7 @@ pins-cmd-dat { pins-clk { pinmux = ; drive-strength = ; - mediatek,pull-down-adv = <10>; + mediatek,pull-down-adv = <2>; }; pins-rst { @@ -609,13 +609,13 @@ pins-cmd-dat { pins-clk { pinmux = ; drive-strength = ; - mediatek,pull-down-adv = <10>; + mediatek,pull-down-adv = <2>; }; pins-ds { pinmux = ; drive-strength = ; - mediatek,pull-down-adv = <10>; + mediatek,pull-down-adv = <2>; }; pins-rst { @@ -633,13 +633,13 @@ pins-cmd-dat { , ; input-enable; - mediatek,pull-up-adv = <10>; + mediatek,pull-up-adv = <2>; }; pins-clk { pinmux = ; input-enable; - mediatek,pull-down-adv = <10>; + mediatek,pull-down-adv = <2>; }; }; @@ -652,13 +652,13 @@ pins-cmd-dat { ; drive-strength = <6>; input-enable; - mediatek,pull-up-adv = <10>; + mediatek,pull-up-adv = <2>; }; pins-clk { pinmux = ; drive-strength = <8>; - mediatek,pull-down-adv = <10>; + mediatek,pull-down-adv = <2>; input-enable; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts index dbdee604edab..7c3010889ae7 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts @@ -324,7 +324,7 @@ pins_cmd_dat { pins_clk { pinmux = ; drive-strength = ; - mediatek,pull-down-adv = <10>; + mediatek,pull-down-adv = <2>; }; pins_rst { @@ -353,13 +353,13 @@ pins_cmd_dat { pins_clk { pinmux = ; drive-strength = ; - mediatek,pull-down-adv = <10>; + mediatek,pull-down-adv = <2>; }; pins_ds { pinmux = ; drive-strength = ; - mediatek,pull-down-adv = <10>; + mediatek,pull-down-adv = <2>; }; pins_rst { @@ -377,13 +377,13 @@ pins_cmd_dat { , ; input-enable; - mediatek,pull-up-adv = <10>; + mediatek,pull-up-adv = <2>; }; pins_clk { pinmux = ; input-enable; - mediatek,pull-down-adv = <10>; + mediatek,pull-down-adv = <2>; }; pins_pmu { @@ -401,13 +401,13 @@ pins_cmd_dat { ; drive-strength = <6>; input-enable; - mediatek,pull-up-adv = <10>; + mediatek,pull-up-adv = <2>; }; pins_clk { pinmux = ; drive-strength = <8>; - mediatek,pull-down-adv = <10>; + mediatek,pull-down-adv = <2>; input-enable; }; }; From d22e9b8c96452ae0fead5e26651be66fe298100e Mon Sep 17 00:00:00 2001 From: Julien Massot Date: Fri, 5 Sep 2025 15:21:19 +0200 Subject: [PATCH 03/14] arm64: dts: mediatek: mt8395-nio-12l: Enable UFS UFS is the primary storage for the Radxa NIO 12L. Enable it now that the ufshci and ufsphy nodes are available in the common mt8195 dtsi. Signed-off-by: Julien Massot Link: https://lore.kernel.org/r/20250905-radxa-nio-12l-ufs-v1-1-e2468bfd2c69@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts index 329c60cc6a6b..4cbd78c126f6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts +++ b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts @@ -990,6 +990,16 @@ &uart1 { status = "okay"; }; +&ufshci { + vcc-supply = <&mt6359_vemc_1_ldo_reg>; + vccq2-supply = <&mt6359_vufs_ldo_reg>; + status = "okay"; +}; + +&ufsphy { + status = "okay"; +}; + &ssusb0 { pinctrl-names = "default"; pinctrl-0 = <&usb3_port0_pins>; From 1383007f85fbb06aac5061b756b1ae4e701fef59 Mon Sep 17 00:00:00 2001 From: Julien Massot Date: Fri, 5 Sep 2025 13:51:59 +0200 Subject: [PATCH 04/14] arm64: dts: mediatek: mt8395-nio-12l: add PMIC and GPIO keys support Add support for PMIC and GPIO keys on the Radxa NIO 12L board: Declare a gpio-keys node for the Volume Up button using GPIO106. Add the corresponding pin configuration in the pinctrl node. Add a mediatek,mt6359-keys subnode under the PMIC to handle the power and home buttons exposed by the MT6359. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Julien Massot Link: https://lore.kernel.org/r/20250905-radxa-nio-12-l-gpio-v3-2-40f11377fb55@collabora.com Signed-off-by: Matthias Brugger --- .../dts/mediatek/mt8395-radxa-nio-12l.dts | 36 +++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts index 4cbd78c126f6..d32f973f5e05 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts +++ b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts @@ -8,6 +8,7 @@ #include "mt8195.dtsi" #include "mt6359.dtsi" #include +#include #include #include #include @@ -60,6 +61,18 @@ backlight: backlight { status = "disabled"; }; + keys: gpio-keys { + compatible = "gpio-keys"; + + button-volume-up { + wakeup-source; + debounce-interval = <100>; + gpios = <&pio 106 GPIO_ACTIVE_LOW>; + label = "volume_up"; + linux,code = ; + }; + }; + wifi_vreg: regulator-wifi-3v3-en { compatible = "regulator-fixed"; regulator-name = "wifi_3v3_en"; @@ -626,6 +639,14 @@ pins-txd { }; }; + gpio_key_pins: gpio-keys-pins { + pins { + pinmux = ; + bias-pull-up; + input-enable; + }; + }; + i2c2_pins: i2c2-pins { pins-bus { pinmux = , @@ -880,6 +901,21 @@ &pciephy { &pmic { interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; + + mt6359keys: keys { + compatible = "mediatek,mt6359-keys"; + mediatek,long-press-mode = <1>; + power-off-time-sec = <0>; + + power-key { + linux,keycodes = ; + wakeup-source; + }; + + home { + linux,keycodes = ; + }; + }; }; &scp { From 0da6f7a0ab5322eb6d091a9c89d799adfeae078d Mon Sep 17 00:00:00 2001 From: Aleksander Jan Bajkowski Date: Sun, 7 Sep 2025 13:15:09 +0200 Subject: [PATCH 05/14] arm64: dts: mediatek: add thermal sensor support on mt7981 The temperature sensor in the MT7981 is same as in the MT7986. Signed-off-by: Aleksander Jan Bajkowski Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20250907111742.23195-2-olek2@wp.pl Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt7981b.dtsi | 31 ++++++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi index 5cbea9cd411f..277c11247c13 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi @@ -76,7 +76,7 @@ watchdog: watchdog@1001c000 { #reset-cells = <1>; }; - clock-controller@1001e000 { + apmixedsys: clock-controller@1001e000 { compatible = "mediatek,mt7981-apmixedsys"; reg = <0 0x1001e000 0 0x1000>; #clock-cells = <1>; @@ -184,6 +184,31 @@ spi@1100b000 { status = "disabled"; }; + thermal@1100c800 { + compatible = "mediatek,mt7981-thermal", + "mediatek,mt7986-thermal"; + reg = <0 0x1100c800 0 0x800>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_THERM_CK>, + <&infracfg CLK_INFRA_ADC_26M_CK>; + clock-names = "therm", "auxadc"; + nvmem-cells = <&thermal_calibration>; + nvmem-cell-names = "calibration-data"; + #thermal-sensor-cells = <1>; + mediatek,auxadc = <&auxadc>; + mediatek,apmixedsys = <&apmixedsys>; + }; + + auxadc: adc@1100d000 { + compatible = "mediatek,mt7981-auxadc", + "mediatek,mt7986-auxadc"; + reg = <0 0x1100d000 0 0x1000>; + clocks = <&infracfg CLK_INFRA_ADC_26M_CK>; + clock-names = "main"; + #io-channel-cells = <1>; + status = "disabled"; + }; + pio: pinctrl@11d00000 { compatible = "mediatek,mt7981-pinctrl"; reg = <0 0x11d00000 0 0x1000>, @@ -211,6 +236,10 @@ efuse@11f20000 { reg = <0 0x11f20000 0 0x1000>; #address-cells = <1>; #size-cells = <1>; + + thermal_calibration: thermal-calib@274 { + reg = <0x274 0xc>; + }; }; clock-controller@15000000 { From d0c970091abf11805cb629f20760c0e67eb73f82 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Wed, 9 Jul 2025 13:09:43 +0200 Subject: [PATCH 06/14] arm64: dts: mediatek: mt7986: add sram node Currently sram is allocated in driver via offset from reg of ethernet node. Change it to use a dedicated sram node like mt7988. Signed-off-by: Frank Wunderlich Link: https://lore.kernel.org/r/20250709111147.11843-8-linux@fw-web.de Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi index 559990dcd1d1..550f569451fb 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -523,7 +523,7 @@ wed1: wed@15011000 { eth: ethernet@15100000 { compatible = "mediatek,mt7986-eth"; - reg = <0 0x15100000 0 0x80000>; + reg = <0 0x15100000 0 0x40000>; interrupts = , , , @@ -553,6 +553,7 @@ eth: ethernet@15100000 { <&topckgen CLK_TOP_SGM_325M_SEL>; assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>, <&apmixedsys CLK_APMIXED_SGMPLL>; + sram = <ð_sram>; #address-cells = <1>; #size-cells = <0>; mediatek,ethsys = <ðsys>; @@ -562,6 +563,15 @@ eth: ethernet@15100000 { status = "disabled"; }; + /*15100000+0x40000*/ + eth_sram: sram@15140000 { + compatible = "mmio-sram"; + reg = <0 0x15140000 0 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x15140000 0 0x40000>; + }; + wo_ccif0: syscon@151a5000 { compatible = "mediatek,mt7986-wo-ccif", "syscon"; reg = <0 0x151a5000 0 0x1000>; From 93e435336ab4bfb115e546e5a31b895b1ce0b83d Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Wed, 9 Jul 2025 13:09:44 +0200 Subject: [PATCH 07/14] arm64: dts: mediatek: mt7986: add interrupts for RSS and interrupt names Add interrupts for RSS/LRO and names to access them via name instead of index. Signed-off-by: Frank Wunderlich Link: https://lore.kernel.org/r/20250709111147.11843-9-linux@fw-web.de Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi index 550f569451fb..a9e079fd42c6 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -527,7 +527,13 @@ eth: ethernet@15100000 { interrupts = , , , - ; + , + , + , + , + ; + interrupt-names = "fe0", "fe1", "fe2", "fe3", "pdma0", + "pdma1", "pdma2", "pdma3"; clocks = <ðsys CLK_ETH_FE_EN>, <ðsys CLK_ETH_GP2_EN>, <ðsys CLK_ETH_GP1_EN>, From 65f0e3970143ec5d24271a51e0bc8c0588383280 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Wed, 9 Jul 2025 13:09:45 +0200 Subject: [PATCH 08/14] arm64: dts: mediatek: mt7988: add basic ethernet-nodes Add basic ethernet related nodes. Mac1+2 needs pcs (sgmii+usxgmii) to work correctly which will be linked later when driver is merged. Signed-off-by: Daniel Golle Signed-off-by: Frank Wunderlich Link: https://lore.kernel.org/r/20250709111147.11843-10-linux@fw-web.de Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 137 +++++++++++++++++++++- 1 file changed, 134 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index 560ec86dbec0..897b5a82b53e 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -680,7 +680,28 @@ xphyu3port0: usb-phy@11e13000 { }; }; - clock-controller@11f40000 { + xfi_tphy0: phy@11f20000 { + compatible = "mediatek,mt7988-xfi-tphy"; + reg = <0 0x11f20000 0 0x10000>; + clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, + <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>; + clock-names = "xfipll", "topxtal"; + resets = <&watchdog 14>; + mediatek,usxgmii-performance-errata; + #phy-cells = <0>; + }; + + xfi_tphy1: phy@11f30000 { + compatible = "mediatek,mt7988-xfi-tphy"; + reg = <0 0x11f30000 0 0x10000>; + clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, + <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>; + clock-names = "xfipll", "topxtal"; + resets = <&watchdog 15>; + #phy-cells = <0>; + }; + + xfi_pll: clock-controller@11f40000 { compatible = "mediatek,mt7988-xfi-pll"; reg = <0 0x11f40000 0 0x1000>; resets = <&watchdog 16>; @@ -714,19 +735,129 @@ phy_calibration_p3: calib@97c { }; }; - clock-controller@15000000 { + ethsys: clock-controller@15000000 { compatible = "mediatek,mt7988-ethsys", "syscon"; reg = <0 0x15000000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; }; - clock-controller@15031000 { + ethwarp: clock-controller@15031000 { compatible = "mediatek,mt7988-ethwarp"; reg = <0 0x15031000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; }; + + eth: ethernet@15100000 { + compatible = "mediatek,mt7988-eth"; + reg = <0 0x15100000 0 0x40000>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "fe0", "fe1", "fe2", "fe3", "pdma0", + "pdma1", "pdma2", "pdma3"; + clocks = <ðsys CLK_ETHDMA_CRYPT0_EN>, + <ðsys CLK_ETHDMA_FE_EN>, + <ðsys CLK_ETHDMA_GP2_EN>, + <ðsys CLK_ETHDMA_GP1_EN>, + <ðsys CLK_ETHDMA_GP3_EN>, + <ðwarp CLK_ETHWARP_WOCPU2_EN>, + <ðwarp CLK_ETHWARP_WOCPU1_EN>, + <ðwarp CLK_ETHWARP_WOCPU0_EN>, + <ðsys CLK_ETHDMA_ESW_EN>, + <&topckgen CLK_TOP_ETH_GMII_SEL>, + <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>, + <&topckgen CLK_TOP_ETH_SYS_200M_SEL>, + <&topckgen CLK_TOP_ETH_SYS_SEL>, + <&topckgen CLK_TOP_ETH_XGMII_SEL>, + <&topckgen CLK_TOP_ETH_MII_SEL>, + <&topckgen CLK_TOP_NETSYS_SEL>, + <&topckgen CLK_TOP_NETSYS_500M_SEL>, + <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>, + <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>, + <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>, + <&topckgen CLK_TOP_NETSYS_WARP_SEL>, + <ðsys CLK_ETHDMA_XGP1_EN>, + <ðsys CLK_ETHDMA_XGP2_EN>, + <ðsys CLK_ETHDMA_XGP3_EN>; + clock-names = "crypto", "fe", "gp2", "gp1", "gp3", + "ethwarp_wocpu2", "ethwarp_wocpu1", + "ethwarp_wocpu0", "esw", "top_eth_gmii_sel", + "top_eth_refck_50m_sel", "top_eth_sys_200m_sel", + "top_eth_sys_sel", "top_eth_xgmii_sel", + "top_eth_mii_sel", "top_netsys_sel", + "top_netsys_500m_sel", "top_netsys_pao_2x_sel", + "top_netsys_sync_250m_sel", + "top_netsys_ppefb_250m_sel", + "top_netsys_warp_sel","xgp1", "xgp2", "xgp3"; + assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>, + <&topckgen CLK_TOP_NETSYS_GSW_SEL>, + <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>, + <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>, + <&topckgen CLK_TOP_SGM_0_SEL>, + <&topckgen CLK_TOP_SGM_1_SEL>; + assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>, + <&topckgen CLK_TOP_NET1PLL_D4>, + <&topckgen CLK_TOP_NET1PLL_D8_D4>, + <&topckgen CLK_TOP_NET1PLL_D8_D4>, + <&apmixedsys CLK_APMIXED_SGMPLL>, + <&apmixedsys CLK_APMIXED_SGMPLL>; + sram = <ð_sram>; + #address-cells = <1>; + #size-cells = <0>; + mediatek,ethsys = <ðsys>; + mediatek,infracfg = <&topmisc>; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "internal"; + + /* Connected to internal switch */ + fixed-link { + speed = <10000>; + full-duplex; + pause; + }; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + status = "disabled"; + }; + + gmac2: mac@2 { + compatible = "mediatek,eth-mac"; + reg = <2>; + status = "disabled"; + }; + + mdio_bus: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + /* internal 2.5G PHY */ + int_2p5g_phy: ethernet-phy@15 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <15>; + }; + }; + }; + + eth_sram: sram@15400000 { + compatible = "mmio-sram"; + reg = <0 0x15400000 0 0x200000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x15400000 0 0x200000>; + }; }; thermal-zones { From 32d5a82c5dd60f3f5e34cade74f92f0604cda096 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Wed, 9 Jul 2025 13:09:46 +0200 Subject: [PATCH 09/14] arm64: dts: mediatek: mt7988: add switch node Add mt7988 builtin mt753x switch nodes. Signed-off-by: Daniel Golle Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20250709111147.11843-11-linux@fw-web.de Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 148 ++++++++++++++++++++++ 1 file changed, 148 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index 897b5a82b53e..366203a72d6d 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -742,6 +742,154 @@ ethsys: clock-controller@15000000 { #reset-cells = <1>; }; + switch: switch@15020000 { + compatible = "mediatek,mt7988-switch"; + reg = <0 0x15020000 0 0x8000>; + interrupt-controller; + #interrupt-cells = <1>; + interrupts = ; + resets = <ðwarp MT7988_ETHWARP_RST_SWITCH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + gsw_port0: port@0 { + reg = <0>; + phy-handle = <&gsw_phy0>; + phy-mode = "internal"; + }; + + gsw_port1: port@1 { + reg = <1>; + phy-handle = <&gsw_phy1>; + phy-mode = "internal"; + }; + + gsw_port2: port@2 { + reg = <2>; + phy-handle = <&gsw_phy2>; + phy-mode = "internal"; + }; + + gsw_port3: port@3 { + reg = <3>; + phy-handle = <&gsw_phy3>; + phy-mode = "internal"; + }; + + port@6 { + reg = <6>; + ethernet = <&gmac0>; + phy-mode = "internal"; + + fixed-link { + speed = <10000>; + full-duplex; + pause; + }; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + mediatek,pio = <&pio>; + + gsw_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + interrupts = <0>; + nvmem-cells = <&phy_calibration_p0>; + nvmem-cell-names = "phy-cal-data"; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + gsw_phy0_led0: led@0 { + reg = <0>; + status = "disabled"; + }; + + gsw_phy0_led1: led@1 { + reg = <1>; + status = "disabled"; + }; + }; + }; + + gsw_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + interrupts = <1>; + nvmem-cells = <&phy_calibration_p1>; + nvmem-cell-names = "phy-cal-data"; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + gsw_phy1_led0: led@0 { + reg = <0>; + status = "disabled"; + }; + + gsw_phy1_led1: led@1 { + reg = <1>; + status = "disabled"; + }; + }; + }; + + gsw_phy2: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + interrupts = <2>; + nvmem-cells = <&phy_calibration_p2>; + nvmem-cell-names = "phy-cal-data"; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + gsw_phy2_led0: led@0 { + reg = <0>; + status = "disabled"; + }; + + gsw_phy2_led1: led@1 { + reg = <1>; + status = "disabled"; + }; + }; + }; + + gsw_phy3: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <3>; + interrupts = <3>; + nvmem-cells = <&phy_calibration_p3>; + nvmem-cell-names = "phy-cal-data"; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + gsw_phy3_led0: led@0 { + reg = <0>; + status = "disabled"; + }; + + gsw_phy3_led1: led@1 { + reg = <1>; + status = "disabled"; + }; + }; + }; + }; + }; + ethwarp: clock-controller@15031000 { compatible = "mediatek,mt7988-ethwarp"; reg = <0 0x15031000 0 0x1000>; From 0333aa8fa2d5f0dcc92afcbb38f7b286163dc0cc Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Wed, 9 Jul 2025 13:09:47 +0200 Subject: [PATCH 10/14] arm64: dts: mediatek: mt7988a-bpi-r4: add aliases for ethernet Add aliases for gmacs to allow bootloader setting mac-adresses. Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20250709111147.11843-12-linux@fw-web.de Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi index 5fd222df440d..6a62da34a51e 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi @@ -9,6 +9,12 @@ #include "mt7988a.dtsi" / { + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; + ethernet2 = &gmac2; + }; + chosen { stdout-path = "serial0:115200n8"; }; From c1347c688bf1889ba9e974a828f1f0f26717cd04 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Wed, 9 Jul 2025 13:09:48 +0200 Subject: [PATCH 11/14] arm64: dts: mediatek: mt7988a-bpi-r4: add sfp cages and link to gmac Add SFP cages to Bananapi-R4 board. The 2.5g phy variant only contains the wan-SFP, so add this to common dtsi and the lan-sfp only to the dual-SFP variant. Signed-off-by: Daniel Golle Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20250709111147.11843-13-linux@fw-web.de Signed-off-by: Matthias Brugger --- .../mediatek/mt7988a-bananapi-bpi-r4-2g5.dts | 11 +++++++++++ .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 19 +++++++++++++++++++ .../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 19 +++++++++++++++++++ 3 files changed, 49 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts index 53de9c113f60..6f0c81e3fd94 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts +++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts @@ -9,3 +9,14 @@ / { model = "Banana Pi BPI-R4 (1x SFP+, 1x 2.5GbE)"; chassis-type = "embedded"; }; + +&gmac1 { + phy = <&int_2p5g_phy>; + phy-mode = "internal"; + status = "okay"; +}; + +&int_2p5g_phy { + pinctrl-0 = <&i2p5gbe_led0_pins>; + pinctrl-names = "i2p5gbe-led"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts index 36bd1ef2efab..4b3796ba82e3 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts @@ -8,6 +8,25 @@ / { compatible = "bananapi,bpi-r4", "mediatek,mt7988a"; model = "Banana Pi BPI-R4 (2x SFP+)"; chassis-type = "embedded"; + + /* SFP2 cage (LAN) */ + sfp2: sfp2 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp2>; + maximum-power-milliwatt = <3000>; + + los-gpios = <&pio 2 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&pio 83 GPIO_ACTIVE_LOW>; + rate-select0-gpios = <&pio 3 GPIO_ACTIVE_LOW>; + tx-disable-gpios = <&pio 0 GPIO_ACTIVE_HIGH>; + tx-fault-gpios = <&pio 1 GPIO_ACTIVE_HIGH>; + }; +}; + +&gmac1 { + managed = "in-band-status"; + phy-mode = "usxgmii"; + sfp = <&sfp2>; }; &pca9545 { diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi index 6a62da34a51e..34c1bc7f6c09 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi @@ -64,6 +64,19 @@ reg_3p3v: regulator-3p3v { regulator-boot-on; regulator-always-on; }; + + /* SFP1 cage (WAN) */ + sfp1: sfp1 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp1>; + maximum-power-milliwatt = <3000>; + + los-gpios = <&pio 54 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&pio 82 GPIO_ACTIVE_LOW>; + rate-select0-gpios = <&pio 21 GPIO_ACTIVE_LOW>; + tx-disable-gpios = <&pio 70 GPIO_ACTIVE_HIGH>; + tx-fault-gpios = <&pio 69 GPIO_ACTIVE_HIGH>; + }; }; &cci { @@ -134,6 +147,12 @@ map-cpu-active-low { }; }; +&gmac2 { + managed = "in-band-status"; + phy-mode = "usxgmii"; + sfp = <&sfp1>; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; From 16c1f659860be36541ab89c2cfd3674fbe706cd7 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Wed, 9 Jul 2025 13:09:49 +0200 Subject: [PATCH 12/14] arm64: dts: mediatek: mt7988a-bpi-r4: configure switch phys and leds Assign pinctrl to switch phys and leds. Signed-off-by: Daniel Golle Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20250709111147.11843-14-linux@fw-web.de Signed-off-by: Matthias Brugger --- .../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 61 +++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi index 34c1bc7f6c09..0ff69dae45d3 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi @@ -5,6 +5,7 @@ #include #include #include +#include #include "mt7988a.dtsi" @@ -153,6 +154,66 @@ &gmac2 { sfp = <&sfp1>; }; +&gsw_phy0 { + pinctrl-0 = <&gbe0_led0_pins>; + pinctrl-names = "gbe-led"; +}; + +&gsw_phy0_led0 { + function = LED_FUNCTION_WAN; + color = ; + status = "okay"; +}; + +&gsw_port0 { + label = "wan"; +}; + +&gsw_phy1 { + pinctrl-0 = <&gbe1_led0_pins>; + pinctrl-names = "gbe-led"; +}; + +&gsw_phy1_led0 { + function = LED_FUNCTION_LAN; + color = ; + status = "okay"; +}; + +&gsw_port1 { + label = "lan1"; +}; + +&gsw_phy2 { + pinctrl-0 = <&gbe2_led0_pins>; + pinctrl-names = "gbe-led"; +}; + +&gsw_phy2_led0 { + function = LED_FUNCTION_LAN; + color = ; + status = "okay"; +}; + +&gsw_port2 { + label = "lan2"; +}; + +&gsw_phy3 { + pinctrl-0 = <&gbe3_led0_pins>; + pinctrl-names = "gbe-led"; +}; + +&gsw_phy3_led0 { + function = LED_FUNCTION_LAN; + color = ; + status = "okay"; +}; + +&gsw_port3 { + label = "lan3"; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; From 930b6fe1a50c7ba69608230322614c87ea3dd35e Mon Sep 17 00:00:00 2001 From: Mateusz Koza Date: Mon, 8 Sep 2025 15:05:35 +0200 Subject: [PATCH 13/14] dt-bindings: arm: mediatek: Add grinn,genio-700-sbc Add device tree bindings support for the Grinn GenioSBC-700, a single-board computer based on the MediaTek Genio 700 SoC. More details about the hardware: - https://grinn-global.com/products/grinn-geniosom-700 - https://grinn-global.com/products/grinn-genioboard-edge-ai-sbc Acked-by: Conor Dooley Signed-off-by: Mateusz Koza Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20250908130620.2309399-3-mateusz.koza@grinn-global.com Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/arm/mediatek.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 19ed9448c9c2..448241939a75 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -436,6 +436,7 @@ properties: - const: mediatek,mt8188 - items: - enum: + - grinn,genio-700-sbc - mediatek,mt8390-evk - const: mediatek,mt8390 - const: mediatek,mt8188 From 12a565af705542c4380e95f4e3a505a2c25ad754 Mon Sep 17 00:00:00 2001 From: Mateusz Koza Date: Mon, 8 Sep 2025 15:05:37 +0200 Subject: [PATCH 14/14] dt-bindings: arm: mediatek: Add grinn,genio-510-sbc Add device tree bindings support for the Grinn GenioSBC-510, a single-board computer based on the MediaTek Genio 510 SoC. More details about the hardware: - https://grinn-global.com/products/grinn-geniosom-510 - https://grinn-global.com/products/grinn-genioboard-edge-ai-sbc Acked-by: Conor Dooley Signed-off-by: Mateusz Koza Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20250908130620.2309399-5-mateusz.koza@grinn-global.com Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/arm/mediatek.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 448241939a75..f04277873694 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -431,6 +431,7 @@ properties: - const: mediatek,mt8365 - items: - enum: + - grinn,genio-510-sbc - mediatek,mt8370-evk - const: mediatek,mt8370 - const: mediatek,mt8188