Yunhui Cui
a3313375e8
riscv: print hartid on bringup
...
Firmware randomly releases cores, so CPU numbers don't linearly map
to hartids. When the system has an exception, we care more about hartids.
Adding "dyndbg="file smpboot.c +p" loglevel=8" to the cmdline can output
the hartid.
Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com >
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com >
Link: https://lore.kernel.org/r/20250303083424.14309-1-cuiyunhui@bytedance.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com >
2025-04-01 07:03:03 +00:00
Alexandre Ghiti
74f4bf9d15
Merge patch series "riscv: Add runtime constant support"
...
Charlie Jenkins <charlie@rivosinc.com > says:
Ard brought this to my attention in this patch [1].
I benchmarked this patch on the Nezha D1 (which does not contain Zba or
Zbkb so it uses the default algorithm) by navigating through a large
directory structure. I created a 1000-deep directory structure and then
cd and ls through it. With this patch there was a 0.57% performance
improvement.
[1] https://lore.kernel.org/lkml/CAMj1kXE4DJnwFejNWQu784GvyJO=aGNrzuLjSxiowX_e7nW8QA@mail.gmail.com/
* patches from https://lore.kernel.org/r/20250319-runtime_const_riscv-v10-0-745b31a11d65@rivosinc.com :
riscv: Add runtime constant support
riscv: Move nop definition to insn-def.h
Link: https://lore.kernel.org/linux-riscv/20250319-runtime_const_riscv-v10-0-745b31a11d65@rivosinc.com/
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com >
2025-03-20 09:15:04 +00:00
Charlie Jenkins
a44fb57221
riscv: Add runtime constant support
...
Implement the runtime constant infrastructure for riscv. Use this
infrastructure to generate constants to be used by the d_hash()
function.
This is the riscv variant of commit 94a2bc0f61e3c92e8171charlie@rivosinc.com >
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com >
Tested-by: Alexandre Ghiti <alexghiti@rivosinc.com >
Link: https://lore.kernel.org/r/20250319-runtime_const_riscv-v10-2-745b31a11d65@rivosinc.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com >
2025-03-20 09:15:03 +00:00
Charlie Jenkins
afa8a93932
riscv: Move nop definition to insn-def.h
...
We have duplicated the definition of the nop instruction in ftrace.h and
in jump_label.c. Move this definition into the generic file insn-def.h
so that they can share the definition with each other and with future
files.
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com >
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com >
Tested-by: Alexandre Ghiti <alexghiti@rivosinc.com >
Reviewed-by: Andrew Jones <ajones@ventanamicro.com >
Link: https://lore.kernel.org/r/20250319-runtime_const_riscv-v10-1-745b31a11d65@rivosinc.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com >
2025-03-20 09:14:42 +00:00
Alexandre Ghiti
d9b65824d8
Merge patch series "riscv: Unaligned access speed probing fixes and skipping"
...
Andrew Jones <ajones@ventanamicro.com > says:
The first six patches of this series are fixes and cleanups of the
unaligned access speed probing code. The next patch introduces a
kernel command line option that allows the probing to be skipped.
This command line option is a different approach than Jesse's [1].
[1] takes a cpu-list for a particular speed, supporting heterogeneous
platforms. With this approach, the kernel command line should only
be used for homogeneous platforms. [1] also only allowed 'fast' and
'slow' to be selected. This parameter also supports 'unsupported',
which could be useful for testing code paths gated on that. The final
patch adds the documentation.
[1] https://lore.kernel.org/linux-riscv/20240805173816.3722002-1-jesse@rivosinc.com/
* patches from https://lore.kernel.org/r/20250304120014.143628-10-ajones@ventanamicro.com :
Documentation/kernel-parameters: Add riscv unaligned speed parameters
riscv: Add parameter for skipping access speed tests
riscv: Fix set up of vector cpu hotplug callback
riscv: Fix set up of cpu hotplug callbacks
riscv: Change check_unaligned_access_speed_all_cpus to void
riscv: Fix check_unaligned_access_all_cpus
riscv: Fix riscv_online_cpu_vec
riscv: Annotate unaligned access init functions
Link: https://lore.kernel.org/r/20250304120014.143628-10-ajones@ventanamicro.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com >
2025-03-20 07:25:24 +00:00
Andrew Jones
9fe58530a8
Documentation/kernel-parameters: Add riscv unaligned speed parameters
...
Document riscv parameters used to select scalar and vector unaligned
access speeds.
Signed-off-by: Andrew Jones <ajones@ventanamicro.com >
Link: https://lore.kernel.org/r/20250304120014.143628-18-ajones@ventanamicro.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com >
2025-03-19 14:23:31 +00:00
Andrew Jones
aecb09e091
riscv: Add parameter for skipping access speed tests
...
Allow skipping scalar and vector unaligned access speed tests. This
is useful for testing alternative code paths and to skip the tests in
environments where they run too slowly. All CPUs must have the same
unaligned access speed.
The code movement is because we now need the scalar cpu hotplug
callback to always run, so we need to bring it and its supporting
functions out of CONFIG_RISCV_PROBE_UNALIGNED_ACCESS.
Signed-off-by: Andrew Jones <ajones@ventanamicro.com >
Link: https://lore.kernel.org/r/20250304120014.143628-17-ajones@ventanamicro.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com >
2025-03-19 14:23:30 +00:00
Andrew Jones
2744ec472d
riscv: Fix set up of vector cpu hotplug callback
...
Whether or not we have RISCV_PROBE_VECTOR_UNALIGNED_ACCESS we need to
set up a cpu hotplug callback to check if we have vector at all,
since, when we don't have vector, we need to set
vector_misaligned_access to unsupported rather than leave it the
default of unknown.
Fixes: e7c9d66e31alexghiti@rivosinc.com >
Signed-off-by: Andrew Jones <ajones@ventanamicro.com >
Link: https://lore.kernel.org/r/20250304120014.143628-16-ajones@ventanamicro.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com >
2025-03-19 14:23:30 +00:00
Andrew Jones
05ee21f0fc
riscv: Fix set up of cpu hotplug callbacks
...
CPU hotplug callbacks should be set up even if we detected all
current cpus emulate misaligned accesses, since we want to
ensure our expectations of all cpus emulating is maintained.
Fixes: 6e5ce7f2eae7c9d66e31cleger@rivosinc.com >
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com >
Signed-off-by: Andrew Jones <ajones@ventanamicro.com >
Link: https://lore.kernel.org/r/20250304120014.143628-15-ajones@ventanamicro.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com >
2025-03-19 14:23:30 +00:00
Andrew Jones
813d39baee
riscv: Change check_unaligned_access_speed_all_cpus to void
...
The return value of check_unaligned_access_speed_all_cpus() is always
zero, so make the function void so we don't need to concern ourselves
with it. The change also allows us to tidy up
check_unaligned_access_all_cpus() a bit.
Reviewed-by: Clément Léger <cleger@rivosinc.com >
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com >
Signed-off-by: Andrew Jones <ajones@ventanamicro.com >
Link: https://lore.kernel.org/r/20250304120014.143628-14-ajones@ventanamicro.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com >
2025-03-19 14:23:29 +00:00
Andrew Jones
e6d0adf2eb
riscv: Fix check_unaligned_access_all_cpus
...
check_vector_unaligned_access_emulated_all_cpus(), like its name
suggests, will return true when all cpus emulate unaligned vector
accesses. If the function returned false it may have been because
vector isn't supported at all (!has_vector()) or because at least
one cpu doesn't emulate unaligned vector accesses. Since false may
be returned for two cases, checking for it isn't sufficient when
attempting to determine if we should proceed with the vector speed
check. Move the !has_vector() functionality to
check_unaligned_access_all_cpus() in order for
check_vector_unaligned_access_emulated_all_cpus() to return false
for a single case.
Fixes: e7c9d66e31alexghiti@rivosinc.com >
Signed-off-by: Andrew Jones <ajones@ventanamicro.com >
Link: https://lore.kernel.org/r/20250304120014.143628-13-ajones@ventanamicro.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com >
2025-03-19 14:23:29 +00:00
Andrew Jones
5af72a8186
riscv: Fix riscv_online_cpu_vec
...
We shouldn't probe when we already know vector is unsupported and
we should probe when we see we don't yet know whether it's supported.
Furthermore, we should ensure we've set the access type to
unsupported when we don't have vector at all.
Fixes: e7c9d66e31alexghiti@rivosinc.com >
Signed-off-by: Andrew Jones <ajones@ventanamicro.com >
Link: https://lore.kernel.org/r/20250304120014.143628-12-ajones@ventanamicro.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com >
2025-03-19 14:23:29 +00:00
Andrew Jones
a00e022be5
riscv: Annotate unaligned access init functions
...
Several functions used in unaligned access probing are only run at
init time. Annotate them appropriately.
Fixes: f413aae96calexghiti@rivosinc.com >
Signed-off-by: Andrew Jones <ajones@ventanamicro.com >
Link: https://lore.kernel.org/r/20250304120014.143628-11-ajones@ventanamicro.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com >
2025-03-19 14:23:28 +00:00
Alexandre Ghiti
5b376a68da
Merge patch series "riscv: add support for Zaamo and Zalrsc extensions"
...
Clément Léger <cleger@rivosinc.com > says:
Since commit e87412e621f1 ("integrate Zaamo and Zalrsc text (#1304 )"),
the A extension has been described as a set of instructions provided by
Zaamo and Zalrsc. Add these two extensions.
This series is based on the Zc one [1].
Link: https://lore.kernel.org/linux-riscv/20240619113529.676940-1-cleger@rivosinc.com/ [1]
* patches from https://lore.kernel.org/lkml/20240619153913.867263-1-cleger@rivosinc.com/ :
dt-bindings: riscv: add Zaamo and Zalrsc ISA extension description
riscv: add parsing for Zaamo and Zalrsc extensions
riscv: hwprobe: export Zaamo and Zalrsc extensions
RISC-V: KVM: Allow Zaamo/Zalrsc extensions for Guest/VM
KVM: riscv: selftests: Add Zaamo/Zalrsc extensions to get-reg-list
test
Link: https://lore.kernel.org/lkml/20240619153913.867263-1-cleger@rivosinc.com/
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com >
2025-03-19 12:03:47 +00:00
Clément Léger
7a9827e777
KVM: riscv: selftests: Add Zaamo/Zalrsc extensions to get-reg-list test
...
The KVM RISC-V allows Zaamo/Zalrsc extensions for Guest/VM so add these
extensions to get-reg-list test.
Signed-off-by: Clément Léger <cleger@rivosinc.com >
Reviewed-by: Anup Patel <anup@brainfault.org >
Link: https://lore.kernel.org/r/20240619153913.867263-6-cleger@rivosinc.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com >
2025-03-19 12:03:46 +00:00
Clément Léger
2d79608cf6
RISC-V: KVM: Allow Zaamo/Zalrsc extensions for Guest/VM
...
Extend the KVM ISA extension ONE_REG interface to allow KVM user space
to detect and enable Zaamo/Zalrsc extensions for Guest/VM.
Signed-off-by: Clément Léger <cleger@rivosinc.com >
Reviewed-by: Anup Patel <anup@brainfault.org >
Link: https://lore.kernel.org/r/20240619153913.867263-5-cleger@rivosinc.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com >
2025-03-19 12:03:46 +00:00
Clément Léger
9d45d1ff90
riscv: hwprobe: export Zaamo and Zalrsc extensions
...
Export the Zaamo and Zalrsc extensions to userspace using hwprobe.
Signed-off-by: Clément Léger <cleger@rivosinc.com >
Reviewed-by: Charlie Jenkins <charlie@rivosinc.com >
Link: https://lore.kernel.org/r/20240619153913.867263-4-cleger@rivosinc.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com >
2025-03-19 12:03:45 +00:00
Clément Léger
35173b666a
riscv: add parsing for Zaamo and Zalrsc extensions
...
These 2 new extensions are actually a subset of the A extension which
provides atomic memory operations and load-reserved/store-conditional
instructions.
Signed-off-by: Clément Léger <cleger@rivosinc.com >
Acked-by: Conor Dooley <conor.dooley@microchip.com >
Link: https://lore.kernel.org/r/20240619153913.867263-3-cleger@rivosinc.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com >
2025-03-19 12:03:45 +00:00
Clément Léger
a65e0f67da
dt-bindings: riscv: add Zaamo and Zalrsc ISA extension description
...
Add description for the Zaamo and Zalrsc ISA extension[1].
Link: https://github.com/riscv/riscv-zaamo-zalrsc [1]
Signed-off-by: Clément Léger <cleger@rivosinc.com >
Acked-by: Conor Dooley <conor.dooley@microchip.com >
Link: https://lore.kernel.org/r/20240619153913.867263-2-cleger@rivosinc.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com >
2025-03-19 12:03:45 +00:00
Pu Lehui
67a5ba8f74
riscv: fgraph: Fix stack layout to match __arch_ftrace_regs argument of ftrace_return_to_handler
...
Naresh Kamboju reported a "Bad frame pointer" kernel warning while
running LTP trace ftrace_stress_test.sh in riscv. We can reproduce the
same issue with the following command:
```
$ cd /sys/kernel/debug/tracing
$ echo 'f:myprobe do_nanosleep%return args1=$retval' > dynamic_events
$ echo 1 > events/fprobes/enable
$ echo 1 > tracing_on
$ sleep 1
```
And we can get the following kernel warning:
[ 127.692888] ------------[ cut here ]------------
[ 127.693755] Bad frame pointer: expected ff2000000065be50, received ba34c141e9594000
[ 127.693755] from func do_nanosleep return to ffffffff800ccb16
[ 127.698699] WARNING: CPU: 1 PID: 129 at kernel/trace/fgraph.c:755 ftrace_return_to_handler+0x1b2/0x1be
[ 127.699894] Modules linked in:
[ 127.700908] CPU: 1 UID: 0 PID: 129 Comm: sleep Not tainted 6.14.0-rc3-g0ab191c74642 #32
[ 127.701453] Hardware name: riscv-virtio,qemu (DT)
[ 127.701859] epc : ftrace_return_to_handler+0x1b2/0x1be
[ 127.702032] ra : ftrace_return_to_handler+0x1b2/0x1be
[ 127.702151] epc : ffffffff8013b5e0 ra : ffffffff8013b5e0 sp : ff2000000065bd10
[ 127.702221] gp : ffffffff819c12f8 tp : ff60000080853100 t0 : 6e00000000000000
[ 127.702284] t1 : 0000000000000020 t2 : 6e7566206d6f7266 s0 : ff2000000065bd80
[ 127.702346] s1 : ff60000081262000 a0 : 000000000000007b a1 : ffffffff81894f20
[ 127.702408] a2 : 0000000000000010 a3 : fffffffffffffffe a4 : 0000000000000000
[ 127.702470] a5 : 0000000000000000 a6 : 0000000000000008 a7 : 0000000000000038
[ 127.702530] s2 : ba34c141e9594000 s3 : 0000000000000000 s4 : ff2000000065bdd0
[ 127.702591] s5 : 00007fff8adcf400 s6 : 000055556dc1d8c0 s7 : 0000000000000068
[ 127.702651] s8 : 00007fff8adf5d10 s9 : 000000000000006d s10: 0000000000000001
[ 127.702710] s11: 00005555737377c8 t3 : ffffffff819d899e t4 : ffffffff819d899e
[ 127.702769] t5 : ffffffff819d89a0 t6 : ff2000000065bb18
[ 127.702826] status: 0000000200000120 badaddr: 0000000000000000 cause: 0000000000000003
[ 127.703292] [<ffffffff8013b5e0>] ftrace_return_to_handler+0x1b2/0x1be
[ 127.703760] [<ffffffff80017bce>] return_to_handler+0x16/0x26
[ 127.704009] [<ffffffff80017bb8>] return_to_handler+0x0/0x26
[ 127.704057] [<ffffffff800d3352>] common_nsleep+0x42/0x54
[ 127.704117] [<ffffffff800d44a2>] __riscv_sys_clock_nanosleep+0xba/0x10a
[ 127.704176] [<ffffffff80901c56>] do_trap_ecall_u+0x188/0x218
[ 127.704295] [<ffffffff8090cc3e>] handle_exception+0x14a/0x156
[ 127.705436] ---[ end trace 0000000000000000 ]---
The reason is that the stack layout for constructing argument for the
ftrace_return_to_handler in the return_to_handler does not match the
__arch_ftrace_regs structure of riscv, leading to unexpected results.
Fixes: a3ed4157b7lkft@linaro.org >
Closes: https://lore.kernel.org/all/CA+G9fYvp_oAxeDFj88Tk2rfEZ7jtYKAKSwfYS66=57Db9TBdyA@mail.gmail.com
Signed-off-by: Pu Lehui <pulehui@huawei.com >
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com >
Tested-by: Björn Töpel <bjorn@rivosinc.com >
Reviewed-by: Masami Hiramatsu (Google) <mhiramat@kernel.org >
Link: https://lore.kernel.org/r/20250317031214.4138436-2-pulehui@huaweicloud.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com >
2025-03-19 12:03:25 +00:00
Pu Lehui
e8eb8e1bda
riscv: fgraph: Select HAVE_FUNCTION_GRAPH_TRACER depends on HAVE_DYNAMIC_FTRACE_WITH_ARGS
...
Currently, fgraph on riscv relies on the infrastructure of
DYNAMIC_FTRACE_WITH_ARGS. However, DYNAMIC_FTRACE_WITH_ARGS may be
turned off on riscv, which will cause the enabled fgraph to be abnormal.
Therefore, let's select HAVE_FUNCTION_GRAPH_TRACER depends on
HAVE_DYNAMIC_FTRACE_WITH_ARGS.
Fixes: a3ed4157b7lkp@intel.com >
Closes: https://lore.kernel.org/oe-kbuild-all/202503160820.dvqMpH0g-lkp@intel.com/
Signed-off-by: Pu Lehui <pulehui@huawei.com >
Reviewed-by: Björn Töpel <bjorn@rivosinc.com >
Link: https://lore.kernel.org/r/20250317031214.4138436-1-pulehui@huaweicloud.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com >
2025-03-18 14:11:45 +00:00
Alexandre Ghiti
33981b1c4e
riscv: Fix missing __free_pages() in check_vector_unaligned_access()
...
The locally allocated pages are never freed up, so add the corresponding
__free_pages().
Fixes: e7c9d66e31https://lore.kernel.org/r/20250228090613.345309-1-alexghiti@rivosinc.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com >
2025-03-18 13:37:56 +00:00
Tingbo Liao
475afa39b1
riscv: Fix the __riscv_copy_vec_words_unaligned implementation
...
Correct the VEC_S macro definition to fix the implementation
of vector words copy in the case of unalignment in RISC-V.
Fixes: e7c9d66e31alexghiti@rivosinc.com >
Signed-off-by: Tingbo Liao <tingbo.liao@starfivetech.com >
Link: https://lore.kernel.org/r/20250228090801.8334-1-tingbo.liao@starfivetech.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com >
2025-03-18 13:37:27 +00:00
Thomas Weißschuh
eb8db421ce
riscv: mm: Don't use %pK through printk
...
Restricted pointers ("%pK") are not meant to be used through printk().
It can unintentionally expose security sensitive, raw pointer values.
Use regular pointer formatting instead.
Link: https://lore.kernel.org/lkml/20250113171731-dc10e3c1-da64-4af0-b767-7c7070468023@linutronix.de/
Signed-off-by: Thomas Weißschuh <thomas.weissschuh@linutronix.de >
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com >
Link: https://lore.kernel.org/r/20250217-restricted-pointers-riscv-v1-1-72a078076a76@linutronix.de
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com >
2025-03-18 13:35:07 +00:00
Zixian Zeng
eac5b13881
riscv: remove redundant CMDLINE_FORCE check
...
Drop redundant CMDLINE_FORCE check as it's already done in
function early_init_dt_scan_chosen().
Signed-off-by: Zixian Zeng <sycamoremoon376@gmail.com >
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com >
Link: https://lore.kernel.org/r/20250114-rebund-v1-1-5632b2d54d6c@gmail.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com >
2025-03-18 13:33:31 +00:00
Juhan Jin
5f1a58ed91
riscv: ftrace: Add parentheses in macro definitions of make_call_t0 and make_call_ra
...
This patch adds parentheses to parameters caller and callee of macros
make_call_t0 and make_call_ra. Every existing invocation of these two
macros uses a single variable for each argument, so the absence of the
parentheses seems okay. However, future invocations might use more
complex expressions as arguments. For example, a future invocation might
look like this: make_call_t0(a - b, c, call). Without parentheses in the
macro definition, the macro invocation expands to:
...
unsigned int offset = (unsigned long) c - (unsigned long) a - b;
...
which is clearly wrong.
The use of parentheses ensures arguments are correctly evaluated and
potentially saves future users of make_call_t0 and make_call_ra debugging
trouble.
Fixes: 6724a76cffjuhan.jin@foxmail.com >
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com >
Link: https://lore.kernel.org/r/tencent_AE90AA59903A628E87E9F80E563DA5BA5508@qq.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com >
2025-03-18 13:32:55 +00:00
Masahiro Yamada
82e81b8950
riscv: migrate to the generic rule for built-in DTB
...
Commit 654102df2amasahiroy@kernel.org >
Acked-by: Conor Dooley <conor.dooley@microchip.com >
Link: https://lore.kernel.org/r/20241222000836.2578171-1-masahiroy@kernel.org
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com >
2025-03-18 13:30:13 +00:00
Charlie Jenkins
bba547810c
riscv: tracing: Fix __write_overflow_field in ftrace_partial_regs()
...
The size of ®s->a0 is unknown, causing the error:
../include/linux/fortify-string.h:571:25: warning: call to
'__write_overflow_field' declared with attribute warning: detected write
beyond size of field (1st parameter); maybe use struct_group()?
[-Wattribute-warning]
Fix this by wrapping the required registers in pt_regs with
struct_group() and reference the group when doing the offending
memcpy().
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com >
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com >
Tested-by: Alexandre Ghiti <alexghiti@rivosinc.com >
Link: https://lore.kernel.org/r/20250224-fix_ftrace_partial_regs-v1-1-54b906417e86@rivosinc.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com >
2025-03-18 13:06:05 +00:00
Geert Uytterhoeven
72770690e0
riscv: Remove duplicate CLINT_TIMER selections
...
Since commit f862bbf4cdgeert+renesas@glider.be >
Reviewed-by: Conor Dooley <conor.dooley@microchip.com >
Acked-by: Conor Dooley <conor.dooley@microchip.com >
Link: https://lore.kernel.org/r/ce55529a42fa232cacd580e38866c60701f91095.1738764474.git.geert+renesas@glider.be
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com >
2025-03-18 13:05:13 +00:00
Geert Uytterhoeven
c2db83fe10
riscv: defconfig: Disable Renesas SoC support
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Follow-up to commit e36ddf3226geert+renesas@glider.be >
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com >
Link: https://lore.kernel.org/r/e8a2fb273c8c68bd6d526b924b4212f397195b28.1738764211.git.geert+renesas@glider.be
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com >
2025-03-18 13:04:25 +00:00
Chin Yik Ming
418af0eafb
riscv: Fix a comment typo in set_mm_asid()
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s/verion/version
Signed-off-by: Chin Yik Ming <yikming2222@gmail.com >
Reviewed-by: Charlie Jenkins <charlie@rivosinc.com >
Link: https://lore.kernel.org/r/20241114212725.4172401-1-yikming2222@gmail.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com >
2025-03-18 13:02:47 +00:00
Alexandre Ghiti
a5edc510da
Merge patch series "Support SSTC while PM operations"
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Nick Hu <nick.hu@sifive.com > says:
When the cpu is going to be hotplug, stop the stimecmp to prevent pending
interrupt.
When the cpu is going to be suspended, save the stimecmp before entering
the suspend state and restore it in the resume path.
* patches from https://lore.kernel.org/r/20250219114135.27764-1-nick.hu@sifive.com :
clocksource/drivers/timer-riscv: Stop stimecmp when cpu hotplug
riscv: Add stimecmp save and restore
Link: https://lore.kernel.org/r/20250219114135.27764-1-nick.hu@sifive.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com >
2025-03-18 12:59:08 +00:00
Nick Hu
70c93b026e
clocksource/drivers/timer-riscv: Stop stimecmp when cpu hotplug
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Stop the timer when the cpu is going to be offline otherwise the
timer interrupt may be pending while performing power-down.
Suggested-by: Anup Patel <anup@brainfault.org >
Link: https://lore.kernel.org/lkml/20240829033904.477200-3-nick.hu@sifive.com/T/#u
Signed-off-by: Nick Hu <nick.hu@sifive.com >
Reviewed-by: Anup Patel <anup@brainfault.org >
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org >
Link: https://lore.kernel.org/r/20250219114135.27764-3-nick.hu@sifive.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com >
2025-03-18 12:59:03 +00:00
Nick Hu
ffef54ad41
riscv: Add stimecmp save and restore
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If the HW support the SSTC extension, we should save and restore the
stimecmp register while cpu non retention suspend.
Signed-off-by: Nick Hu <nick.hu@sifive.com >
Reviewed-by: Anup Patel <anup@brainfault.org >
Link: https://lore.kernel.org/r/20250219114135.27764-2-nick.hu@sifive.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com >
2025-03-18 12:59:03 +00:00
Chin Yik Ming
7f238b1266
riscv: Simplify base extension checks and direct boolean return
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Reduce three lines checking to single line using a ternary conditional
expression for getting the base extension word. In addition, the
test_bit macro function already return a boolean which matches the
return type of the caller, so directly return the result of the test_bit
macro function.
Signed-off-by: Chin Yik Ming <yikming2222@gmail.com >
Reviewed-by: Andrew Jones <ajones@ventanamicro.com >
Link: https://lore.kernel.org/r/20250129203843.1136838-1-yikming2222@gmail.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com >
2025-03-18 12:47:20 +00:00
Jinjie Ruan
a4a58f510b
riscv: Remove unused TASK_TI_FLAGS
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Since commit f0bddf5058f0bddf5058ruanjinjie@huawei.com >
Reviewed-by: Charlie Jenkins <charlie@rivosinc.com >
Link: https://lore.kernel.org/r/20241109014605.2801492-1-ruanjinjie@huawei.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com >
2025-03-18 12:46:15 +00:00
Yunhui Cui
36dec9e448
RISC-V: selftests: Add TEST_ZICBOM into CBO tests
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Add test for Zicbom and its block size into CBO tests, when
Zicbom is present, test that cbo.clean/flush may be issued and works.
As the software can't verify the clean/flush functions, we just judged
that cbo.clean/flush isn't executed illegally.
Reviewed-by: Andrew Jones <ajones@ventanamicro.com >
Reviewed-by: Samuel Holland <samuel.holland@sifive.com >
Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com >
Link: https://lore.kernel.org/r/20250226063206.71216-4-cuiyunhui@bytedance.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com >
2025-03-18 12:44:17 +00:00
Yunhui Cui
eb10039709
RISC-V: hwprobe: Expose Zicbom extension and its block size
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Expose Zicbom through hwprobe and also provide a key to extract its
respective block size.
[ alex: Fix merge conflicts and hwprobe numbering ]
Reviewed-by: Andrew Jones <ajones@ventanamicro.com >
Reviewed-by: Samuel Holland <samuel.holland@sifive.com >
Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com >
Link: https://lore.kernel.org/r/20250226063206.71216-3-cuiyunhui@bytedance.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com >
2025-03-18 12:43:56 +00:00
Yunhui Cui
de70b532f9
RISC-V: Enable cbo.clean/flush in usermode
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Enabling cbo.clean and cbo.flush in user mode makes it more
convenient to manage the cache state and achieve better performance.
Reviewed-by: Andrew Jones <ajones@ventanamicro.com >
Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com >
Link: https://lore.kernel.org/r/20250226063206.71216-2-cuiyunhui@bytedance.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com >
2025-03-18 12:35:14 +00:00
Alexandre Ghiti
2f2cd9f334
Merge patch series "riscv: Add bfloat16 instruction support"
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Inochi Amaoto <inochiama@gmail.com > says:
Add description for the BFloat16 precision Floating-Point ISA extension,
(Zfbfmin, Zvfbfmin, Zvfbfwma). which was ratified in commit 4dc23d62
("Added Chapter title to BF16") of the riscv-isa-manual.
* patches from https://lore.kernel.org/r/20250213003849.147358-1-inochiama@gmail.com :
riscv: hwprobe: export bfloat16 ISA extension
riscv: add ISA extension parsing for bfloat16 ISA extension
dt-bindings: riscv: add bfloat16 ISA extension description
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com >
Link: https://lore.kernel.org/r/20250213003849.147358-1-inochiama@gmail.com
2025-03-18 11:52:54 +00:00
Inochi Amaoto
a4863e002c
riscv: hwprobe: export bfloat16 ISA extension
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Export Zfbmin, Zvfbfmin, Zvfbfwma ISA extension through hwprobe.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com >
Reviewed-by: Clément Léger <cleger@rivosinc.com >
Link: https://lore.kernel.org/r/20250213003849.147358-4-inochiama@gmail.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com >
2025-03-18 11:52:02 +00:00
Inochi Amaoto
e186c28dda
riscv: add ISA extension parsing for bfloat16 ISA extension
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Add parsing for Zfbmin, Zvfbfmin, Zvfbfwma ISA extension which
were ratified in 4dc23d62 ("Added Chapter title to BF16") of
the riscv-isa-manual.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com >
Reviewed-by: Clément Léger <cleger@rivosinc.com >
Link: https://lore.kernel.org/r/20250213003849.147358-3-inochiama@gmail.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com >
2025-03-18 11:52:02 +00:00
Inochi Amaoto
35bc188373
dt-bindings: riscv: add bfloat16 ISA extension description
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Add description for the BFloat16 precision Floating-Point ISA extension,
(Zfbfmin, Zvfbfmin, Zvfbfwma). which was ratified in commit 4dc23d62
("Added Chapter title to BF16") of the riscv-isa-manual.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com >
Acked-by: Conor Dooley <conor.dooley@microchip.com >
Link: https://lore.kernel.org/r/20250213003849.147358-2-inochiama@gmail.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com >
2025-03-18 11:52:02 +00:00
Guo Ren
d9708b1931
riscv: Implement smp_cond_load8/16() with Zawrs
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RISC-V code uses the queued spinlock implementation, which calls
the macros smp_cond_load_acquire for one byte. So, complement the
implementation of byte and halfword versions.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com >
Signed-off-by: Guo Ren <guoren@kernel.org >
Cc: Andrew Jones <ajones@ventanamicro.com >
Reviewed-by: Andrew Jones <ajones@ventanamicro.com >
Link: https://lore.kernel.org/r/20241217013910.1039923-1-guoren@kernel.org
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com >
2025-03-18 09:12:45 +00:00
Alexandre Ghiti
d9be2b9b60
riscv: Call secondary mmu notifier when flushing the tlb
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This is required to allow the IOMMU driver to correctly flush its own
TLB.
Reviewed-by: Clément Léger <cleger@rivosinc.com >
Reviewed-by: Samuel Holland <samuel.holland@sifive.com >
Link: https://lore.kernel.org/r/20250113142424.30487-1-alexghiti@rivosinc.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com >
2025-03-18 09:11:43 +00:00
Miquel Sabaté Solà
4458b8f68d
riscv: hwprobe: export Zicntr and Zihpm extensions
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Export Zicntr and Zihpm ISA extensions through the hwprobe syscall.
[ alex: Fix hwprobe numbering ]
Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com >
Acked-by: Jesse Taube <jesse@rivosinc.com >
Reviewed-by: Conor Dooley <conor.dooley@microchip.com >
Link: https://lore.kernel.org/r/20240913051324.8176-1-mikisabate@gmail.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com >
2025-03-18 09:10:22 +00:00
Clément Léger
d3817d091f
riscv: remove useless pc check in stacktrace handling
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Checking for pc to be a kernel text address at this location is useless
since pc == handle_exception. Remove this check.
[ alex: Fix merge conflict ]
Signed-off-by: Clément Léger <cleger@rivosinc.com >
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com >
Link: https://lore.kernel.org/r/20240830084934.3690037-1-cleger@rivosinc.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com >
2025-03-18 09:06:21 +00:00
Andrew Bresticker
03dc00a2b6
riscv: Support huge pfnmaps
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Use RSW0 as the special bit for pmds and puds, just like for ptes.
Also define the {pte,pmd,pud}_pgprot helpers which were previously
missing and are needed for the follow_pfnmap APIs.
Signed-off-by: Andrew Bresticker <abrestic@rivosinc.com >
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com >
Link: https://lore.kernel.org/r/20250108135700.2614848-1-abrestic@rivosinc.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com >
2025-03-18 08:58:42 +00:00
Alexandre Ghiti
8df0cdcc21
Merge patch series "RISC-V: clarify what some RISCV_ISA* config options do & redo Zbb toolchain dependency"
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Conor Dooley <conor@kernel.org > says:
Since one depends on the other, albeit trivially, here's a v4 of the Zbb
toolchain dep removal alongside the rewording of Kconfig options I'd
sent out before the merge window. I think I like this implementation
better than v1, but I couldn't think of a good name for a "public"
version of __ALTERNATIVE(), so I used it here directly.
Unfortunately "ALTERNATIVE_2_CFG" already exists and I couldn't think of
a good way to name an alternative macro that allows for several config
options that didn't make the distinction sufficiently clear.. Yell
if you have better suggestions than I did.
I am a wee bit "worried" that this makes the Kconfig option confusing as
it isn't immediately obvious if someone is or is not going to get the
toolchain based optimisations.
Cheers,
Conor.
* patches from https://lore.kernel.org/r/20241024-aspire-rectify-9982da6943e5@spud :
RISC-V: separate Zbb optimisations requiring and not requiring toolchain support
RISC-V: clarify what some RISCV_ISA* config options do
Link: https://lore.kernel.org/r/20241024-aspire-rectify-9982da6943e5@spud
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com >
2025-03-18 08:53:10 +00:00
Conor Dooley
9343aaba1f
RISC-V: separate Zbb optimisations requiring and not requiring toolchain support
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It seems a bit ridiculous to require toolchain support for BPF to
assemble Zbb instructions, so move the dependency on toolchain support
for Zbb optimisations out of the Kconfig option and to the callsites.
Zbb support has always depended on alternatives, so while adjusting the
config options guarding optimisations, remove any checks for
whether or not alternatives are enabled.
Reviewed-by: Andrew Jones <ajones@ventanamicro.com >
Signed-off-by: Conor Dooley <conor.dooley@microchip.com >
Reviewed-by: Charlie Jenkins <charlie@rivosinc.com >
Reviewed-by: Samuel Holland <samuel.holland@sifive.com >
Link: https://lore.kernel.org/r/20241024-chump-freebase-d26b6d81af33@spud
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com >
2025-03-18 08:53:02 +00:00
