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riscv: Implement smp_cond_load8/16() with Zawrs

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RISC-V code uses the queued spinlock implementation, which calls
the macros smp_cond_load_acquire for one byte. So, complement the
implementation of byte and halfword versions.

Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Signed-off-by: Guo Ren <guoren@kernel.org>
Cc: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Link: https://lore.kernel.org/r/20241217013910.1039923-1-guoren@kernel.org
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
This commit is contained in:
Guo Ren
2024-12-16 20:39:10 -05:00
committed by Alexandre Ghiti
parent d9be2b9b60
commit d9708b1931
1 changed files with 35 additions and 3 deletions
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38
arch/riscv/include/asm/cmpxchg.h
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@@ -365,16 +365,48 @@ static __always_inline void __cmpwait(volatile void *ptr,
{
unsigned long tmp;
u32 *__ptr32b;
ulong __s, __val, __mask;
asm goto(ALTERNATIVE("j %l[no_zawrs]", "nop",
0, RISCV_ISA_EXT_ZAWRS, 1)
: : : : no_zawrs);
switch (size) {
case 1:
fallthrough;
__ptr32b = (u32 *)((ulong)(ptr) & ~0x3);
__s = ((ulong)(ptr) & 0x3) * BITS_PER_BYTE;
__val = val << __s;
__mask = 0xff << __s;
asm volatile(
" lr.w %0, %1\n"
" and %0, %0, %3\n"
" xor %0, %0, %2\n"
" bnez %0, 1f\n"
ZAWRS_WRS_NTO "\n"
"1:"
: "=&r" (tmp), "+A" (*(__ptr32b))
: "r" (__val), "r" (__mask)
: "memory");
break;
case 2:
/* RISC-V doesn't have lr instructions on byte and half-word. */
goto no_zawrs;
__ptr32b = (u32 *)((ulong)(ptr) & ~0x3);
__s = ((ulong)(ptr) & 0x2) * BITS_PER_BYTE;
__val = val << __s;
__mask = 0xffff << __s;
asm volatile(
" lr.w %0, %1\n"
" and %0, %0, %3\n"
" xor %0, %0, %2\n"
" bnez %0, 1f\n"
ZAWRS_WRS_NTO "\n"
"1:"
: "=&r" (tmp), "+A" (*(__ptr32b))
: "r" (__val), "r" (__mask)
: "memory");
break;
case 4:
asm volatile(
" lr.w %0, %1\n"