mirrors/linux
1
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git synced 2026-05-03 08:50:17 -04:00
Code Issues Packages Projects Releases Wiki Activity
1,185,207 Commits 1 Branch 928 Tags
9bbcb892a7cd06c8156e6de211a8d7d45ee48086
Commit Graph

1185207 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Konrad Dybcio
9bbcb892a7 clk: qcom: gpucc-sc8280xp: Add runtime PM 
The GPU_CC block on SC8280XP is powered by the GFX rail. We need to
ensure that it's enabled to prevent unwanted power collapse.

Enable runtime PM to keep the power flowing only when necessary.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230619-topic-sc8280xp-clk-rpm-v1-1-1e5e1064cdb2@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-06-20 16:31:04 -07:00
Dmitry Baryshkov
4e13c7a55c clk: qcom: mmcc-msm8974: fix MDSS_GDSC power flags 
Using PWRSTS_RET on msm8974's MDSS_GDSC causes display to stop working.
The gdsc doesn't fully come out of retention mode. Change it's pwrsts
flags to PWRSTS_OFF_ON.

Fixes: d399723950 ("clk: qcom: gdsc: Fix the handling of PWRSTS_RET support")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Rajendra Nayak <quic_rjendra@quicinc.com>
Tested-by: Luca Weiss <luca@z3ntu.xyz>
Link: https://lore.kernel.org/r/20230507175335.2321503-2-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-06-20 10:41:33 -07:00
Konrad Dybcio
097d359c8c clk: qcom: gpucc-sm6375: Enable runtime pm 
The GPUCC block on SM6375 is powered by VDD_CX and VDD_GX. If the latter
rail is not online, GX_GDSC will never turn on. Enable runtime pm so that
we can reference VDD_GX from the dt to ensure that.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230529-topic-sm6375gpuccpd-v1-2-8d57c41a6066@linaro.org
 2023-06-13 16:30:13 -07:00
Konrad Dybcio
2f138c667c dt-bindings: clock: sm6375-gpucc: Add VDD_GX 
The GPUCC block on SM6375 is powered by VDD_CX and VDD_GX. If the latter
rail is not online, GX_GDSC will never turn on. Describe the missing
handles.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230529-topic-sm6375gpuccpd-v1-1-8d57c41a6066@linaro.org
 2023-06-13 16:30:13 -07:00
Konrad Dybcio
e88c533d8a clk: qcom: gcc-sm6115: Add missing PLL config properties 
When the driver was ported upstream, PLL ctl register values were omitted.
Add them to ensure the PLLs are fully configured like we expect them to.

Fixes: cbe63bfdc5 ("clk: qcom: Add Global Clock controller (GCC) driver for SM6115")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Iskren Chernev <me@iskren.info>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230601-topic-alpha_ctl-v1-2-b6a932dfcf68@linaro.org
 2023-06-13 16:15:04 -07:00
Konrad Dybcio
5016243394 clk: qcom: clk-alpha-pll: Add a way to update some bits of test_ctl(_hi) 
The "vanilla" Alpha PLL configs are sometimes provided with an intention
to only update certain bits of th register.

Do so if a mask is found.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Iskren Chernev <me@iskren.info>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230601-topic-alpha_ctl-v1-1-b6a932dfcf68@linaro.org
 2023-06-13 16:15:04 -07:00
Arnd Bergmann
5ae7899765 clk: qcom: gcc-ipq6018: remove duplicate initializers 
A recent change added new initializers for .config_ctl_val and
.config_ctl_hi_val but left the old values in place:

drivers/clk/qcom/gcc-ipq6018.c:4155:27: error: initialized field overwritten [-Werror=override-init]
 4155 |         .config_ctl_val = 0x240d4828,
      |                           ^~~~~~~~~~
drivers/clk/qcom/gcc-ipq6018.c:4156:30: error: initialized field overwritten [-Werror=override-init]
 4156 |         .config_ctl_hi_val = 0x6,
      |                              ^~~

Remove the unused ones now to avoid confusion.

Fixes: f4f0c8acee ("clk: qcom: gcc-ipq6018: update UBI32 PLL")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230601213416.3373599-1-arnd@kernel.org
 2023-06-13 16:11:01 -07:00
Anusha Rao
f6b2bd9cb2 clk: qcom: gcc-ipq9574: Enable crypto clocks 
Enable the clocks required for crypto operation.

Reviewed-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230526161129.1454-3-quic_anusha@quicinc.com
 2023-06-13 15:25:45 -07:00
Bjorn Andersson
004823da9b Merge branch '20230526161129.1454-2-quic_anusha@quicinc.com' into clk-for-6.5 
Merge the DeviceTree binding updates for IPQ9574 GCC adding clocks and
resets related to Crypto Engine, through a topic branch in order to make
them available in the DeviceTree source tree as well.
 2023-06-13 15:19:18 -07:00
Anusha Rao
35e237b3d5 dt-bindings: clock: Add crypto clock and reset definitions 
Add crypto clock and reset ID definitions for ipq9574.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230526161129.1454-2-quic_anusha@quicinc.com
 2023-06-13 15:17:22 -07:00
Srinivas Kandagatla
c2ef1ec97c clk: qcom: Add lpass audio clock controller driver for SC8280XP 
Add support for the lpass audio clock controller found on SC8280XP based
devices. This would allow lpass peripheral loader drivers to control the
clocks and bring the subsystems out of reset.

Currently this patch only supports resets as the Q6DSP is in control of
LPASS IP which manages most of the clocks via Q6PRM service on GPR rpmsg
channel.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230608125315.11454-5-srinivas.kandagatla@linaro.org
 2023-06-13 11:14:04 -07:00
Srinivas Kandagatla
a5c9c3ba24 clk: qcom: Add lpass clock controller driver for SC8280XP 
Add support for the lpass clock controller found on SC8280XP based devices.
This would allow lpass peripheral loader drivers to control the clocks and
bring the subsystems out of reset.

Currently this patch only supports resets as the Q6DSP is in control of
LPASS IP which manages most of the clocks via Q6PRM service on GPR rpmsg
channel.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230608125315.11454-4-srinivas.kandagatla@linaro.org
 2023-06-13 11:14:04 -07:00
Luca Weiss
5683f11aa1 dt-bindings: clock: qcom,mmcc: define clocks/clock-names for MSM8226 
Define clock/clock-names properties of the MMCC device node to be used
on MSM8226 platform.

Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Acked-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230509-msm8226-mmcc-parents-v1-2-83a2dfc986ab@z3ntu.xyz
 2023-06-13 10:02:57 -07:00
Jagadeesh Kona
bfae40744b clk: qcom: gpucc-sm8550: Add support for graphics clock controller 
Add support for gpucc driver on SM8550, which provides clocks for the
graphics subsystem.

Co-developed-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230524181800.28717-3-quic_jkona@quicinc.com
 2023-05-26 18:24:05 -07:00
Konrad Dybcio
728692d49e clk: qcom: Add support for SM8450 GPUCC 
The GPUCC manages the clocks for the Adreno GPU found on the
sm8450 SoCs.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230517-topic-waipio-gpucc-v1-4-4f40e282af1d@linaro.org
 2023-05-26 18:23:24 -07:00
Konrad Dybcio
d4113d5f2b clk: qcom: gcc-sm8450: Enable hw_clk_ctrl 
Enable hardware clock control on all RCGs.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230517-topic-waipio-gpucc-v1-3-4f40e282af1d@linaro.org
 2023-05-26 18:22:58 -07:00
Konrad Dybcio
a0e0ec7424 clk: qcom: rcg2: Make hw_clk_ctrl toggleable 
Certain SoCs use the HW_CLK_CTRL feature on some of the clocks they
host. This allows the clocks to be turned on automatically when a
downstream branch tries to change rate or config.

Make it togglable so that we can utilize this.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230517-topic-waipio-gpucc-v1-2-4f40e282af1d@linaro.org
 2023-05-26 18:22:58 -07:00
Bjorn Andersson
6de1bd7405 Merge branch 'sm8450-sm8550-gpucc-binding' into clk-for-6.5 
Bring GPUCC DeviceTree bindings for SM8450 and SM8550 in through a topic
branch to allow sharing it with the DeviceTree source tree as well.
 2023-05-26 18:22:17 -07:00
Jagadeesh Kona
778af143ad dt-bindings: clock: qcom: Add SM8550 graphics clock controller 
Add device tree bindings for the graphics clock controller on
Qualcomm SM8550 platform.

Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230524181800.28717-2-quic_jkona@quicinc.com
 2023-05-26 18:22:07 -07:00
Konrad Dybcio
63f4e4b6f5 dt-bindings: clock: Add Qcom SM8450 GPUCC 
Add device tree bindings for the graphics clock controller on Qualcomm
Technology Inc's SM8450 SoCs.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230517-topic-waipio-gpucc-v1-1-4f40e282af1d@linaro.org
 2023-05-26 18:22:04 -07:00
Dmitry Baryshkov
8fd492e77f clk: qcom: mmcc-msm8974: use clk_rcg2_shared_ops for mdp_clk_src clock 
The mdp_clk_src clock should not be turned off. Instead it should be
'parked' to the XO, as most of other mdp_clk_src clocks. Fix that by
using the clk_rcg2_shared_ops.

Fixes: d8b212014e ("clk: qcom: Add support for MSM8974's multimedia clock controller (MMCC)")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Luca Weiss <luca@z3ntu.xyz>
Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230507175335.2321503-1-dmitry.baryshkov@linaro.org
 2023-05-26 13:42:46 -07:00
Kathiravan T
7510e80f4a clk: qcom: ipq5332: fix the order of SLEEP_CLK and XO clock 
The order of DT_SLEEP_CLK and DT_XO are swapped and it is incorrect.
Due to which the clocks for which the parent should be XO is having parent
as SLEEP_CLK and vice versa. So fix the same by re-ordering the entries.

Fixes: 3d89d52970 ("clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC")
Reported-by: Devi Priya <quic_devipriy@quicinc.com>
Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230417105607.4091-1-quic_kathirav@quicinc.com
 2023-05-26 13:29:32 -07:00
Kathiravan T
81c1ef89a4 clk: qcom: ipq5332: fix the src parameter in ftbl_gcc_apss_axi_clk_src 
480MHz is derived from P_GPLL4_OUT_AUX not from P_GPLL4_OUT_MAIN. Update
the freq_tbl with the correct src.

Fixes: 3d89d52970 ("clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC")
Reported-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230417044342.9406-1-quic_kathirav@quicinc.com
 2023-05-26 13:29:23 -07:00
Konrad Dybcio
63d56adf04 clk: qcom: dispcc-qcm2290: Fix GPLL0_OUT_DIV handling 
GPLL0_OUT_DIV (.fw_name = "gcc_disp_gpll0_div_clk_src") was previously
made to reuse the same parent enum entry as GPLL0_OUT_MAIN
(.fw_name = "gcc_disp_gpll0_clk_src") in parent_map_2.

Resolve it by introducing its own entry in the parent enum and
correctly assigning it in disp_cc_parent_map_2[].

Fixes: cc517ea333 ("clk: qcom: Add display clock controller driver for QCM2290")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230412-topic-qcm_dispcc-v2-2-bce7dd512fe4@linaro.org
 2023-05-26 13:26:03 -07:00
Konrad Dybcio
92dfee0fc8 clk: qcom: dispcc-qcm2290: Fix BI_TCXO_AO handling 
BI_TCXO_AO (.fw_name = "bi_tcxo_ao") was previously made to reuse the
same parent enum entry as BI_TCXO (.fw_name = "bi_tcxo") in parent_map_2.

Resolve it by introducing its own entry in the parent enum and
correctly assigning it in disp_cc_parent_map_2[].

Fixes: cc517ea333 ("clk: qcom: Add display clock controller driver for QCM2290")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230412-topic-qcm_dispcc-v2-1-bce7dd512fe4@linaro.org
 2023-05-26 13:26:02 -07:00
Robert Marko
349b5bed53 clk: qcom: ipq6018: fix networking resets 
Networking resets in IPQ6018 all use bitmask as they require multiple
bits to be set and cleared instead of a single bit.

So, current networking resets have the same register and bit 0 set which
is clearly incorrect.

Fixes: d9db07f088 ("clk: qcom: Add ipq6018 Global Clock Controller support")
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230526190855.2941291-2-robimarko@gmail.com
 2023-05-26 13:04:52 -07:00
Robert Marko
f4f0c8acee clk: qcom: gcc-ipq6018: update UBI32 PLL 
Update the UBI32 alpha PLL config to the latest values from the downstream
QCA 5.4 kernel.

Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230526190855.2941291-1-robimarko@gmail.com
 2023-05-26 13:04:52 -07:00
Devi Priya
20beb85f7a clk: qcom: apss-ipq-pll: Add support for IPQ9574 
Add the compatible and configuration values for A73 Huayra PLL found
on IPQ9574.

Co-developed-by: Praveenkumar I <quic_ipkumar@quicinc.com>
Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230406061314.10916-3-quic_devipriy@quicinc.com
 2023-05-26 12:16:40 -07:00
Devi Priya
17035787e2 dt-bindings: clock: qcom,a53pll: add IPQ9574 compatible 
IPQ9574 uses A73 PLL of type Huayra. Add the IPQ9574 A73 compatible to A53
bindings as the PLL properties match with that of A53.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230406061314.10916-2-quic_devipriy@quicinc.com
 2023-05-26 12:16:40 -07:00
Krzysztof Kozlowski
7a52084ae1 dt-bindings: clock: qcom,gcc-sc7280: document CX power domain 
The GCC clock controller needs CX power domain, at least according to
DTS:

  sc7280-herobrine-crd-pro.dtb: clock-controller@100000: Unevaluated properties are not allowed ('power-domains' was unexpected)

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230516105241.30091-3-krzysztof.kozlowski@linaro.org
 2023-05-24 21:47:17 -07:00
Krzysztof Kozlowski
21a95637a3 dt-bindings: clock: qcom,gcc-sc7180: document CX power domain 
The GCC clock controller needs CX power domain, at least according to
DTS:

  sc7180-trogdor-pompom-r3.dtb: clock-controller@100000: Unevaluated properties are not allowed ('power-domains' was unexpected)

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230516105241.30091-2-krzysztof.kozlowski@linaro.org
 2023-05-24 21:47:17 -07:00
Krzysztof Kozlowski
2310ab77f1 dt-bindings: clock: qcom,gcc-sm8250: add missing bi_tcxo_ao clock 
The initial SM8250 GCC driver added in commit 3e5770921a ("clk: qcom:
gcc: Add global clock controller driver for SM8250") already consumed it
on the clock.  This fixes warnings like:

  sm8250-xiaomi-elish-csot.dtb: clock-controller@100000: clock-names: ['bi_tcxo', 'bi_tcxo_ao', 'sleep_clk'] is too long

Fixes: 98394efb48 ("dt-bindings: clock: Add SM8250 GCC clock bindings")
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230516105241.30091-1-krzysztof.kozlowski@linaro.org
 2023-05-24 21:47:17 -07:00
Krzysztof Kozlowski
ab7f00379f clk: qcom: restrict drivers per ARM/ARM64 
There is no point to allow selecting clock controller drivers for
Qualcomm ARMv7 SoCs when building ARM64 kernel, and vice versa.  This
makes kernel configuration more difficult as many do not remember the
Qualcomm SoCs model names/numbers.  No features should be lost because:
1. There won't be a single image for ARMv7 and ARMv8/9 SoCs.
2. Newer ARMv8/9 SoCs won't be running in arm32 emulation mode.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230514114711.18258-1-krzysztof.kozlowski@linaro.org
 2023-05-24 21:47:17 -07:00
Imran Shaik
108cdc09b2 clk: qcom: Add GCC driver support for SDX75 
Add Global Clock Controller (GCC) support for SDX75 platform.

Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230512122347.1219-6-quic_tdas@quicinc.com
 2023-05-24 21:47:17 -07:00
Imran Shaik
1c2360ff58 clk: qcom: rpmh: Add RPMH clocks support for SDX75 
Add support for RPMH clocks for SDX75 platform.

Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230512122347.1219-5-quic_tdas@quicinc.com
 2023-05-24 21:47:17 -07:00
Imran Shaik
379d72721b dt-bindings: clock: qcom: Add RPMHCC for SDX75 
Add compatible string for qcom RPMHCC for SDX75 platform.

Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230512122347.1219-4-quic_tdas@quicinc.com
 2023-05-24 21:47:17 -07:00
Imran Shaik
9092d1083a clk: qcom: branch: Extend the invert logic for branch2 clocks 
Add support to handle the invert logic for branch2 clocks.
Invert branch halt would indicate the clock ON when CLK_OFF
bit is '1' and OFF when CLK_OFF bit is '0'.

Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230512122347.1219-2-quic_tdas@quicinc.com
 2023-05-24 21:47:17 -07:00
Bjorn Andersson
521302ca64 Merge branch '20230512122347.1219-3-quic_tdas@quicinc.com' into clk-for-6.5 
Merge SDX75 Global Clock Controller DeviceTree binding through a topic
branch, to allow inclusion in DeviceTree source as well.
 2023-05-24 21:47:17 -07:00
Luca Weiss
e9a2db5caf clk: qcom: smd-rpm: conditionally enable scaling before doing handover 
On older platforms like msm8226, msm8974 and msm8916 the driver in the
downstream kernel enables scaling first before doing the handover of the
clocks.

While this normally doesn't seem to cause noticeable problems, on
apq8026-asus-sparrow this causes the device to immediately reboot,
perhaps due to older rpm firmware that becomes unhappy.

On newer platforms the order has swapped and enabling scaling is done
after the handover, so let's introduce this behavior only conditionally
for msm8226 and msm8974 for now.

Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230506-rpmcc-scaling-handover-v1-1-374338a8dfd9@z3ntu.xyz
 2023-05-24 21:47:17 -07:00
Christian Marangi
bbd899f534 clk: qcom: gcc-sdm660: drop redundant F define 
The same exact F frequency table entry is defined in clk-rcg.h
Drop the redundant define to cleanup code.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230417174408.23722-2-ansuelsmth@gmail.com
 2023-05-24 21:47:17 -07:00
Christian Marangi
923f7d678b clk: qcom: gcc-ipq6018: drop redundant F define 
The same exact F frequency table entry is defined in clk-rcg.h
Drop the redundant define to cleanup code.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230417174408.23722-1-ansuelsmth@gmail.com
 2023-05-24 21:47:16 -07:00
Krzysztof Kozlowski
2f9b209646 dt-bindings: clock: qcom,gcc-msm8953: split to separate schema 
The Qualcomm MSM8953 GCC clock controller has clock inputs, thus
existing gcc-other.yaml was not describing it fully.  Move the binding
to its own schema file and document the clocks based on DTS.  Add driver
contributors as its maintainers.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230408143729.84097-1-krzysztof.kozlowski@linaro.org
 2023-05-24 21:47:16 -07:00
Konrad Dybcio
7bf654a0d9 clk: qcom: gcc-qcm2290: Mark RCGs shared where applicable 
The vast majority of shared RCGs were not marked as such. Fix it.

Fixes: 496d1a13d4 ("clk: qcom: Add Global Clock Controller driver for QCM2290")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230403174807.345185-1-konrad.dybcio@linaro.org
 2023-05-24 21:47:16 -07:00
Jagadeesh Kona
f53153a379 clk: qcom: videocc-sm8550: Add video clock controller driver for SM8550 
Add support for the video clock controller for video clients to be able
to request for videocc clocks on SM8550 platform.

Co-developed-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230524145203.13153-4-quic_jkona@quicinc.com
 2023-05-24 21:47:16 -07:00
Jagadeesh Kona
c7d91f26f0 dt-bindings: clock: qcom: Add SM8550 video clock controller 
Add compatible string for SM8550 video clock controller.

Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230524145203.13153-3-quic_jkona@quicinc.com
 2023-05-24 21:47:16 -07:00
Jagadeesh Kona
34d54e5833 clk: qcom: clk-alpha-pll: Add support to configure PLL_TEST_CTL_U2 
The lucid ole pll reuses lucid evo ops but it has an additional test
control register which is required to be programmed, add support to
program the same.

Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230524145203.13153-2-quic_jkona@quicinc.com
 2023-05-24 21:47:16 -07:00
Taniya Das
441fe711be clk: qcom: videocc-sm8450: Add video clock controller driver for SM8450 
Add support for the video clock controller driver for peripheral clock
clients to be able to request for video cc clocks.

Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230524140656.7076-3-quic_tdas@quicinc.com
 2023-05-24 21:47:16 -07:00
Bjorn Andersson
cc8d2cf5cd Merge branch '20230524140656.7076-2-quic_tdas@quicinc.com' into HEAD 
Merge the SM8450 Video Clock Controller DeviceTree binding through a
topic branch, in order to be able to use the introduced constants in
changes on DeviceTree source branch as well.
 2023-05-24 21:47:16 -07:00
Konrad Dybcio
fd0b5b106f clk: qcom: Introduce SM8350 VIDEOCC 
Add support for the Video Clock Controller found on the SM8350 SoC.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230413-topic-lahaina_vidcc-v4-2-86c714a66a81@linaro.org
 2023-05-24 21:47:16 -07:00
Bjorn Andersson
6d6a98aaa7 Merge branch '20230413-topic-lahaina_vidcc-v4-1-86c714a66a81@linaro.org' into HEAD 
Merge the Video Clock Controller DeviceTree bindings through a topic
branch, in order to be able to use the introduced constants in the
DeviceTree source branch as well.
 2023-05-24 21:46:48 -07:00