2271 Commits

Author	SHA1	Message	Date
Linus Torvalds	522ba450b5	Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux ... Pull clk updates from Stephen Boyd: "There's a bunch of patches here across drivers/clk/ to migrate drivers to use struct clk_ops::determine_rate() instead of the round_rate() one so that we can remove the round_rate clk_op entirely. Brian has taken up that task which nobody else has wanted to do for close to a decade. Thanks Brian! This is all prerequisite work to get to the real task of improving the clk rate setting process. Once we have determine_rate() used everywhere, we'll be able to do things like chain the rate request structs in linked lists to order the rate setting operations or add more parameters without having to change every clk driver in existence. It's also nice to not have multiple ways to do something which just causes confusion for clk driver authors. Overall I'm glad this is getting done. Beyond this change we also have a tweak to the clk_lookup() function in the core framework to use hashing on the clk name instead of a clk tree walk with string comparisons. We _still_ rely on the clk name to be unique, because historically we've used globally unique strings to describe the clk tree topology. This tree walk becomes increasingly slow as more clks are added to the system. Searching from the roots for a duplicate is simple but pretty dumb and it wastes boot time so we're using a hash table as an improvement. Ideally we wouldn't rely on the strings to be unique at all, relegating them to simply debug information, but that is future work that will likely require some sort of Kconfig knob indicating strings aren't used for topology description. Outside of the core framework changes we have the usual new SoC support and fixes to clk drivers for things that were discovered once the clks were used by consumer drivers. Nothing in particular is jumping out at me in the "misc" pile, except maybe the Amlogic driver that has gone through a refactoring. That series got a fix from testing in -next though so it seems likely that things have been getting good test coverage for a couple weeks already" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (299 commits) clk: microchip: core: remove duplicate roclk_determine_rate() reset: aspeed: register AST2700 reset auxiliary bus device dt-bindings: clock: ast2700: modify soc0/1 clock define clk: tegra: do not overallocate memory for bpmp clocks clk: ep93xx: Use int type to store negative error codes clk: nxp: Fix pll0 rate check condition in LPC18xx CGU driver clk: loongson2: Add clock definitions for Loongson-2K0300 SoC clk: loongson2: Avoid hardcoding firmware name of the reference clock clk: loongson2: Allow zero divisors for dividers clk: loongson2: Support scale clocks with an alternative mode clk: loongson2: Allow specifying clock flags for gate clock dt-bindings: clock: loongson2: Add Loongson-2K0300 compatible clk: clocking-wizard: Fix output clock register offset for Versal platforms clk: xilinx: Optimize divisor search in clk_wzrd_get_divisors_ver() clk: mmp: pxa1908: Instantiate power driver through auxiliary bus clk: s2mps11: add support for S2MPG10 PMIC clock dt-bindings: clock: samsung,s2mps11: add s2mpg10 dt-bindings: stm32: cosmetic fixes for STM32MP25 clock and reset bindings clk: stm32: introduce clocks for STM32MP21 platform dt-bindings: stm32: add STM32MP21 clocks and reset bindings ...	2025-10-07 09:28:37 -07:00
Stephen Boyd	8397c58ea7	Merge branches 'clk-marvell', 'clk-xilinx', 'clk-mediatek' and 'clk-loongson' into clk-next ... - Add Mediatek MT8196 clk drivers * clk-marvell: clk: mmp: pxa1908: Instantiate power driver through auxiliary bus * clk-xilinx: clk: clocking-wizard: Fix output clock register offset for Versal platforms clk: xilinx: Optimize divisor search in clk_wzrd_get_divisors_ver() * clk-mediatek: (31 commits) clk: mediatek: Add MT8196 vencsys clock support clk: mediatek: Add MT8196 vdecsys clock support clk: mediatek: Add MT8196 ovl1 clock support clk: mediatek: Add MT8196 ovl0 clock support clk: mediatek: Add MT8196 disp-ao clock support clk: mediatek: Add MT8196 disp1 clock support clk: mediatek: Add MT8196 disp0 clock support clk: mediatek: Add MT8196 mfg clock support clk: mediatek: Add MT8196 mdpsys clock support clk: mediatek: Add MT8196 mcu clock support clk: mediatek: Add MT8196 I2C clock support clk: mediatek: Add MT8196 pextpsys clock support clk: mediatek: Add MT8196 ufssys clock support clk: mediatek: Add MT8196 peripheral clock support clk: mediatek: Add MT8196 vlpckgen clock support clk: mediatek: Add MT8196 topckgen2 clock support clk: mediatek: Add MT8196 topckgen clock support clk: mediatek: Add MT8196 apmixedsys clock support dt-bindings: clock: mediatek: Describe MT8196 clock controllers clk: mediatek: clk-mtk: Add MUX_DIV_GATE macro ... * clk-loongson: clk: loongson2: Add clock definitions for Loongson-2K0300 SoC clk: loongson2: Avoid hardcoding firmware name of the reference clock clk: loongson2: Allow zero divisors for dividers clk: loongson2: Support scale clocks with an alternative mode clk: loongson2: Allow specifying clock flags for gate clock dt-bindings: clock: loongson2: Add Loongson-2K0300 compatible	2025-10-06 13:00:22 -05:00
Stephen Boyd	b91217d912	Merge branches 'clk-microchip', 'clk-lookup' and 'clk-st' into clk-next ... - Speed up clk_core_lookup() by using a hashtable * clk-microchip: ARM: at91: remove default values for PMC_PLL_ACR clk: at91: add ACR in all PLL settings clk: at91: sam9x7: Add peripheral clock id for pmecc clk: at91: clk-master: Add check for divide by 3 clk: at91: clk-sam9x60-pll: force write to PLL_UPDT register ARM: at91: pm: save and restore ACR during PLL disable/enable * clk-lookup: clk: Use hashtable for global clk lookups clk: Sort include statements * clk-st: dt-bindings: stm32: cosmetic fixes for STM32MP25 clock and reset bindings clk: stm32: introduce clocks for STM32MP21 platform dt-bindings: stm32: add STM32MP21 clocks and reset bindings	2025-10-06 13:00:12 -05:00
Stephen Boyd	f0fd248204	Merge branches 'clk-scmi', 'clk-qcom' and 'clk-broadcom' into clk-next ... * clk-scmi: clk: scmi: Add duty cycle ops only when duty cycle is supported * clk-qcom: (27 commits) clk: qcom: gcc-sc8280xp: drop obsolete PCIe GDSC comment clk: qcom: tcsrcc-x1e80100: Set the bi_tcxo as parent to eDP refclk clk: qcom: dispcc-glymur: Constify 'struct qcom_cc_desc' clk: qcom: gcc: Add support for Global Clock controller found on MSM8937 dt-bindings: clock: qcom: Add MSM8937 Global Clock Controller clk: qcom: Select the intended config in QCS_DISPCC_615 clk: qcom: common: Fix NULL vs IS_ERR() check in qcom_cc_icc_register() clk: qcom: alpha-pll: convert from round_rate() to determine_rate() clk: qcom: milos: Constify 'struct qcom_cc_desc' clk: qcom: gcc: Add support for Global Clock Controller dt-bindings: clock: qcom: document the Glymur Global Clock Controller clk: qcom: clk-alpha-pll: Add support for Taycan EKO_T PLL clk: qcom: rpmh: Add support for Glymur rpmh clocks clk: qcom: Add TCSR clock driver for Glymur SoC dt-bindings: clock: qcom: Document the Glymur SoC TCSR Clock Controller dt-bindings: clock: qcom-rpmhcc: Add support for Glymur SoCs clk: qcom: dispcc-glymur: Add support for Display Clock Controller dt-bindings: clock: Add DISPCC and reset controller for GLYMUR SoC clk: qcom: gcc-sdm660: Add missing LPASS/CDSP vote clocks dt-bindings: clock: gcc-sdm660: Add LPASS/CDSP vote clocks/GDSCs ... * clk-broadcom: clk: bcm: rpi: Maximize V3D clock clk: bcm: rpi: Turn firmware clock on/off when preparing/unpreparing clk: bcm: rpi: Add missing logs if firmware fails	2025-10-06 12:57:03 -05:00
Stephen Boyd	c1e102f349	Merge branches 'clk-imx', 'clk-allwinner' and 'clk-ti' into clk-next ... * clk-imx: clk: imx95-blk-ctl: Save/restore registers when RPM routines are called clk: imx95-blk-ctl: Save platform data in imx95_blk_ctl structure * clk-allwinner: clk: sunxi-ng: add support for the A523/T527 MCU CCU clk: sunxi-ng: div: support power-of-two dividers clk: sunxi-ng: sun55i-a523-ccu: Add missing NPU module clock dt-bindings: clock: sun55i-a523-ccu: Add A523 MCU CCU clock controller dt-bindings: clock: sun55i-a523-ccu: Add missing NPU module clock clk: sunxi-ng: sun6i-rtc: Add A523 specifics * clk-ti: clk: keystone: sci-clk: use devm_kmemdup_array() clk: ti: am33xx: keep WKUP_DEBUGSS_CLKCTRL enabled	2025-10-06 12:56:54 -05:00
Stephen Boyd	3aae991cc2	Merge branches 'clk-samsung', 'clk-tegra' and 'clk-amlogic' into clk-next ... * clk-samsung: clk: s2mps11: add support for S2MPG10 PMIC clock dt-bindings: clock: samsung,s2mps11: add s2mpg10 clk: samsung: exynos990: Add PERIC0 and PERIC1 clock support dt-bindings: clock: exynos990: Add PERIC0 and PERIC1 clock units clk: samsung: exynos990: Add missing USB clock registers to HSI0 clk: samsung: exynos990: Add LHS_ACEL gate clock for HSI0 and update CLK_NR_TOP dt-bindings: clock: exynos990: Add LHS_ACEL clock ID for HSI0 block clk: samsung: artpec-8: Add initial clock support for ARTPEC-8 SoC clk: samsung: Add clock PLL support for ARTPEC-8 SoC dt-bindings: clock: Add ARTPEC-8 clock controller clk: samsung: exynos990: Add DPU_BUS and CMUREF mux/div and update CLKS_NR_TOP dt-bindings: clock: exynos990: Extend clocks IDs clk: samsung: exynos990: Replace bogus divs with fixed-factor clocks clk: samsung: exynos990: Fix CMU_TOP mux/div bit widths clk: samsung: exynos990: Use PLL_CON0 for PLL parent muxes clk: samsung: pll: convert from round_rate() to determine_rate() clk: samsung: cpu: convert from round_rate() to determine_rate() clk: samsung: fsd: Add clk id for PCLK and PLL in CAM_CSI block dt-bindings: clock: Add CAM_CSI clock macro for FSD * clk-tegra: clk: tegra: dfll: Add CVB tables for Tegra114 clk: tegra: Add DFLL DVCO reset control for Tegra114 dt-bindings: arm: tegra: Add ASUS TF101G and SL101 dt-bindings: reset: Add Tegra114 CAR header dt-bindings: arm: tegra: Add Xiaomi Mi Pad (A0101) dt-bindings: clock: tegra30: Add IDs for CSI pad clocks dt-bindings: display: tegra: Move avdd-dsi-csi-supply from VI to CSI dt-bindings: i2c: nvidia,tegra20-i2c: Document Tegra264 I2C * clk-amlogic: clk: amlogic: fix recent code refactoring clk: amlogic: c3-peripherals: use helper for basic composite clocks clk: amlogic: align s4 and c3 pwm clock descriptions clk: amlogic: add composite clock helpers clk: amlogic: use the common pclk definition clk: amlogic: introduce a common pclk definition clk: amlogic: pclk explicitly use CLK_IGNORE_UNUSED clk: amlogic: drop CLK_SET_RATE_PARENT from peripheral clocks clk: amlogic: move PCLK definition to clkc-utils clk: amlogic: aoclk: use clkc-utils syscon probe clk: amlogic: use probe helper in mmio based controllers clk: amlogic: add probe helper for mmio based controllers clk: amlogic: drop meson-clkcee clk: amlogic: naming consistency alignment	2025-10-06 12:56:46 -05:00
Stephen Boyd	ec7336475d	Merge branches 'clk-bindings', 'clk-cleanup', 'clk-renesas', 'clk-thead' and 'clk-spacemit' into clk-next ... * clk-bindings: dt-bindings: clock: mediatek: Add power-domains property dt-bindings: clock: silabs,si5341: Add missing properties dt-bindings: clock: adi,axi-clkgen: add clock-output-names property dt-bindings: clock: Remove unused fujitsu,mb86s70-crg11 binding dt-bindings: clock: Convert silabs,si570 to DT schema dt-bindings: clock: Convert silabs,si5341 to DT schema dt-bindings: clock: Convert silabs,si514/544 to DT schema * clk-cleanup: clk: tegra: do not overallocate memory for bpmp clocks clk: ep93xx: Use int type to store negative error codes dt-bindings: clock: st: flexgen: remove deprecated compatibles clk: st: flexgen: remove unused compatible clk: clk-axi-clkgen: remove unneeded semicolon clk: tegra: Remove redundant semicolons clk: npcm: select CONFIG_AUXILIARY_BUS clk: remove unneeded 'fast_io' parameter in regmap_config * clk-renesas: (27 commits) clk: renesas: r9a09g05[67]: Reduce differences clk: renesas: r9a09g047: Add USB3.0 clocks/resets clk: renesas: cpg-mssr: Fix memory leak in cpg_mssr_reserved_init() clk: renesas: r9a09g056: Add clock and reset entries for I3C clk: renesas: r9a09g057: Add clock and reset entries for I3C dt-bindings: clock: renesas,r9a09g047-cpg: Add USB3.0 core clocks clk: renesas: r9a09g077: Add Ethernet Subsystem core and module clocks clk: renesas: rzv2h: Simplify polling condition in __rzv2h_cpg_assert() clk: renesas: rzv2h: Re-assert reset on deassert timeout clk: renesas: rzg2l: Re-assert reset on deassert timeout clk: renesas: rzg2l: Simplify rzg2l_cpg_assert() and rzg2l_cpg_deassert() dt-bindings: clock: renesas,r9a09g077/87: Add Ethernet clock IDs clk: renesas: r9a09g047: Add GPT clocks and resets clk: renesas: r9a09g077: Add module clocks for SCI1-SCI5 clk: renesas: rzv2h: remove round_rate() in favor of determine_rate() clk: renesas: rzg2l: convert from round_rate() to determine_rate() clk: renesas: r9a07g04[34]: Use tabs instead of spaces clk: renesas: r9a07g043: Add MSTOP for RZ/G2UL clk: renesas: r9a07g044: Add MSTOP for RZ/G2L clk: renesas: r9a08g045: Add MSTOP for GPIO ... * clk-thead: clk: thead: th1520-ap: set all AXI clocks to CLK_IS_CRITICAL clk: thead: support changing DPU pixel clock rate clk: thead: add support for enabling/disabling PLLs clk: thead: Correct parent for DPU pixel clocks clk: thead: th1520-ap: fix parent of padctrl0 clock clk: thead: th1520-ap: describe gate clocks with clk_gate * clk-spacemit: clk: spacemit: fix i2s clock clk: spacemit: introduce pre-div for ddn clock dt-bindings: clock: spacemit: introduce i2s pre-clock to fix i2s clock clk: spacemit: ccu_pll: convert from round_rate() to determine_rate() clk: spacemit: ccu_mix: convert from round_rate() to determine_rate() clk: spacemit: ccu_ddn: convert from round_rate() to determine_rate() clk: spacemit: fix sspax_clk dt-bindings: clock: spacemit: CLK_SSPA_I2S_BCLK for SSPA	2025-10-06 12:56:23 -05:00
Linus Torvalds	86bcf7be1e	Merge tag 'riscv-for-linus-6.18-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux ... Pull more RISC-V updates from Paul Walmsley: - Support for the RISC-V-standardized RPMI interface. RPMI is a platform management communication mechanism between OSes running on application processors, and a remote platform management processor. Similar to ARM SCMI, TI SCI, etc. This includes irqchip, mailbox, and clk changes. - Support for the RISC-V-standardized MPXY SBI extension. MPXY is a RISC-V-specific standard implementing a shared memory mailbox between S-mode operating systems (e.g., Linux) and M-mode firmware (e.g., OpenSBI). It is part of this PR since one of its use cases is to enable M-mode firmware to act as a single RPMI client for all RPMI activity on a core (including S-mode RPMI activity). Includes a mailbox driver. - Some ACPI-related updates to enable the use of RPMI and MPXY. - The addition of Linux-wide memcpy_{from,to}_le32() static inline functions, for RPMI use. - An ACPI Kconfig change to enable boot logos on any ACPI-using architecture (including RISC-V) - A RISC-V defconfig change to add GPIO keyboard and event device support, for front panel shutdown or reboot buttons * tag 'riscv-for-linus-6.18-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (26 commits) clk: COMMON_CLK_RPMI should depend on RISCV ACPI: support BGRT table on RISC-V MAINTAINERS: Add entry for RISC-V RPMI and MPXY drivers RISC-V: Enable GPIO keyboard and event device in RV64 defconfig irqchip/riscv-rpmi-sysmsi: Add ACPI support mailbox/riscv-sbi-mpxy: Add ACPI support irqchip/irq-riscv-imsic-early: Export imsic_acpi_get_fwnode() ACPI: RISC-V: Add RPMI System MSI to GSI mapping ACPI: RISC-V: Add support to update gsi range ACPI: RISC-V: Create interrupt controller list in sorted order ACPI: scan: Update honor list for RPMI System MSI ACPI: Add support for nargs_prop in acpi_fwnode_get_reference_args() ACPI: property: Refactor acpi_fwnode_get_reference_args() to support nargs_prop irqchip: Add driver for the RPMI system MSI service group dt-bindings: Add RPMI system MSI interrupt controller bindings dt-bindings: Add RPMI system MSI message proxy bindings clk: Add clock driver for the RISC-V RPMI clock service group dt-bindings: clock: Add RPMI clock service controller bindings dt-bindings: clock: Add RPMI clock service message proxy bindings mailbox: Add RISC-V SBI message proxy (MPXY) based mailbox driver ...	2025-10-04 10:36:22 -07:00
Linus Torvalds	d955299b5c	Merge tag 'soc-fixes-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc ... Pull SoC build fix from Arnd Bergmann: "One commit for the dt bindings was missing from the dt branch, this one is already pending in the clk tree that contains the corresponding device driver" * tag 'soc-fixes-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: dt-bindings: clock: Add ARTPEC-8 clock controller	2025-10-03 19:36:39 -07:00
Linus Torvalds	38057e3236	Merge tag 'soc-drivers-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc ... Pull SoC driver updates from Arnd Bergmann: "Lots of platform specific updates for Qualcomm SoCs, including a new TEE subsystem driver for the Qualcomm QTEE firmware interface. Added support for the Apple A11 SoC in drivers that are shared with the M1/M2 series, among more updates for those. Smaller platform specific driver updates for Renesas, ASpeed, Broadcom, Nvidia, Mediatek, Amlogic, TI, Allwinner, and Freescale SoCs. Driver updates in the cache controller, memory controller and reset controller subsystems. SCMI firmware updates to add more features and improve robustness. This includes support for having multiple SCMI providers in a single system. TEE subsystem support for protected DMA-bufs, allowing hardware to access memory areas that managed by the kernel but remain inaccessible from the CPU in EL1/EL0" * tag 'soc-drivers-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (139 commits) soc/fsl/qbman: Use for_each_online_cpu() instead of for_each_cpu() soc: fsl: qe: Drop legacy-of-mm-gpiochip.h header from GPIO driver soc: fsl: qe: Change GPIO driver to a proper platform driver tee: fix register_shm_helper() pmdomain: apple: Add "apple,t8103-pmgr-pwrstate" dt-bindings: spmi: Add Apple A11 and T2 compatible serial: qcom-geni: Load UART qup Firmware from linux side spi: geni-qcom: Load spi qup Firmware from linux side i2c: qcom-geni: Load i2c qup Firmware from linux side soc: qcom: geni-se: Add support to load QUP SE Firmware via Linux subsystem soc: qcom: geni-se: Cleanup register defines and update copyright dt-bindings: qcom: se-common: Add QUP Peripheral-specific properties for I2C, SPI, and SERIAL bus Documentation: tee: Add Qualcomm TEE driver tee: qcom: enable TEE_IOC_SHM_ALLOC ioctl tee: qcom: add primordial object tee: add Qualcomm TEE driver tee: increase TEE_MAX_ARG_SIZE to 4096 tee: add TEE_IOCTL_PARAM_ATTR_TYPE_OBJREF tee: add TEE_IOCTL_PARAM_ATTR_TYPE_UBUF tee: add close_context to TEE driver operation ...	2025-10-01 17:32:51 -07:00
Linus Torvalds	0f048c878e	Merge tag 'soc-dt-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc ... Pull SoC dt updates from Arnd Bergmann: "There are five sets of new SoCs that get added in existing families, all of them being either upgrades or cut-down versions of the older chips: - Apple M2 Pro, M2 Max and M2 Ultra, used in the 2022/2023 generation of high-end workstations and laptops from Apple. Linux has been working on these for a while but stil requires patches. - Axis Artpec8 is an Armv8 chip based on Samsung Exynos design, unlike the earlier Armv7 Artpec6 from the same company that was part of a separate family of chips. - NXP i.MX91 is a cut-down version of i.MX93, using only a single Cortex-A55 core. - Qualcomm Lemans Auto is a variant of the Lemans SoC that was originally merged under the sa8775p name, the differences being mostly the firmware configuration of the platform. - Four new Renesas SoCs RZ/T2H (r9a09g077m44), RZ/N2H (r9a09g087m44), RZ/T2H (r9a09g077), and RZ/N2H (r9a09g087) are all industrial bedded SoCs based on Cortex-A55 cores In total, there are 65 new machines, including: - Industrial embedded system and single-board computers based on NXP, Allwinner, TI, Rockchips, Marvell, Xilinx Spacemit, Starfive chips. - Reference boards for the newly added Renesas, Qualcomm, NXP and Axis ARMv8 chips as well as Microchip's MPFS RISC-V SoC - Laptops and Workstations using Apple M2 and Qualcomm Snapdragon X1 chips. - Several Samsung phones using Qualcomm Snapdragon chips - Set-top boxes based on Allwinner H313 - Five BMC boards using 32-bit ASpeed SoCs - Three network routers using IXP4xx (ARMv5!) and Broadcom bcm4708 (ARMv7) SoCs Two machines get phased out because they were available only in small quantities but never made it into products: one STi407 based reference board, and a Snapdragon 845 based Chromebook. Aside from the newly added machines, a lot of work went into improving hardware support on the existing machines and cleaning up contents for validation" * tag 'soc-dt-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (931 commits) arm64: dts: apm-shadowcat: Drop "apm,xgene2-pcie" compatible arm64: dts: apm-shadowcat: Move slimpro nodes out of "simple-bus" node ARM: dts: microchip: sam9x7: Add qspi controller arm64: dts: qcom: Add MST pixel streams for displayport arm64: dts: qcom: sm6350: correct DP compatibility strings arm64: dts: qcom: monaco-evk: Enable Adreno 623 GPU arm64: dts: qcom: qcs8300-ride: Enable Adreno 623 GPU arm64: dts: qcom: qcs8300: Add gpu and gmu nodes arm64: dts: allwinner: h313: Add Amediatech X96Q dt-bindings: arm: sunxi: Add Amediatech X96Q arm64: dts: apple: t8015: Add SPMI node arm64: dts: apple: t8012: Add SPMI node arm64: dts: apple: Add J180d (Mac Pro, M2 Ultra, 2023) device tree arm64: dts: rockchip: Add devicetree for the ROC-RK3588-RT dt-bindings: arm: rockchip: Add Firefly ROC-RK3588-RT arm64: dts: rockchip: update pinctrl names for Radxa E52C arm64: dts: rockchip: remove vcc_3v3_pmu regulator for Radxa E52C arm64: dts: apple: Add J474s, J475c and J475d device trees arm64: dts: apple: Add J414 and J416 Macbook Pro device trees arm64: dts: apple: Add initial t6020/t6021/t6022 DTs ...	2025-10-01 17:19:38 -07:00
Anup Patel	b385830290	dt-bindings: clock: Add RPMI clock service controller bindings ... Add device tree bindings for the RPMI clock service group based controller for the supervisor software. The RPMI clock service group is defined by the RISC-V platform management interface (RPMI) specification. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> Link: https://lore.kernel.org/r/20250818040920.272664-10-apatel@ventanamicro.com Signed-off-by: Paul Walmsley <pjw@kernel.org>	2025-09-25 13:16:42 -06:00
Anup Patel	54e184f0f5	dt-bindings: clock: Add RPMI clock service message proxy bindings ... Add device tree bindings for the RPMI clock service group based message proxy implemented by the SBI implementation (machine mode firmware or hypervisor). The RPMI clock service group is defined by the RISC-V platform management interface (RPMI) specification. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20250818040920.272664-9-apatel@ventanamicro.com Signed-off-by: Paul Walmsley <pjw@kernel.org>	2025-09-25 13:16:13 -06:00
Arnd Bergmann	17752efeca	Merge tag 'sunxi-dt-for-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt ... Allwinner Device Tree changes for 6.18 This tag contains two DT binding header changes that are shared with the clk tree. In this cycle we gained support for the MCU PRCM clock and reset controller on the A523/A527/T527 family of SoCs, the NPU which is a Vivante GC9000 IP block, and the NPU clock that was missing. The other PRCM clock controller gained default bus clock rate settings. These were not configured in the upstream U-boot bootloader, leading to them running at slower rates. The assigned rates are from the user manual. There is also a new board, the NetCube Systems Nagami SoM and two of its carrier boards. The A523 family development boards now have their internal RTC clocks configured correctly, so that the RTC does not drift wildly. The missing functions for the AXP717 on these boards are added. Missing reset GPIOs and delays for Ethernet PHYs are added. Last, the Cubie A5E now has its LEDs described and usable. An overlay for the Orange Pi Zero interface (addon) board was added. This can be used with the Orange Pi Zero and Zero Plus 2. Default audio routing for these two boards (to be used with the addon) were added to complement the overlay. * tag 'sunxi-dt-for-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: arm64: dts: allwinner: sun55i: Complete AXP717A sub-functions arm64: dts: allwinner: t527: orangepi-4a: hook up external 32k crystal arm64: dts: allwinner: t527: avaota-a1: hook up external 32k crystal arm64: dts: allwinner: a527: cubie-a5e: Drop external 32.768 KHz crystal arm64: dts: sun55i: a523: Assign standard clock rates to PRCM bus clocks ARM: dts: sunxi: add support for NetCube Systems Nagami Keypad Carrier ARM: dts: sunxi: add support for NetCube Systems Nagami Basic Carrier ARM: dts: sunxi: add support for NetCube Systems Nagami SoM riscv: dts: allwinner: d1s-t113: Add pinctrl's required by NetCube Systems Nagami SoM dt-bindings: arm: sunxi: Add NetCube Systems Nagami SoM and carrier board bindings ARM: dts: allwinner: Add Orange Pi Zero Interface Board overlay ARM: dts: allwinner: orangepi-zero-plus2: Add default audio routing ARM: dts: allwinner: orangepi-zero: Add default audio routing arm64: dts: allwinner: a523: Add NPU device node arm64: dts: allwinner: a523: Add MCU PRCM CCU node dt-bindings: clock: sun55i-a523-ccu: Add A523 MCU CCU clock controller dt-bindings: clock: sun55i-a523-ccu: Add missing NPU module clock arm64: dts: allwinner: t527: avaota-a1: Add ethernet PHY reset setting arm64: dts: allwinner: a527: cubie-a5e: Add ethernet PHY reset setting arm64: dts: allwinner: a527: cubie-a5e: Add LEDs Link: https://lore.kernel.org/r/aMrtuZg8HlR--TAt@wens.tw Signed-off-by: Arnd Bergmann <arnd@arndb.de>	2025-09-23 22:17:56 +02:00
Yao Zi	793e6b7480	dt-bindings: clock: loongson2: Add Loongson-2K0300 compatible ... Document the clock controller shipped in Loongson-2K0300 SoC, which generates various clock signals for SoC peripherals. Differing from previous generations of SoCs, LS2K0300 requires a 120MHz external clock input. Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Yanteng Si <siyanteng@cqsoftware.com.cn> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-09-21 12:48:30 -07:00
André Draszik	b92ef17f0c	dt-bindings: clock: samsung,s2mps11: add s2mpg10 ... The Samsung S2MPG10 clock controller is similar to the existing clock controllers supported by this binding. Register offsets / layout are slightly different, so it needs its own compatible. Acked-by: Stephen Boyd <sboyd@kernel.org> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: André Draszik <andre.draszik@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-09-21 10:43:16 -07:00
Gabriel Fernandez	099760708a	dt-bindings: stm32: cosmetic fixes for STM32MP25 clock and reset bindings ... - drop minItems from access-controllers - remove rcc label from example - fixes typos - remove double '::' from 'See also::' Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-09-21 10:31:57 -07:00
Gabriel Fernandez	49f6c8b74d	dt-bindings: stm32: add STM32MP21 clocks and reset bindings ... Adds clock and reset binding entries for STM32MP21 SoC family. Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-09-21 10:31:55 -07:00
Raphael Gallais-Pou	b52297f6eb	dt-bindings: clock: st: flexgen: remove deprecated compatibles ... st/stih407-clock.dtsi file has been removed in commit 65322c1daf51 ("clk: st: flexgen: remove unused compatible"). This file has three compatibles which are now dangling. Remove them from documentation. Signed-off-by: Raphael Gallais-Pou <rgallaispou@gmail.com> Reviewed-by: Brian Masney <bmasney@redhat.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-09-21 09:52:31 -07:00
Laura Nao	dd240e95f1	dt-bindings: clock: mediatek: Describe MT8196 clock controllers ... Introduce binding documentation for system clocks, functional clocks, and PEXTP0/1 and UFS reset controllers on MediaTek MT8196. This binding also includes a handle to the hardware voter, a fixed-function MCU designed to aggregate votes from the application processor and other remote processors to manage clocks and power domains. The HWV on MT8196/MT6991 is incomplete and requires software to manually enable power supplies, parent clocks, and FENC, as well as write to both the HWV MMIO and the controller registers. Because of these constraints, the HWV cannot be modeled using generic clock, power domain, or interconnect APIs. Instead, a custom phandle is exceptionally used to provide direct, syscon-like register access to drivers. Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Co-developed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Laura Nao <laura.nao@collabora.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-09-21 09:35:59 -07:00
Julien Massot	ac28c75986	dt-bindings: clock: mediatek: Add power-domains property ... The mt8183-mfgcfg node uses a power domain in its device tree node. To prevent schema validation warnings, add the optional `power-domains` property to the binding schema for mediatek syscon clocks. Fixes: 1781f2c461 ("arm64: dts: mediatek: mt8183: Add power-domains properity to mfgcfg") Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Julien Massot <julien.massot@collabora.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-09-19 22:45:07 -07:00
Duje Mihanović	5bcf9e1d0a	dt-bindings: clock: marvell,pxa1908: Add syscon compatible to apmu ... Add required syscon compatible and #power-domain-cells to the APMU controller. This is required for the SoC's power domain controller as the registers are shared. Device tree bindings for said power domains are also added. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Duje Mihanović <duje@dujemihanovic.xyz> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>	2025-09-17 16:09:14 +02:00
Rob Herring (Arm)	7c85e4da8c	dt-bindings: clock: silabs,si5341: Add missing properties ... Add "clock-output-names" which is a standard property for clock providers. Add the "always-on" boolean property which was undocumented, but already in use for some time. The flag prevents a clock output from being disabled. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Tested-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Michal Simek <michal.simek@amd.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-09-16 17:47:12 -07:00
Janne Grunau	ff0b47ab71	dt-bindings: clock: apple,nco: Add t6020-nco compatible ... After discussion with the devicetree maintainers we agreed to not extend lists with the generic compatible "apple,nco" anymore [1]. Use "apple,t8103-nco" as base compatible as it is the SoC the driver and bindings were written for. The block found on Apple's M2 Pro/Max/Ultra SoCs is compatible with "apple,t8103-nco" so add its per-SoC compatible with the former as fallback used by the existing driver. [1]: https://lore.kernel.org/asahi/12ab93b7-1fc2-4ce0-926e-c8141cfe81bf@kernel.org/ Reviewed-by: Neal Gompa <neal@gompa.dev> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Janne Grunau <j@jannau.net>	2025-09-14 21:51:01 +02:00
Chen-Yu Tsai	0f610e650d	dt-bindings: clock: sun55i-a523-ccu: Add A523 MCU CCU clock controller ... There are four clock controllers in the A523 SoC. The existing binding already covers two of them that are critical for basic operation. The remaining ones are the MCU clock controller and CPU PLL clock controller. Add a description for the MCU CCU. This unit controls and provides clocks to the MCU (RISC-V) subsystem and peripherals meant to operate under low power conditions. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20250911174710.3149589-3-wens@kernel.org Signed-off-by: Chen-Yu Tsai <wens@csie.org>	2025-09-13 13:49:09 +08:00
Denzeel Oliva	43bd82eb33	dt-bindings: clock: exynos990: Add PERIC0 and PERIC1 clock units ... Add clock management unit bindings for PERIC0 and PERIC1 blocks which provide clocks for USI, I2C and UART peripherals. Signed-off-by: Denzeel Oliva <wachiturroxd150@gmail.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>	2025-09-07 11:10:55 +02:00
Bjorn Andersson	154691e7c9	Merge branch '20250903-msm8937-v9-1-a097c91c5801@mainlining.org' into clk-for-6.18 ... Merge the MSM8937 global clock controller binding through a topic branch to allow merging the constants into the DeviceTree branch as well.	2025-09-04 08:38:00 -05:00
Barnabás Czémán	4d32c1f66a	dt-bindings: clock: qcom: Add MSM8937 Global Clock Controller ... Add device tree bindings for the global clock controller on Qualcomm MSM8937 platform. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org> Link: https://lore.kernel.org/r/20250903-msm8937-v9-1-a097c91c5801@mainlining.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2025-09-04 08:37:53 -05:00
Taniya Das	ee2d967030	dt-bindings: clock: qcom: document the Glymur Global Clock Controller ... Add device tree bindings for global clock controller on Glymur SoC. Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250825-glymur-clock-controller-v5-v5-6-01b8c8681bcd@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2025-09-03 18:15:43 -05:00
Taniya Das	ae5b84788e	dt-bindings: clock: qcom: Document the Glymur SoC TCSR Clock Controller ... The Glymur SoC TCSR block provides CLKREF clocks for EDP, PCIe and USB. Add this to the TCSR clock controller binding together with identifiers for the clocks. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250825-glymur-clock-controller-v5-v5-2-01b8c8681bcd@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2025-09-03 18:14:44 -05:00
Taniya Das	f9b007a96a	dt-bindings: clock: qcom-rpmhcc: Add support for Glymur SoCs ... Add bindings and update documentation compatible for RPMh clock controller on Glymur SoC. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250825-glymur-clock-controller-v5-v5-1-01b8c8681bcd@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2025-09-03 18:14:44 -05:00
Taniya Das	781c118c3e	dt-bindings: clock: Add DISPCC and reset controller for GLYMUR SoC ... Add the device tree bindings for the display clock controller which are required on Qualcomm Glymur SoC. Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250829-glymur-disp-clock-controllers-v1-1-0ce6fabd837c@oss.qualcomm.com [bjorn: Dropped unnecessary include in DT example] Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2025-09-03 17:13:16 -05:00
Hakyeong Kim	91f98de423	dt-bindings: clock: Add ARTPEC-8 clock controller ... Add dt-schema for Axis ARTPEC-8 SoC clock controller. The Clock Management Unit (CMU) has a top-level block CMU_CMU which generates clocks for other blocks. Add device-tree binding definitions for following CMU blocks: - CMU_CMU - CMU_BUS - CMU_CORE - CMU_CPUCL - CMU_FSYS - CMU_IMEM - CMU_PERI Signed-off-by: Hakyeong Kim <hgkim05@coasia.com> Signed-off-by: SeonGu Kang <ksk4725@coasia.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Ravi Patel <ravi.patel@samsung.com> Link: https://lore.kernel.org/r/20250825114436.46882-2-ravi.patel@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>	2025-08-31 15:22:10 +02:00
David Lechner	6793ca9a43	dt-bindings: clock: adi,axi-clkgen: add clock-output-names property ... Add an optional `clock-output-names` property to the ADI AXI Clock Generator binding. This is already being used in the Linux driver and real-world dtbs, so we should document it to allow for correct binding validation. Signed-off-by: David Lechner <dlechner@baylibre.com> Link: https://lore.kernel.org/r/20250811-dt-bindings-clk-axi-clkgen-add-clock-output-names-property-v1-1-f02727736aa7@baylibre.com Reviewed-by: Nuno Sá <nuno.sa@analog.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-08-13 11:41:32 -07:00
Rob Herring (Arm)	bedeb73fb9	dt-bindings: clock: Remove unused fujitsu,mb86s70-crg11 binding ... The fujitsu,mb86s70-crg11 binding is unused. The driver for it was removed in 2017. It's not used for Synquacer DT either like some other mb86s70 bindings are. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250804175304.3423965-1-robh@kernel.org Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-08-13 11:28:20 -07:00
Rob Herring (Arm)	7513cc3914	dt-bindings: clock: Convert silabs,si570 to DT schema ... Convert the Silicon Labs SI570 binding to DT schema format. It's a straight-forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250804222010.4082782-1-robh@kernel.org Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-08-13 11:02:06 -07:00
Rob Herring (Arm)	b02011c8c6	dt-bindings: clock: Convert silabs,si5341 to DT schema ... Convert the Silicon Labs SI5341 binding to DT schema format. It's a straight-forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250804222034.4083410-1-robh@kernel.org Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-08-13 11:01:37 -07:00
Rob Herring (Arm)	d903f5c60a	dt-bindings: clock: Convert silabs,si514/544 to DT schema ... Convert the Silicon Labs SI514 and SI544 bindings to DT schema format. Combine the bindings into a single schema as they are the same. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250804222042.4083656-1-robh@kernel.org Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-08-13 11:01:16 -07:00
Satya Priya Kakitapalli	be477c3924	dt-bindings: clock: qcom,videocc: Add sc8180x compatible ... The sc8180x video clock controller block is identical to that of sm8150. Add a new compatible string for sc8180x videocc and use sm8150 as fallback. Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250710-sc8180x-videocc-dt-v4-1-07a9d9d5e0e6@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2025-08-11 22:56:50 -05:00
Sricharan Ramabadhran	c17ccefb61	dt-bindings: clock: ipq5424-apss-clk: Add ipq5424 apss clock controller ... The CPU core in ipq5424 is clocked by a huayra PLL with RCG support. The RCG and PLL have a separate register space from the GCC. Also the L3 cache has a separate pll and needs to be scaled along with the CPU. Co-developed-by: Md Sadre Alam <quic_mdalam@quicinc.com> Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> [ Added interconnect related changes ] Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Link: https://lore.kernel.org/r/20250811090954.2854440-2-quic_varada@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2025-08-11 10:05:20 -05:00
Linus Torvalds	2d945dde7f	Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux ... Pull clk updates from Stephen Boyd: "This is the usual collection of primarily clk driver updates. The big part of the diff is all the new Qualcomm clk drivers added for a few SoCs they're working on. The other two vendors with significant work this cycle are Renesas and Amlogic. Renesas adds a bunch of clks to existing drivers and supports some new SoCs while Amlogic is starting a significant refactoring to simplify their code. The core framework gained a pair of helpers to get the 'struct device' or 'struct device_node' associated with a 'struct clk_hw'. Some associated KUnit tests were added for these simple helpers as well. Beyond that core change there are lots of little fixes throughout the clk drivers for the stuff we see every day, wrong clk driver data that affects tree topology or supported frequencies, etc. They're not found until the clks are actually used by some consumer device driver. New Drivers: - Global, display, gpu, video, camera, tcsr, and rpmh clock controller for the Qualcomm Milos SoC - Camera, display, GPU, and video clock controllers for Qualcomm QCS615 - Video clock controller driver for Qualcomm SM6350 - Camera clock controller driver for Qualcomm SC8180X - I3C clocks and resets on Renesas RZ/G3E - Expanded Serial Peripheral Interface (xSPI) clocks and resets on Renesas RZ/V2H(P) and RZ/V2N - SPI (RSPI) clocks and resets on Renesas RZ/V2H(P) - SDHI and I2C clocks on Renesas RZ/T2H and RZ/N2H - Ethernet clocks and resets on Renesas RZ/G3E - Initial support for the Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs - Ethernet clocks and resets on Renesas RZ/V2H and RZ/V2N - Timer, I2C, watchdog, GPU, and USB2.0 clocks and resets on Renesas RZ/V2N Updates: - Support atomic PWMs in the PWM clk driver - clk_hw_get_dev() and clk_hw_get_of_node() helpers - Replace round_rate() with determine_rate() in various clk drivers - Convert clk DT bindings to DT schema format for DT validation - Various clk driver cleanups and refactorings from static analysis tools and possibly real humans - A lot of little fixes here and there to things like clk tree topology, missing frequencies, flagging clks as critical, etc" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (216 commits) clk: clocking-wizard: Fix the round rate handling for versal clk: Fix typos clk: spacemit: ccu_pll: fix error return value in recalc_rate callback clk: tegra: periph: Make tegra_clk_periph_ops static clk: tegra: periph: Fix error handling and resolve unsigned compare warning clk: imx: scu: convert from round_rate() to determine_rate() clk: imx: pllv4: convert from round_rate() to determine_rate() clk: imx: pllv3: convert from round_rate() to determine_rate() clk: imx: pllv2: convert from round_rate() to determine_rate() clk: imx: pll14xx: convert from round_rate() to determine_rate() clk: imx: pfd: convert from round_rate() to determine_rate() clk: imx: frac-pll: convert from round_rate() to determine_rate() clk: imx: fracn-gppll: convert from round_rate() to determine_rate() clk: imx: fixup-div: convert from round_rate() to determine_rate() clk: imx: cpu: convert from round_rate() to determine_rate() clk: imx: busy: convert from round_rate() to determine_rate() clk: imx: composite-93: remove round_rate() in favor of determine_rate() clk: imx: composite-8m: remove round_rate() in favor of determine_rate() clk: qcom: Remove redundant pm_runtime_mark_last_busy() calls clk: imx: Remove redundant pm_runtime_mark_last_busy() calls ...	2025-07-31 13:36:27 -07:00
Linus Torvalds	24e5c3241a	Merge tag 'mfd-next-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd ... Pull MFD updates from Lee Jones: "New Support & Features: - Add extensive support for the Analog Devices ADP5589 I/O expander, including core MFD, GPIO, PWM, and a new keypad matrix input driver. This also adds support for handling various events including GPI, keypad, reset and unlock ev ents - Add support for the TI TPS652G1 PMIC, a stripped-down version of the TPS65224, including core MFD, PFSM, pinctrl, and GPIO support - Add support for the Apple Silicon System Management Controller (SMC), including the core MFD driver which handles the RTKit-based protocol, a new GPIO driver for PMU GPIOs, and a new reboot/power-off driver. Improvements & Fixes: - Dynamically add ADP5585 sub-devices based on device tree properties - Move ADP5585 oscillator control from the child PWM driver to the main MFD driver to better handle shared resources - Add support for a hardware reset pin and VDD regulator to the ADP5585 driver - Update the TPS65219 MFD cell's GPIO compatible string for the TPS65214 to reflect hardware capabilities correctly - Separate the ChromeOS EC charge-control probing from the USB-PD subsystem, allowing it to probe independently based on the dedicated EC_FEATURE_CHARGER - Fix an interrupt naming typo in the MT6370 driver - Fix RK806 PMIC reset behavior by allowing the reset mode to be customized via a new device tree property - Fix AXP20X regulator cell ID conflicts for secondary PMICs on boards without an IRQ line connected - Fix MT6397 keypad sub-device creation to use specific names instead of a generic one, ensuring correct driver binding - Fix a build warning in the stm32-timers driver by adding a missing include for export.h. Cleanups & Refactoring: - Refactor the ADP5585 driver to simplify how regmap defaults are handled, making it easier to add new chip variants - Introduce per-chip register map structures for the ADP5585/ADP5589 family to handle differences between the devices - Convert several drivers to use dev_fwnode() instead of of_fwnode_handle() - Make various static structures const in the cs40l50, rohm-bd71828, tps65219, and twl6040 drivers - Remove redundant pm_runtime_mark_last_busy() calls from several drivers - Alphabetize Kconfig entries for Cirrus Logic and Maxim drivers - Remove unused fields from the 'tps65219' struct - Update several MFD-related headers to follow the 'Include What You Use' (IWYU) principle. Removals: - Remove the old, platform-data-based adp5589-keys input driver, which is now superseded by the new MFD-based adp5585-keys driver - Remove the unused twl6030_mmc_card_detect() functions and associated header declarations - Remove the now unused pcf50633/core.h header file - Remove the fsl,imx8qxp-csr device tree binding, which was being used incorrectly. Device Tree Bindings Updates: - Add support for the Analog Devices ADP5589 I/O expander to the adi,adp5585.yaml binding - Add new properties to the adi,adp5585.yaml binding for input events, including keypad pins, unlock events, and reset events - Add a reset-gpios property to the adi,adp5585.yaml binding - Add the TI TPS652G1 PMIC to the ti,tps6594.yaml binding - Add new bindings for the Apple Mac System Management Controller (SMC) and its sub-devices: apple,smc.yaml, apple,smc-gpio.yaml, and apple,smc-reboot.yaml - Convert the Freescale MXS LRADC binding (mxs-lradc) to YAML schema format - Convert and combine the NXP LPC1850 CREG, DMAMUX, and USB OTG PHY bindings into a single YAML schema file - Convert the TI TPS65910 binding to YAML schema format - Add a comment to the samsung,s2mps11.yaml binding to clarify the use of 'oneOf' for interrupt properties - Add the rockchip,reset-mode property to the rockchip,rk806.yaml binding to allow customization of the PMIC's reset behavior" * tag 'mfd-next-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (28 commits) mfd: dt-bindings: Convert TPS65910 to DT schema mfd: Minor Cirrus/Maxim Kconfig order fixes mfd: Remove redundant pm_runtime_mark_last_busy() calls mfd: mt6397: Do not use generic name for keypad sub-devices mfd: axp20x: Set explicit ID for regulator cell if no IRQ line is present mfd: mt6370: Fix the interrupt naming typo mfd: rk8xx-core: Allow to customize RK806 reset mode dt-bindings: mfd: rk806: Allow to customize PMIC reset mode mfd: syscon: atmel-smc: Don't use "proxy" headers mfd: madera: Don't use "proxy" headers mfd: wm8350-core: Don't use "proxy" headers dt-bindings: mfd: samsung,s2mps11: Add comment about interrupts properties mfd: davinci_voicecodec: Don't use "proxy" headers mfd: pcf50633: Remove the header file core.h mfd: tps65219: Remove another unused field from 'struct tps65219' mfd: tps65219: Remove an unused field from 'struct tps65219' mfd: tps65219: Constify struct regmap_irq_sub_irq_map and tps65219_chip_data mfd: rohm-bd71828: Constify some structures dt-bindings: mfd: fsl,imx8qxp-csr: Remove binding documentation mfd: axp20x: Set explicit ID for AXP313 regulator ...	2025-07-31 11:50:25 -07:00
Linus Torvalds	f1aa129d80	Merge tag 'mips_6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux ... Pull MIPS updates from Thomas Bogendoerfer: - DT updates for ralink, mobileye and atheros/qualcomm - Clean up of mc146818 usage - Speed up delay calibration for CPS - Other cleanups and fixes * tag 'mips_6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (50 commits) MIPS: Don't use %pK through printk MIPS: Update Joshua Kinard's e-mail address MIPS: mobileye: dts: eyeq5,eyeq6h: rename the emmc controller MIPS: mm: tlb-r4k: Uniquify TLB entries on init MIPS: SGI-IP27: Delete an unnecessary check before kfree() in hub_domain_free() mips/malta,loongson2ef: use generic mc146818_get_time function mips: remove redundant macro mc146818_decode_year mips/mach-rm: remove custom mc146818rtc.h file mips: remove unused function mc146818_set_rtc_mmss MIPS: CPS: Optimise delay CPU calibration for SMP MIPS: CPS: Improve mips_cps_first_online_in_cluster() MIPS: disable MMID when not supported by the hardware MIPS: eyeq5_defconfig: add I2C subsystem, driver and temp sensor driver MIPS: eyeq5_defconfig: add GPIO subsystem & driver MIPS: mobileye: eyeq5: add two GPIO bank nodes MIPS: mobileye: eyeq5: add evaluation board I2C temp sensor MIPS: mobileye: eyeq5: add 5 I2C controller nodes MIPS: eyeq5_defconfig: Update for v6.16-rc1 MIPS: vpe-mt: add missing prototypes for vpe_{alloc,start,stop,free} mips: boot: use 'targets' instead of extra-y in Makefile ...	2025-07-31 11:08:55 -07:00
Stephen Boyd	64c21f253a	Merge branch 'clk-fixes' into clk-next ... Resolve conflicts with i.MX95 changes 88768d6f8c ("clk: imx95-blk-ctl: Rename lvds and displaymix csr blk") in clk-imx and aacc875a44 ("clk: imx: Fix an out-of-bounds access in dispmix_csr_clk_dev_data") in clk-fixes. * clk-fixes: clk: sunxi-ng: v3s: Fix TCON clock parents clk: sunxi-ng: v3s: Fix CSI1 MCLK clock name clk: sunxi-ng: v3s: Fix CSI SCLK clock name dt-bindings: clock: mediatek: Add #reset-cells property for MT8188 clk: imx: Fix an out-of-bounds access in dispmix_csr_clk_dev_data clk: scmi: Handle case where child clocks are initialized before their parents clk: sunxi-ng: a523: Mark MBUS clock as critical	2025-07-31 09:10:06 -07:00
Stephen Boyd	c30cc9ffc1	Merge branches 'clk-rockchip', 'clk-thead', 'clk-microchip', 'clk-imx' and 'clk-qcom' into clk-next ... * clk-rockchip: clk: rockchip: rk3568: Add PLL rate for 132MHz * clk-thead: clk: thead: th1520-ap: Describe mux clocks with clk_mux clk: thead: th1520-ap: Correctly refer the parent of osc_12m clk: thead: Mark essential bus clocks as CLK_IGNORE_UNUSED * clk-microchip: clk: at91: sam9x7: update pll clk ranges * clk-imx: MAINTAINERS: Update i.MX Clock Entry clk: imx95-blk-ctl: Add clock for i.MX94 LVDS/Display CSR clk: imx95-blk-ctl: Rename lvds and displaymix csr blk clk: imx95-blk-ctl: Fix synchronous abort dt-bindings: clock: Add support for i.MX94 LVDS/DISPLAY CSR clk: imx: Fix an out-of-bounds access in dispmix_csr_clk_dev_data * clk-qcom: (65 commits) dt-bindings: clock: qcom,sm4450-dispcc: Reference qcom,gcc.yaml dt-bindings: clock: qcom,sm4450-camcc: Reference qcom,gcc.yaml dt-bindings: clock: qcom,mmcc: Reference qcom,gcc.yaml dt-bindings: clock: qcom,sm8150-camcc: Reference qcom,gcc.yaml dt-bindings: clock: qcom: Remove double colon from description clk: qcom: Add Video Clock controller (VIDEOCC) driver for Milos dt-bindings: clock: qcom: document the Milos Video Clock Controller clk: qcom: Add Graphics Clock controller (GPUCC) driver for Milos dt-bindings: clock: qcom: document the Milos GPU Clock Controller clk: qcom: Add Display Clock controller (DISPCC) driver for Milos dt-bindings: clock: qcom: document the Milos Display Clock Controller clk: qcom: Add Camera Clock controller (CAMCC) driver for Milos dt-bindings: clock: qcom: document the Milos Camera Clock Controller clk: qcom: Add Global Clock controller (GCC) driver for Milos dt-bindings: clock: qcom: document the Milos Global Clock Controller clk: qcom: common: Add support to register rcg dfs in qcom_cc_really_probe clk: qcom: gcc-x1e80100: Add missing video resets dt-bindings: clock: qcom,x1e80100-gcc: Add missing video resets clk: qcom: videocc-sm8550: Add separate frequency tables for X1E80100 clk: qcom: videocc-sm8550: Allow building without SM8550/SM8560 GCC ...	2025-07-29 15:19:17 -07:00
Stephen Boyd	e3abdd1870	Merge branches 'clk-renesas', 'clk-samsung', 'clk-spacemit', 'clk-allwinner' and 'clk-amlogic' into clk-next ... * clk-renesas: (42 commits) clk: renesas: r9a08g045: Add MSTOP for coupled clocks as well clk: renesas: r9a09g047: Add clock and reset signals for the GBETH IPs clk: renesas: r9a09g057: Add XSPI clock/reset clk: renesas: r9a09g056: Add XSPI clock/reset clk: renesas: rzv2h: Add fixed-factor module clocks with status reporting clk: renesas: r9a09g057: Add support for xspi mux and divider clk: renesas: r9a09g056: Add support for xspi mux and divider clk: renesas: r9a09g077: Add RIIC module clocks clk: renesas: r9a09g077: Add PLL2 and SDHI clock support clk: renesas: rzv2h: Drop redundant base pointer from pll_clk clk: renesas: r9a09g057: Add entries for the RSPIs dt-bindings: clock: renesas,r9a09g077/87: Add SDHI_CLKHS clock ID dt-bindings: clock: renesas,r9a09g056/57-cpg: Add XSPI core clock clk: renesas: rzv2h: Add missing include file clk: renesas: rzv2h: Use devm_kmemdup_array() clk: renesas: Add CPG/MSSR support to RZ/N2H SoC clk: renesas: r9a09g077: Add PCLKL core clock dt-bindings: clock: renesas,cpg-mssr: Document RZ/N2H support dt-bindings: soc: renesas: Document RZ/N2H (R9A09G087) SoC dt-bindings: clock: renesas,r9a09g077: Add PCLKL core clock ID ... * clk-samsung: clk: samsung: exynosautov920: add block hsi2 clock support dt-bindings: clock: exynosautov920: add hsi2 clock definitions dt-bindings: clock: exynosautov920: sort clock definitions clk: samsung: exynos850: fix a comment clk: samsung: gs101: fix alternate mout_hsi0_usb20_ref parent clock clk: samsung: gs101: fix CLK_DOUT_CMU_G3D_BUSD * clk-spacemit: clk: spacemit: ccu_pll: fix error return value in recalc_rate callback reset: spacemit: add support for SpacemiT CCU resets clk: spacemit: mark K1 pll1_d8 as critical clk: spacemit: define three reset-only CCUs clk: spacemit: set up reset auxiliary devices soc: spacemit: create a header for clock/reset registers dt-bindings: soc: spacemit: define spacemit,k1-ccu resets * clk-allwinner: clk: sunxi-ng: ccu_nm: convert from round_rate() to determine_rate() clk: sunxi-ng: ccu_nkmp: convert from round_rate() to determine_rate() clk: sunxi-ng: ccu_nk: convert from round_rate() to determine_rate() clk: sunxi-ng: ccu_gate: convert from round_rate() to determine_rate() clk: sunxi-ng: v3s: Assign the de and tcon clocks to the video pll clk: sunxi-ng: v3s: Fix de clock definition clk: sunxi-ng: sun55i-a523-r-ccu: Add missing PPU0 reset dt-bindings: reset: sun55i-a523-r-ccu: Add missing PPU0 reset * clk-amlogic: clk: amlogic: s4: remove unused data clk: amlogic: drop clk_regmap tables clk: amlogic: get regmap with clk_regmap_init clk: amlogic: remove unnecessary headers clk: amlogic: axg-audio: use the auxiliary reset driver	2025-07-29 15:18:33 -07:00
Linus Torvalds	115e74a29b	Merge tag 'soc-dt-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc ... Pull SoC devicetree updates from Arnd Bergmann: "There are a few new variants of existing chips: - mt6572 is an older mobile phone chip from mediatek that was extremely popular a decade ago but never got upstreamed until now - exynos2200 is a recent high-end mobile phone chip used in a few Samsung phones like the Galaxy S22 - Renesas R-Car V4M-7 (R8A779H2) is an updated version of R-Car V4M (R8A779H0) and used in automotive applications - Tegra264 is a new chip from NVIDIA, but support is fairly minimal for now, and not much information is public about it There are five more chips in a separate branch, as those are new chip families that I merged along with the necessary infrastructure. New board support is not that exciting, with a total of 33 newly added machines here: - Evaluation platforms for the chips above, plus TI am62d2 and Sophgo sg2042 - Six 32-bit industrial boards based on stm32, imx6 and am33 chips, plus eight 64-bit rockchips rk33xx/rk35xx, am62d2, t527, imx8 and imx95 - Two newly added ASPEED BMC based motherboards, and one that got removed - Phones and Tablets based on 32-bit mt6572, tegra30 and 64-bit msm8976 SoCs - Three Laptops based on Mediatek mt8186 and Qualcomm Snapdragon X1 - A set-top box based on Amlogic meson-gxm Updates for existing machines are spread over all the above families. One notable change here is support for the RP1 I/O chip used in Raspberry Pi 5" * tag 'soc-dt-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (606 commits) riscv: dts: sophgo: fix mdio node name for CV180X riscv: dts: sophgo: sophgo-srd3-10: reserve uart0 device riscv: dts: sophgo: add Sophgo SG2042_EVB_V2.0 board device tree riscv: dts: sophgo: add Sophgo SG2042_EVB_V1.X board device tree dt-bindings: riscv: add Sophgo SG2042_EVB_V1.X/V2.0 bindings riscv: dts: sophgo: add ethernet GMAC device for sg2042 riscv: dts: sophgo: Enable ethernet device for Huashan Pi riscv: dts: sophgo: Add mdio multiplexer device for cv18xx riscv: dts: sophgo: Add ethernet device for cv18xx riscv: dts: sophgo: sg2044: add pmu configuration riscv: dts: sophgo: sg2044: add ziccrse extension riscv: dts: sophgo: add zfh for sg2042 riscv: dts: sophgo: add ziccrse for sg2042 riscv: dts: sophgo: Add xtheadvector to the sg2042 devicetree riscv: dts: sophgo: sg2044: add PCIe device support for SG2044 riscv: dts: sophgo: sg2044: add MSI device support for SG2044 riscv: dts: sophgo: add reset configuration for Sophgo CV1800 series SoC riscv: dts: sophgo: add reset generator for Sophgo CV1800 series SoC dt-bindings: soc: sophgo: Move SoCs/boards from riscv into soc, add SG2000 riscv: dts: sophgo: sg2044: Add missing riscv,cbop-block-size property ...	2025-07-29 11:04:52 -07:00
Frank Li	17a6d7cece	dt-bindings: clock: convert lpc1850-cgu.txt to yaml format ... Convert lpc1850-cgu.txt to yaml format. Additional changes: - remove extra clock source nodes in example. - remove clock consumer in example. - remove clock-output-names and clock-clock-indices from required list to match existed dts. Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20250606162410.1361169-1-Frank.Li@nxp.com Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-07-24 14:26:01 -07:00
Rob Herring (Arm)	3849ceec49	dt-bindings: clock: Convert qca,ath79-pll to DT schema ... Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250630232625.3700213-1-robh@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-07-24 14:19:46 -07:00
Rob Herring (Arm)	71b80a3365	dt-bindings: clock: Convert nuvoton,npcm750-clk to DT schema ... Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250630232637.3700584-1-robh@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-07-24 14:19:42 -07:00