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dt-bindings: clock: marvell,pxa1908: Add syscon compatible to apmu

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Add required syscon compatible and #power-domain-cells to the APMU
controller. This is required for the SoC's power domain controller as
the registers are shared.

Device tree bindings for said power domains are also added.

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Duje Mihanović <duje@dujemihanovic.xyz>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Duje Mihanović
2025-09-13 23:12:48 +02:00
committed by Ulf Hansson
parent 9428fff44f
commit 5bcf9e1d0a
3 changed files with 42 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

30
Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml
View File

@@ -19,11 +19,14 @@ description: |
properties:
compatible:
enum:
- marvell,pxa1908-apbc
- marvell,pxa1908-apbcp
- marvell,pxa1908-mpmu
- marvell,pxa1908-apmu
oneOf:
- enum:
- marvell,pxa1908-apbc
- marvell,pxa1908-apbcp
- marvell,pxa1908-mpmu
- items:
- const: marvell,pxa1908-apmu
- const: syscon
reg:
maxItems: 1
@@ -31,6 +34,9 @@ properties:
'#clock-cells':
const: 1
'#power-domain-cells':
const: 1
required:
- compatible
- reg
@@ -38,11 +44,23 @@ required:
additionalProperties: false
if:
not:
properties:
compatible:
contains:
const: marvell,pxa1908-apmu
then:
properties:
'#power-domain-cells': false
examples:
# APMU block:
- |
clock-controller@d4282800 {
compatible = "marvell,pxa1908-apmu";
compatible = "marvell,pxa1908-apmu", "syscon";
reg = <0xd4282800 0x400>;
#clock-cells = <1>;
#power-domain-cells = <1>;
};

1
MAINTAINERS
View File

@@ -2872,6 +2872,7 @@ S: Maintained
F: arch/arm64/boot/dts/marvell/mmp/
F: drivers/clk/mmp/clk-pxa1908*.c
F: include/dt-bindings/clock/marvell,pxa1908.h
F: include/dt-bindings/power/marvell,pxa1908-power.h
ARM/Mediatek RTC DRIVER
M: Eddie Huang <eddie.huang@mediatek.com>

17
include/dt-bindings/power/marvell,pxa1908-power.h Normal file
View File

@@ -0,0 +1,17 @@
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
/*
* Marvell PXA1908 power domains
*
* Copyright 2025, Duje Mihanović <duje@dujemihanovic.xyz>
*/
#ifndef __DTS_MARVELL_PXA1908_POWER_H
#define __DTS_MARVELL_PXA1908_POWER_H
#define PXA1908_POWER_DOMAIN_VPU 0
#define PXA1908_POWER_DOMAIN_GPU 1
#define PXA1908_POWER_DOMAIN_GPU2D 2
#define PXA1908_POWER_DOMAIN_DSI 3
#define PXA1908_POWER_DOMAIN_ISP 4
#endif