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Author SHA1 Message Date
Taniya Das
313e290902 clk: qcom: gpucc-sm8350: Park RCG's clk source at XO during disable 
The RCG's clk src has to be parked at XO while disabling as per the
HW recommendation, hence use clk_rcg2_shared_ops to achieve the same.

Fixes: 160758b05a ("clk: qcom: add support for SM8350 GPUCC")
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # SM8350-HDK
Link: https://lore.kernel.org/r/20240621-sm8350-gpucc-fixes-v1-1-22db60c7c5d3@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-06-23 15:52:56 -05:00
Luo Jie
b45120fbd3 clk: qcom: nsscc-qca8k: Fix the MDIO functions undefined issue 
The clock controller driver of QCA8K depends on MDIO_BUS because
of mdio_module_driver used to register the driver.

This patch fixes the following undefined symbols.
ERROR: modpost: "mdio_driver_register"
[drivers/clk/qcom/nsscc-qca8k.ko] undefined!
ERROR: modpost: "mdio_driver_unregister"
[drivers/clk/qcom/nsscc-qca8k.ko] undefined!
ERROR: modpost: "__mdiobus_write"
[drivers/clk/qcom/nsscc-qca8k.ko] undefined!
ERROR: modpost: "__mdiobus_read"
[drivers/clk/qcom/nsscc-qca8k.ko] undefined!

Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202406161634.B27sOs8B-lkp@intel.com/
Closes: https://lore.kernel.org/oe-kbuild-all/202406162047.QkUMa2fG-lkp@intel.com/
Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
Link: https://lore.kernel.org/r/20240617093806.3461165-1-quic_luoj@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-06-21 00:54:39 -05:00
Lukas Bulwahn
f8d1dca6c4 clk: qcom: select right config in CLK_QCM2290_GPUCC definition 
Commit 8cab033628 ("clk: qcom: Add QCM2290 GPU clock controller driver")
adds the config CLK_QCM2290_GPUCC, which intends to select the support for
the QCM2290 Global Clock Controller. It however selects the non-existing
config CLK_QCM2290_GCC, whereas the config for the QCM2290 Global Clock
Controller is named QCM_GCC_2290.

Adjust the config to the intended one.

Signed-off-by: Lukas Bulwahn <lukas.bulwahn@redhat.com>
Fixes: 8cab033628 ("clk: qcom: Add QCM2290 GPU clock controller driver")
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240620201431.93254-1-lukas.bulwahn@redhat.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-06-21 00:50:09 -05:00
Elliot Berman
e429be706f clk: qcom: Remove QCOM_RPMCC symbol 
This symbol is selected by a couple drivers, but isn't used by anyone
and hasn't been for years now. Drop it.

No functional change intended.

Signed-off-by: Elliot Berman <quic_eberman@quicinc.com>
Reviewed-by: Mike Tipton <quic_mdtipton@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240619-drop-qcom-rpmcc-v1-1-b487c95162ef@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-06-21 00:47:55 -05:00
Konrad Dybcio
8cab033628 clk: qcom: Add QCM2290 GPU clock controller driver 
Add a driver for the GPU clock controller block found on the QCM2290 SoC.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240606-topic-rb1_gpu-v4-3-4bc0c19da4af@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-06-13 18:03:02 -05:00
Konrad Dybcio
d4d74e4b30 clk: qcom: clk-alpha-pll: Add HUAYRA_2290 support 
Commit 134b55b7e1 ("clk: qcom: support Huayra type Alpha PLL")
introduced an entry to the alpha offsets array, but diving into QCM2290
downstream and some documentation, it turned out that the name Huayra
apparently has been used quite liberally across many chips, even with
noticeably different hardware.

Introduce another set of offsets and a new configure function for the
Huayra PLL found on QCM2290. This is required e.g. for the consumers
of GPUCC_PLL0 to properly start.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240606-topic-rb1_gpu-v4-2-4bc0c19da4af@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-06-12 23:06:52 -05:00
Bjorn Andersson
ea5594aa3e Merge branch '20240606-topic-rb1_gpu-v4-1-4bc0c19da4af@linaro.org' into clk-for-6.11 
Merge the QCM2290 GPUCC binding through a topic branch to allow for it
to also be merged into the DeviceTree branch.
 2024-06-12 23:06:18 -05:00
Konrad Dybcio
525b42832b dt-bindings: clock: Add Qcom QCM2290 GPUCC 
Add device tree bindings for graphics clock controller for Qualcomm
Technology Inc's QCM2290 SoCs.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240606-topic-rb1_gpu-v4-1-4bc0c19da4af@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-06-12 23:06:10 -05:00
Luo Jie
2441b965c4 clk: qcom: add clock controller driver for qca8386/qca8084 
The clock controller driver of qca8386/qca8084 is registered
as the MDIO device, the hardware register is accessed by MDIO bus
that is normally used to access general PHY device, which is
different from the current existed qcom clock controller drivers
using ioremap to access hardware clock registers, nsscc-qca8k is
accessed via an MDIO bus.

MDIO bus is commonly utilized by both qca8386/qca8084 and other
PHY devices, so the mutex lock mdio_bus->mdio_lock should be
used instead of using the mutex lock of remap.

To access the hardware clock registers of qca8386/qca8084, there
is a special MDIO frame sequence, which needs to be sent to the
device.

Enable the reference clock before resetting the clock controller,
the reference clock rate is fixed to 50MHZ.

Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
Link: https://lore.kernel.org/r/20240605124541.2711467-5-quic_luoj@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-06-12 23:04:26 -05:00
Luo Jie
9f93a0a428 clk: qcom: common: commonize qcom_cc_really_probe 
The previous wrapper qcom_cc_really_probe takes the platform
device as parameter, which is limited to platform driver.

As for qca8k clock controller driver, which is registered as
the MDIO device, which also follows the qcom clock framework.

To commonize qcom_cc_really_probe, updating it to take the
struct device as parameter, so that the qcom_cc_really_probe
can be utilized by the previous platform device and the new
added MDIO device.

Also update the current clock controller drivers to take
&pdev->dev as parameter when calling qcom_cc_really_probe.

Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Tested-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
Link: https://lore.kernel.org/r/20240605124541.2711467-4-quic_luoj@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-06-12 23:04:26 -05:00
Luo Jie
80bbd1c355 dt-bindings: clock: add qca8386/qca8084 clock and reset definitions 
QCA8386/QCA8084 includes the clock & reset controller that is
accessed by MDIO bus. Two work modes are supported, qca8386 works
as switch mode, qca8084 works as PHY mode.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
Link: https://lore.kernel.org/r/20240605124541.2711467-3-quic_luoj@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-06-12 23:04:26 -05:00
Luo Jie
7311bbfff3 clk: qcom: branch: Add clk_branch2_prepare_ops 
Add the clk_branch2_prepare_ops for supporting clock controller
where the hardware register is accessed by MDIO bus, and the
spin lock can't be used because of sleep during the MDIO
operation.

The clock is enabled by the .prepare instead of .enable when
the clk_branch2_prepare_ops is used.

Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
Link: https://lore.kernel.org/r/20240605124541.2711467-2-quic_luoj@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-06-12 23:04:26 -05:00
Krzysztof Kozlowski
7e828d77d2 dt-bindings: clock: qcom,sm8450-gpucc: reference qcom,gcc.yaml 
Just like most of Qualcomm clock controllers, we can reference common
qcom,gcc.yaml schema to unify the common parts of the binding.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240605-dt-bindings-qcom-gcc-v2-16-f947b24f1283@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-06-12 23:03:13 -05:00
Krzysztof Kozlowski
4da364c759 dt-bindings: clock: qcom,sm8550-dispcc: reference qcom,gcc.yaml 
Just like most of Qualcomm clock controllers, we can reference common
qcom,gcc.yaml schema to unify the common parts of the binding.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240605-dt-bindings-qcom-gcc-v2-15-f947b24f1283@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-06-12 23:03:13 -05:00
Krzysztof Kozlowski
8acff345c3 dt-bindings: clock: qcom,sm8450-dispcc: reference qcom,gcc.yaml 
Just like most of Qualcomm clock controllers, we can reference common
qcom,gcc.yaml schema to unify the common parts of the binding.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240605-dt-bindings-qcom-gcc-v2-14-f947b24f1283@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-06-12 23:03:13 -05:00
Krzysztof Kozlowski
7b69a903fc dt-bindings: clock: qcom,sm6115-dispcc: reference qcom,gcc.yaml 
Just like most of Qualcomm clock controllers, we can reference common
qcom,gcc.yaml schema to unify the common parts of the binding.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240605-dt-bindings-qcom-gcc-v2-13-f947b24f1283@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-06-12 23:03:13 -05:00
Krzysztof Kozlowski
4ef61bcf1a dt-bindings: clock: qcom,sdm845-dispcc: reference qcom,gcc.yaml 
Just like most of Qualcomm clock controllers, we can reference common
qcom,gcc.yaml schema to unify the common parts of the binding.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240605-dt-bindings-qcom-gcc-v2-12-f947b24f1283@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-06-12 23:03:13 -05:00
Krzysztof Kozlowski
c9ae35ace8 dt-bindings: clock: qcom,sc7280-dispcc: reference qcom,gcc.yaml 
Just like most of Qualcomm clock controllers, we can reference common
qcom,gcc.yaml schema to unify the common parts of the binding.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240605-dt-bindings-qcom-gcc-v2-11-f947b24f1283@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-06-12 23:03:13 -05:00
Krzysztof Kozlowski
e68a21bd18 dt-bindings: clock: qcom,sc7180-dispcc: reference qcom,gcc.yaml 
Just like most of Qualcomm clock controllers, we can reference common
qcom,gcc.yaml schema to unify the common parts of the binding.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240605-dt-bindings-qcom-gcc-v2-10-f947b24f1283@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-06-12 23:03:13 -05:00
Krzysztof Kozlowski
a8197afc44 dt-bindings: clock: qcom,qcm2290-dispcc: reference qcom,gcc.yaml 
Just like most of Qualcomm clock controllers, we can reference common
qcom,gcc.yaml schema to unify the common parts of the binding.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240605-dt-bindings-qcom-gcc-v2-9-f947b24f1283@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-06-12 23:03:13 -05:00
Krzysztof Kozlowski
fa02399d69 dt-bindings: clock: qcom,msm8998-gpucc: reference qcom,gcc.yaml 
Just like most of Qualcomm clock controllers, we can reference common
qcom,gcc.yaml schema to unify the common parts of the binding.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240605-dt-bindings-qcom-gcc-v2-8-f947b24f1283@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-06-12 23:03:13 -05:00
Krzysztof Kozlowski
f68872fe10 dt-bindings: clock: qcom,gpucc: reference qcom,gcc.yaml 
Just like most of Qualcomm clock controllers, we can reference common
qcom,gcc.yaml schema to unify the common parts of the binding.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240605-dt-bindings-qcom-gcc-v2-7-f947b24f1283@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-06-12 23:03:13 -05:00
Krzysztof Kozlowski
b20b9a7626 dt-bindings: clock: qcom,gpucc-sdm660: reference qcom,gcc.yaml 
Just like most of Qualcomm clock controllers, we can reference common
qcom,gcc.yaml schema to unify the common parts of the binding.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240605-dt-bindings-qcom-gcc-v2-6-f947b24f1283@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-06-12 23:03:13 -05:00
Krzysztof Kozlowski
5576b6f8e9 dt-bindings: clock: qcom,dispcc-sm8x50: reference qcom,gcc.yaml 
Just like most of Qualcomm clock controllers, we can reference common
qcom,gcc.yaml schema to unify the common parts of the binding.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240605-dt-bindings-qcom-gcc-v2-5-f947b24f1283@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-06-12 23:03:13 -05:00
Krzysztof Kozlowski
f168430195 dt-bindings: clock: qcom,dispcc-sm6350: reference qcom,gcc.yaml 
Just like most of Qualcomm clock controllers, we can reference common
qcom,gcc.yaml schema to unify the common parts of the binding.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240605-dt-bindings-qcom-gcc-v2-4-f947b24f1283@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-06-12 23:03:13 -05:00
Krzysztof Kozlowski
cc9d138fff dt-bindings: clock: qcom,dispcc-sc8280xp: reference qcom,gcc.yaml 
Just like most of Qualcomm clock controllers, we can reference common
qcom,gcc.yaml schema to unify the common parts of the binding.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240605-dt-bindings-qcom-gcc-v2-3-f947b24f1283@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-06-12 23:03:13 -05:00
Krzysztof Kozlowski
3b39fb00be dt-bindings: clock: qcom,videocc: reference qcom,gcc.yaml 
Just like most of Qualcomm clock controllers, we can reference common
qcom,gcc.yaml schema to unify the common parts of the binding.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240605-dt-bindings-qcom-gcc-v2-2-f947b24f1283@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-06-12 23:03:12 -05:00
Krzysztof Kozlowski
acc4101466 dt-bindings: clock: qcom,sm8450-videocc: reference qcom,gcc.yaml 
Just like most of Qualcomm clock controllers, we can reference common
qcom,gcc.yaml schema to unify the common parts of the binding.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240605-dt-bindings-qcom-gcc-v2-1-f947b24f1283@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-06-12 23:03:12 -05:00
Dmitry Baryshkov
e81e9a845b dt-bindings: clock: add schema for qcom,gcc-mdm9615 
Add schema for the Global Clock Controller (GCC) present on the Qualcomm
MDM9615 platform.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240529-qcom-gdscs-v2-3-69c63d0ae1e7@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-05-31 18:07:30 -05:00
Dmitry Baryshkov
b0ef3434da dt-bindings: clock: qcom,gcc: sort out power-domains support 
On some of Qualcomm platforms the Global Clock Controller (GCC) doesn't
provide power domains. Move requirement for the '#power-domain-cells'
out of the common qcom,gcc.yaml into individual schema files. For the
platforms that do not provide power-domains, explicitly forbid having
the '#power-domain-cells' property.

Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240529-qcom-gdscs-v2-2-69c63d0ae1e7@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-05-31 18:07:30 -05:00
Dmitry Baryshkov
d99c899d2c dt-bindings: clock: qcom,gcc-other: rename to qcom,mdm-mdm9607 
The only platform remaining in qcom,gcc-other.yaml is MDM9607. Drop the
stale mentioning of gcc-msm8953.h include and rename the schema file
accordingly.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240529-qcom-gdscs-v2-1-69c63d0ae1e7@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-05-31 18:07:30 -05:00
Taniya Das
63aec3e4d9 clk: qcom: camcc-sc7280: Add parent dependency to all camera GDSCs 
Camera titan top GDSC is a parent supply to all other camera GDSCs. Titan
top GDSC is required to be enabled before enabling any other camera GDSCs
and it should be disabled only after all other camera GDSCs are disabled.
Ensure this behavior by marking titan top GDSC as parent of all other
camera GDSCs.

Fixes: 1daec8cfeb ("clk: qcom: camcc: Add camera clock controller driver for SC7280")
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240531095142.9688-4-quic_tdas@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-05-31 17:52:47 -05:00
Taniya Das
f38467b5a9 clk: qcom: gcc-sc7280: Update force mem core bit for UFS ICE clock 
Update the force mem core bit for UFS ICE clock to force the core on signal
to remain active during halt state of the clk. When retention bit of the
clock is set the memories of the subsystem will retain the logic across
power states.

Fixes: a3cc092196 ("clk: qcom: Add Global Clock controller (GCC) driver for SC7280")
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240531095142.9688-3-quic_tdas@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-05-31 17:52:47 -05:00
Taniya Das
7f10197853 clk: qcom: sc7280: Update the transition delay for GDSC 
Add support to update the GDSC transition delay values to avoid
the GDSC FSM state stuck issues without which it could lead to GDSC
power on/off failures.

Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240531095142.9688-2-quic_tdas@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-05-31 17:52:47 -05:00
Alexandru Gagniuc
a8fe85d40f clk: qcom: gcc-ipq9574: Add PCIe pipe clocks 
The IPQ9574 has four PCIe "pipe" clocks. These clocks are required by
PCIe PHYs. Port the pipe clocks from the downstream 5.4 kernel.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240501040800.1542805-3-mr.nuke.me@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-05-28 16:17:01 -05:00
Alexandru Gagniuc
475beea0b9 dt-bindings: clock: Add PCIe pipe related clocks for IPQ9574 
Add defines for the missing PCIe PIPE clocks.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240501040800.1542805-2-mr.nuke.me@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-05-28 16:17:01 -05:00
Danila Tikhonov
aa9fc5c908 clk: qcom: Add Video Clock Controller driver for SM7150 
Add support for the video clock controller found on SM7150.

Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Link: https://lore.kernel.org/r/20240505201038.276047-9-danila@jiaxyga.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-05-27 12:01:56 -05:00
Danila Tikhonov
a4be1860b9 dt-bindings: clock: qcom: Add SM7150 VIDEOCC clocks 
Add device tree bindings for the video clock controller on Qualcomm
SM7150 platform.

Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20240505201038.276047-8-danila@jiaxyga.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-05-27 12:01:56 -05:00
Danila Tikhonov
9f0532da42 clk: qcom: Add Camera Clock Controller driver for SM7150 
Add support for the camera clock controller found on SM7150.

Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Link: https://lore.kernel.org/r/20240505201038.276047-7-danila@jiaxyga.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-05-27 12:01:56 -05:00
Danila Tikhonov
0fd2a04836 dt-bindings: clock: qcom: Add SM7150 CAMCC clocks 
Add device tree bindings for the camera clock controller on Qualcomm
SM7150 platform.

Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20240505201038.276047-6-danila@jiaxyga.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-05-27 12:01:56 -05:00
Danila Tikhonov
3829c41219 clk: qcom: Add Display Clock Controller driver for SM7150 
Add support for the display clock controller found on SM7150.

Co-developed-by: David Wronek <david@mainlining.org>
Signed-off-by: David Wronek <david@mainlining.org>
Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Link: https://lore.kernel.org/r/20240505201038.276047-5-danila@jiaxyga.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-05-27 12:01:56 -05:00
Danila Tikhonov
ca3a91063a dt-bindings: clock: qcom: Add SM7150 DISPCC clocks 
Add device tree bindings for the display clock controller on Qualcomm
SM7150 platform.

Co-developed-by: David Wronek <david@mainlining.org>
Signed-off-by: David Wronek <david@mainlining.org>
Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20240505201038.276047-4-danila@jiaxyga.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-05-27 12:01:55 -05:00
Danila Tikhonov
734b6e7a3b clk: qcom: gcc-sm7150: constify clk_init_data structures 
The clk_init_data structures are never modified, make them const.

No functional changes.

Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Link: https://lore.kernel.org/r/20240505201038.276047-3-danila@jiaxyga.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-05-27 12:01:55 -05:00
Danila Tikhonov
97cf92963a clk: qcom: Fix SM_GCC_7150 dependencies 
Add dependencies on "ARM64 or COMPILE_TEST" for SM_GCC_7150.

Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Link: https://lore.kernel.org/r/20240505201038.276047-2-danila@jiaxyga.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-05-27 12:01:55 -05:00
Christophe JAILLET
fcd9354ceb clk: qcom: Constify struct pll_vco 
pll_vco structure are never modified. They are used as .vco_table in
"struct clk_alpha_pll".

And in this structure, we have:
	const struct pll_vco *vco_table;

Constifying these structures moves some data to a read-only section, so
increase overall security.

On a x86_64, with allmodconfig:
Before:
   text	   data	    bss	    dec	    hex	filename
   9905	  47576	      0	  57481	   e089	drivers/clk/qcom/mmcc-msm8994.o

After:
   text	   data	    bss	    dec	    hex	filename
  10033	  47440	      0	  57473	   e081	drivers/clk/qcom/mmcc-msm8994.o

Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/c3c9a75ed77a5ef2e9b72081e88225d84bba91cd.1715359776.git.christophe.jaillet@wanadoo.fr
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-05-27 11:45:04 -05:00
Dmitry Baryshkov
d85dc696ca dt-bindings: clk: qcom,dispcc-sm8x50: describe additional DP clocks 
On the affected Qualcomm platforms the display clock controller has
additional DP input clocks, describe them in DT schema.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240512-typec-fix-sm8250-v4-1-ad153c747a97@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-05-27 11:43:57 -05:00
Jeff Johnson
65424b99a1 clk: qcom: add missing MODULE_DESCRIPTION() macros 
Fix the following from 'make W=1' with allmodconfig:

WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/clk/qcom/clk-qcom.o
WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/clk/qcom/gcc-msm8976.o
WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/clk/qcom/lpass-gfm-sm8250.o
WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/clk/qcom/videocc-sdm845.o

Signed-off-by: Jeff Johnson <quic_jjohnson@quicinc.com>
Link: https://lore.kernel.org/r/20240516-qcom-clk-md-v1-1-baca27dd2fb2@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-05-26 22:13:01 -05:00
Linus Torvalds
1613e604df Linux 6.10-rc1 v6.10-rc1 2024-05-26 15:20:12 -07:00
Kent Overstreet
9b0abe7948 mm: percpu: Include smp.h in alloc_tag.h 
percpu.h depends on smp.h, but doesn't include it directly because of
circular header dependency issues; percpu.h is needed in a bunch of low
level headers.

This fixes a randconfig build error on mips:

  include/linux/alloc_tag.h: In function '__alloc_tag_ref_set':
  include/asm-generic/percpu.h:31:40: error: implicit declaration of function 'raw_smp_processor_id' [-Werror=implicit-function-declaration]

Reported-by: kernel test robot <lkp@intel.com>
Fixes: 24e44cc22a ("mm: percpu: enable per-cpu allocation tagging")
Closes: https://lore.kernel.org/oe-kbuild-all/202405210052.DIrMXJNz-lkp@intel.com/
Signed-off-by: Kent Overstreet <kent.overstreet@linux.dev>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
 2024-05-26 14:40:39 -07:00
Linus Torvalds
6fbf71854e Merge tag 'perf-tools-fixes-for-v6.10-1-2024-05-26' of git://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools 
Pull perf tool fix from Arnaldo Carvalho de Melo:
 "Revert a patch causing a regression.

  This made a simple 'perf record -e cycles:pp make -j199' stop working
  on the Ampere ARM64 system Linus uses to test ARM64 kernels".

* tag 'perf-tools-fixes-for-v6.10-1-2024-05-26' of git://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools:
  Revert "perf parse-events: Prefer sysfs/JSON hardware events over legacy"
 2024-05-26 09:54:26 -07:00