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clk: qcom: gcc-sc7280: Update force mem core bit for UFS ICE clock

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Update the force mem core bit for UFS ICE clock to force the core on signal
to remain active during halt state of the clk. When retention bit of the
clock is set the memories of the subsystem will retain the logic across
power states.

Fixes: a3cc092196 ("clk: qcom: Add Global Clock controller (GCC) driver for SC7280")
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240531095142.9688-3-quic_tdas@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Taniya Das
2024-05-31 15:21:41 +05:30
committed by Bjorn Andersson
parent 7f10197853
commit f38467b5a9
1 changed files with 3 additions and 0 deletions
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3
drivers/clk/qcom/gcc-sc7280.c
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@@ -3473,6 +3473,9 @@ static int gcc_sc7280_probe(struct platform_device *pdev)
qcom_branch_set_clk_en(regmap, 0x71004);/* GCC_GPU_CFG_AHB_CLK */
regmap_update_bits(regmap, 0x7100C, BIT(13), BIT(13));
/* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
ARRAY_SIZE(gcc_dfs_clocks));
if (ret)