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drm/amd/display: Delete dm_pp_clocks_state

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It isn't used by anything anymore.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Melissa Wen <mwen@igalia.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Timur Kristóf
2026-05-19 12:21:12 +02:00
committed by Alex Deucher
parent ea25284d09
commit ff3af5416a
1 changed files with 0 additions and 23 deletions
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23
drivers/gpu/drm/amd/display/dc/dm_services_types.h
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@@ -36,30 +36,7 @@ struct dm_pp_clock_range {
int max_khz;
};
enum dm_pp_clocks_state {
DM_PP_CLOCKS_STATE_INVALID,
DM_PP_CLOCKS_STATE_ULTRA_LOW,
DM_PP_CLOCKS_STATE_LOW,
DM_PP_CLOCKS_STATE_NOMINAL,
DM_PP_CLOCKS_STATE_PERFORMANCE,
/* Starting from DCE11, Max 8 levels of DPM state supported. */
DM_PP_CLOCKS_DPM_STATE_LEVEL_INVALID = DM_PP_CLOCKS_STATE_INVALID,
DM_PP_CLOCKS_DPM_STATE_LEVEL_0,
DM_PP_CLOCKS_DPM_STATE_LEVEL_1,
DM_PP_CLOCKS_DPM_STATE_LEVEL_2,
/* to be backward compatible */
DM_PP_CLOCKS_DPM_STATE_LEVEL_3,
DM_PP_CLOCKS_DPM_STATE_LEVEL_4,
DM_PP_CLOCKS_DPM_STATE_LEVEL_5,
DM_PP_CLOCKS_DPM_STATE_LEVEL_6,
DM_PP_CLOCKS_DPM_STATE_LEVEL_7,
DM_PP_CLOCKS_MAX_STATES
};
struct dm_pp_gpu_clock_range {
enum dm_pp_clocks_state clock_state;
struct dm_pp_clock_range sclk;
struct dm_pp_clock_range mclk;
struct dm_pp_clock_range eclk;