From ff3af5416ac72419df601ba056a6c297bcd0bd2b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Tue, 19 May 2026 12:21:12 +0200 Subject: [PATCH] drm/amd/display: Delete dm_pp_clocks_state MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It isn't used by anything anymore. Acked-by: Christian König Signed-off-by: Timur Kristóf Reviewed-by: Melissa Wen Signed-off-by: Alex Deucher --- .../drm/amd/display/dc/dm_services_types.h | 23 ------------------- 1 file changed, 23 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dm_services_types.h b/drivers/gpu/drm/amd/display/dc/dm_services_types.h index f114ab819afd..b3505d93503f 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_services_types.h +++ b/drivers/gpu/drm/amd/display/dc/dm_services_types.h @@ -36,30 +36,7 @@ struct dm_pp_clock_range { int max_khz; }; -enum dm_pp_clocks_state { - DM_PP_CLOCKS_STATE_INVALID, - DM_PP_CLOCKS_STATE_ULTRA_LOW, - DM_PP_CLOCKS_STATE_LOW, - DM_PP_CLOCKS_STATE_NOMINAL, - DM_PP_CLOCKS_STATE_PERFORMANCE, - - /* Starting from DCE11, Max 8 levels of DPM state supported. */ - DM_PP_CLOCKS_DPM_STATE_LEVEL_INVALID = DM_PP_CLOCKS_STATE_INVALID, - DM_PP_CLOCKS_DPM_STATE_LEVEL_0, - DM_PP_CLOCKS_DPM_STATE_LEVEL_1, - DM_PP_CLOCKS_DPM_STATE_LEVEL_2, - /* to be backward compatible */ - DM_PP_CLOCKS_DPM_STATE_LEVEL_3, - DM_PP_CLOCKS_DPM_STATE_LEVEL_4, - DM_PP_CLOCKS_DPM_STATE_LEVEL_5, - DM_PP_CLOCKS_DPM_STATE_LEVEL_6, - DM_PP_CLOCKS_DPM_STATE_LEVEL_7, - - DM_PP_CLOCKS_MAX_STATES -}; - struct dm_pp_gpu_clock_range { - enum dm_pp_clocks_state clock_state; struct dm_pp_clock_range sclk; struct dm_pp_clock_range mclk; struct dm_pp_clock_range eclk;